04 Com Bi National Logic Part2

8/3/2019 04 Com Bi National Logic Part2

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1

Combinational-circuit synthesis• Problem (in word description)

• Design circuit (circuit description)• Circuit minimization

• Circuit realization (logic circuit, simulation,function and timing analysis,implementation)



2

Circuit description and design• Circuit description:

– A list of input combinations for which a signalshould be on or off (design a 4-bit prime number detector)

– Verbal equivalent of a truth table (given N=N 0 N 1N 2 N 3 , produce a 1 if N=1,2,3,5,11,13,and 0 otherwise)

– A ∑ or π notation



3

Circuit description and design

• Circuit description:



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Circuit Manipulations• Translate logic function into an equivalent sum-of-

product expression (by simply multiplying out)

Convert into sum-of-product



5

Circuit Implementation• Insert a pair of inverters between each AND-gate

output and corresponding OR-gate input in a two-

level AND-OR circuit

NAND



6

Circuit Implementation• If any product terms in the sum-of-products

expression contain just one literal, we may lose or

gain inverters in the transformation from AND-OR toNAND-NAND.

gain

lose



7

Circuit Manipulations• Any sum-of-products expression can be realized as AND-OR circuit or as NAND-NAND circuit.

• Any product-of-sum expression can be realized as OR-AND circuit or as NOR-NOR circuit.



8

Circuit Minimization• Reducing the number and size of gates needed to build the circuit.

• Reducing the cost of a two-level AND-OR, OR-AND,NAND-NAND, NOR-NOR

• Minimize the number of first-level gate

• Minimize the number of inputs on each first-level gate

• Minimize the number of inputs on the second-level gate

• Based on T10 and T10’.

( (



9

Karnaugh maps

• Graphical representation of a logic function’s truth table.

• Copy 1s and 0s from the truth table to the

corresponding cells of the map.



10

Karnaugh maps

• Examples.

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‘



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Karnaugh maps• Example

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‘

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‘



12

Karnaugh maps• Example



13

Karnaugh maps• Example: prime number detector



14

Karnaugh maps

• Example: prime number detector

Karnaugh map minimization

Canonical-sum design



15

Karnaugh maps

• More examples



16

Timing hazards

• Static hazards :

– Static-1 hazard is a pair of input combinations that: (a)

differ in only one input variable and (b) both give a 1output; such that it is possible for a momentary 0 output to occur during a transition in the different input variable.



17

Timing hazards

• Finding static hazards using maps:

– The existence or non-existence of hazard depends on

circuit design for a logic function.

Originaldesign

Static-1

hazardeliminated



18

Timing hazards

• Static hazards :

– Static-0 hazard is a pair of input combinations that: (a)

differ in only one input variable and (b) both give a 1output; such that it is possible for a momentary 1 output to occur during a transition in the different input variable.



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Timing hazards

• Dynamic hazards :

– Is a possible of an output changing more than once as

the result of a single input transition. Multiple output transitions can occur if there are multiple paths with different delays from the changing input to the changing output.

04 Com Bi National Logic Part2

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