02_CodingStyle

8/3/2019 02_CodingStyle

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http://larc.ee.nthu.edu.tw/~hp/EE4292/

Department of Electrical EngineeringNational Tsing Hua University


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Thanks for Verilog slides from Prof. Chih-TsunHuang.

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Michael Keating and Pierre Bricaud,Reuse Methodology Manual,Kluwer Academic Publishers, Third Ed., 2002

M. Morris Mano,Digital Design, 3rd edition, 2002.

Guide to HDL Coding Styles for Synthesis, SOLD.

Preparing Design Files for Synthesis(Chapter 3 in DesignCompiler User Guide), SOLD.

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Simple and regular

Use simple constructs and simple clocking schemes

Consistent coding style, consistent naming and state

machines Regular partitioning scheme

Easy to understand by comments and meaningfulnames. No hard coded number

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Focus

Keep critical path within a module

All module outputs are registered

Module Well-selected the gate count number within a module

(250 - 5000)

Prepare to reuse hierarchical modules

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Guideline

For each subblock of a hierarchical macro design,register all output signals from the subblock.

Subblock 1Subblock 2

Block A


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Guideline

Keep related combinational logic together in the samemodule

Design Compiler must preserve port definitions.

Logic optimization cannot cross block boundaries

Path from Reg A to Reg C may be larger andslower than necessary.


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Related combinational logic is grouped into oneblock.

Sequential optimization may absorb some of thecombinational logic into a more complex flip-flop.(Best) (JK, T, Muxed, Clock-enabled,)

Better Best


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Module A

Critical Path

LogicRegA

Module B

Non-critical

Path LogicRegB

Speed Optimization

Area Optimization


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Focus

Explicit specify the separate assignment

Make use of the parentheses

Modeling Build the design as your knowledge

Dont rely on CAD tools

Separated combinational and sequential logic blocks

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Using general naming conventions consistently

Document the naming convention

Use lowercase letters for all signal names, variablenames, and port names.

Use uppercase letters for names of constants and user-defined types.

Use meaningful names for signals, ports, andparameters.

Do not use ra for a RAM address bus, but use ram_addr.

Use a consistent name for the clock signal, such as clk. If there is more than one clock, use clkas the prefix for all

clock signals. (clk1, clk2, clk_interface).


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Using general naming conventions consistently

Use the same name for all clock signals that are drivenfrom the same source.

For active-low signals, end the signal with an

underscore followed by a lowercase character (_b, _n)

Use a consistent name for reset signals, such as rst. Ifthe reset signal is active-low, use a name like, rst_n.

When describing multibit buses, use a consistent

ordering bits. Use [x:0] for Verilog, (x downto 0) forVHDL.

When possible, use the same name or similar namesfor ports and signals that are connected.

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Using Named and Positional Association

Incorrect

BUFGS CLK_1 (.I(CLOCK_IN), CLOCK_OUT);

Correct BUFGS CLK_1 (.I(CLOCK_IN), .O(CLOCK_OUT));


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Port maps and generic maps Rule

Always use explicit mapping for ports and generics, using namedassociation rather than positional association.

DW_ram_r_w_s_dff

#((`ram_data_width+`ram_be_data_width),

(`fifo_depth),1)U_int_txf_ram (

.clk (refclk),

.rst_n (txfifo_ram_reset_n),

.cs_n (1b0),

.wr_n (txfifo_wr_en_n),

.rd_addr (txfifo_rd_addr),

.wd_addr (txfifo_wr_addr),

.data_in(txfifo_wr_data),

.data_out (txf_ram_data_out)

)


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Guideline

Do not use hard-codednumeric values.

Advantages using constants

Constants are more intelligibleas they associate a designintension with the value.

Constant values can bechanged in one place.

Compilers can spot typos inconstants but not in hard-

coded values.

wire [7:0] my_in_bus;

reg [7:0] my_out_bus;

`define MY_BUS_SIZE 8

wire [`MY_BUS_SIZE-1:0] my_in_bus;

reg [`MY_BUS_SIZE-1:0] my_out_bus;

Poor coding style

Recommended coding style


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Guideline

Keep constant and parameters definitions in one or asmall number of files with names such as

DesignName_constants.v orDesignName_parameters.v


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Use constants in your design to substitute numbers tomore meaningful names.

The use of constants helps make a design more readableand portable.


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Rule

Include a commented, informational header at the top of

every source file, including scripts.

Legal statement: confidentiality, copyright, restrictions on

reproduction

Filename

Author

Description of function and list of key features of the module.

Date the file was created

Modification history, including date, name of modifier, and descriptionof the change


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Rule

Use comments appropriately to explain processes,functions, and declarations of types and subtypes.

Guideline Use comments to explain ports, signals, and variables,

or group of signals or variables.


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Rule

Use a separate line for each HDL statement.

More readable and maintainable.


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Line length guideline Keep the line length to 72 characters or less.

Indentation guidelines

Use indentation of 2 spaces. Larger indentationrestricts line length when there are several levels ofnesting.

Avoid of using tabs. Differences in editors and usersetups make the positioning of tabs unpredictable and

corrupt the intended indentation.


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Rule Declare ports in a logical order, and keeps this order consistent throughout

the design

Guidelines

Declare one port per line, with a comment following it (preferably on thesame line)

For each instance, declare the ports in the following order

Inputs Clocks

Resets

Enables

Other control signals

Data and address lines

Outputs Clocks

Resets Enables

Other control signals

Data

Use comments to describe groups of ports.


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Omit the Wait for XX ns Statement

Do not use #XX;

Omit the ...After XX ns or Delay Statement

Do not use assign #XX Q=0; Omit Initial Values

Do not use initial sum = 1b0;

Order and Group Arithmetic Functions

ADD = A1 + A2 + A3 + A4; ADD = (A1 + A2) + (A3 + A4); Not equivalent!

Ignore by synthesizer


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If statement vs. Case statement

If statement

Priority-encoded logic

For speed critical path Case statement

Balanced logic

For complex decoding


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Consideration when writing If statement Make sure that all outputs are defined in all branches

of an if statement. If not, it can create latches or long equations on the CE signal.

A good way to prevent this is to have default values for alloutputs before the if statements.

Limiting the number of input signals into an ifstatement can reduce the number of logic levels. If there are a large number of input signals, see if some of

them can be pre-decoded and registered before the ifstatement.

Avoid bringing the dataflow into a complex ifstatement. Only control signals should be generated in complex if-else

statements.


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Default value


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REG BREG A

COMB

COMB COMB

REG BREG A

COMB

COMB

COMB

Bad : Combinational processes are looped.

Good : Combinational processes are not looped.


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Rule

Include a complete sensitivity list in each of youralways blocks.

always @(a)

c


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Avoid using both positive- and negative-edgeclocks

Post problem for timing analysis

Problems for scan Separate pos and neg FFs in different modules

Avoid clock buffers in synthesis

Avoid gated clock

Avoid internally generated clocks

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Syntax error for Verilog Simulator

Mixed edge-triggered and level-sensitivecontrol in an always block

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Either non-synthesizable or incorrect after synthesis initial block is forbidden (non-synthesizable)

Multiple assignments (multiple driving sources)

(non-synthesizable)

Mixed blocking and non-blocking assignment

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Explicit FSM design

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Asynchronous reset Entering the reset state asynchronously, but leaving

synchronous

Synchronous reset

Similar to an enable signal

entering and leaving the reset state synchronously

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No initial in the RTL code

FFs are preferred

Avoid unnecessary latches

Avoid combinational feedback

For sequential blocks, use no-blocking statements

For combinational blocks, use blocking statements

Coding state machines

Two procedure blocks: one for the sequential and one for the

combinational Keep FSM logic and non-FSM logic in separate modules

Assign a default state

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