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A Flexible ADC Approach for Mixed-signal SoC

Platforms

Athon Zanikopoulos, Pieter Harpe, Hans Hegt and Arthur van Roermund

Mixed-signal Microelectronics Group, Eindhoven University of Technology,

Eindhoven, The Netherlands, email: a.zanikopoulos@tue.nl

Abstract Time-to-market pressure and increased design com-plexity created what is called a design gap [1] in the de-sign of systems-on-chip (SoC). As a solution to that problemthe Platform-Based Design (PBD), based on the design-reusemethodology, has been proposed [2], and successfully appliedto digital systems. However, nowadays, the analog part of SoCdoes not take advantage of PBD and therefore dominates theoverall design time, cost and risk. In this paper we proposea Mixed-signal FPGA (FPMA) platform as a solution to theproblems described above. Specifically, we address the feasibility

of a flexible reprogrammable/reconfigurable ADC platform basedon the pipelined architecture. We discuss the programmabilityissues with respect to the performance-flexibility trade-offs, we

justify our decisions and we demonstrate several possible ADCarchitectures.

I. INTRODUCTION

Every year IC technology provides a higher transistor

density, increasing approximately with 60% per year. The

designers cannot keep pace with that because the design

efficiency (engineering skills, productivity of tools and meth-

ods) is increasing with only approximately 20% per year [1].

Furthermore, time-to-market pressure and cost of ownership of

masks drives us to more disciplined design styles, employing

design reuse from gate level up to IP block level.

However, as the complexity of the IC designs increases con-

tinuously (above 100million transistors) and time-to-market

becomes even more important, a new, more advanced and

abstract, reuse methodology becomes imperative. Therefore,

as a natural progression of this line of thinking, the Platform-

Based Design (PBD) has been proposed [3]. It is a new

design reuse methodology based on architecture reuse. A

platform is a library of components that can be assembled

to generate a design at that level of abstraction. We call a

platform instance a set of components that are selected from

the library and whose parameters are set. Platforms allow

design reuse from the functional level down to the circuitand layout level and, finally, real hardware level reuse. We

can address the FPGAs (Field-Programmable Gate Arrays) as

the most successful example of a platform that includes full

hardware reuse. FPGAs are digital systems and the physical

layer can be decoupled from the functional layer.

In parallel with the design reuse methodology evolution, the

recent rapid progress of integrated circuit technology allows

the integration of a whole System on a single Chip. The

The work is sponsored by Stichting Technische Wetenschappen.

SoC trend finally implies the single-chip integration of analog

and digital functions. Especially with the rise of the Personal

Internet Products (PIPs), such as cable modems, ADSL, cell

phones, PDAs etc, this becomes even more indispensable,

because most of the PIPs have a real-time analog input and/or

analog output [4].

However, this SoC trend interferes with the design reuse and

the PBD methodology, because analog/mixed-signal platforms

are hardly available yet and as a consequence the design ofthe analog part dominates the design time, cost and risk. The

fundamental reason for this is that in the analog case the

physical effects have significant influence on the performance

and functionality of the system and the physical layer cannot

be decoupled from the functional layer. Moreover, the low-

voltage environment of the digital CMOS technologies, along

with the absence of components, such as capacitors, resistors,

with good analog characteristics, prevents the transferring of

existing analog designs to digital technologies. Therefore, we

should adopt a new approach that utilizes the benefits of the

low voltage, high speed and low cost digital logic.

Taking into account the PBD necessity and the SoC trend,

we propose a way to implement an analog platform for ADCsin a FPGA, constructing a FPMA. The design complexity will

be hidden from the end user, who, via a software interface, will

be able to configure the hardware in conformity with his/her

needs. The implementation of the analog platform in the FPGA

gives us the possibility to employ the benefits of the existing

digital correction methods that can be implemented in a FPGA.

Existing developments in the direction of flexible or

programmable ADCs are based on either FPAA (Field-

Programmable Analog Arrays) with high granularity which

offer high flexibility but low performance [5], [6] or recon-

figurable ADC solutions with limited coverage of resolution

range [7], [8]. We aim to cover the range of resolutions from

8bits up to 14bits with optimum speed, using a flexible ADCplatform. The following graph (fig. 1) gives a picture of our

target related to other popular ADC architectures.

I I . THE PROPOSED SOLUTION

A. The Flexible Matrix

Several designs have proven that the pipelined architecture

is one of the most successful architectures for high-speed,

low-power analog-to-digital conversion. It provides high mod-

ularity and regularity and it is the most suitable for telecom

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Resolution (bits)

ConversionRate(MSPS)

6 8 10 12 14 16 18 20

1

10

20

50

100

200

500

1E3

2E3

Flash Folding/Interpolation

Pipelined

SAR

Flexible ADC Target

Fig. 1. Flexible ADC target

applications, which are the main focus of the FPGAs users.

Moreover, it is a mature architecture, very well documented

and it allows many (analog and/or digital) techniques to

enhance its performance.

Therefore, we propose a realization of a flexible repro-

grammable/reconfigurable ADC based on the pipelined archi-tecture. Figure 2 depicts our proposal with a 6x6 matrix of

basic blocks [patent filed]. Our idea is not restricted only to

those matrix dimensions, but we can easily employ smaller or

larger dimensions, according to our needs.

S/H

Fig. 2. Flexible reconfigurable matrix composed of BBs

A number of identical basic blocks (BB) and an inter-

connection network construct our matrix. Moreover, for the

functionality of the structure is necessary at least one front-

end S&H.

Every second row of the matrix is flipped in the layout,

as indicated by the arrow, which allows closest neighborsconnectivity to keep the interconnection lines as short as

possible and, hence, to increase the analog signal integrity

and to ease the routing of the analog lines.

We try to keep the number of switches to minimum, and

even more important, to minimize their effect on the analog

signal quality. For that reason, we choose to use a fully

hardwired BB with only the essential for its operation internal

switches (not shown in fig. 2). The external switches are in

general used only for the interconnections of the blocks, which

during the normal operation of the ADCs do not change state,

except for some special situations mentioned below.

This converter architecture provides means to achieve par-

allelization along different axes, such as time parallelization,

hardware parallelization and algorithm parallelization.

According to the dimensions and the target utilization of

the matrix, it is necessary to integrate a number of front-end

Sample and Hold (S&H) circuits. At least one S&H should

comply with the maximum desirable resolution

The BBs that are not in use during the operation can be

switched-off to save power

B. The Basic Block (BB)

The matrix consists of basic blocks and an interconnection

network. The arrow on each BB points into the signal direction

of the cell. A BB is composed of a flash sub-ADC, a sub-DAC,

a subtraction block and a Sample and Hold (S&H) amplifier.

1 .5b

MDAC

S & H A m p

A n a l o g

i n p u tx2

+

-

s u b - AD C s u b -D AC

Residue

Fig. 3. Internal view of a basic block (BB)

Usually, the functions of digital-to-analog conversion, sub-

traction and S&H amplification are implemented in one single

circuit called multiplying DAC (MDAC) [9]. Typically, a

closed-loop switched-capacitor realization of that circuit is

employedWe use identical BBs for the whole structure. The resolution

of every block is equal to 1.5bit, which means an effective

resolution of 1bit plus 0.5bit reserved for digital correction

[9]

This choice improves the modularity and flexibility of the

matrix allowing many combinations, while at the same time

it ensures robustness. Furthermore, the use of a single block

minimizes design risk and time and allows easier IP-reuse

The implementation of this matrix into a high-performance

FPGA permits extensive use of digital correction algorithms.

We propose the use of three distinct correction methods:

- Digital correction [9], which employing bit redundancy

(0.5bit in our case), greatly relaxes the sub-ADCs com-parators offset specifications;

- Digital calibration [10], which employing stage redun-

dancy, corrects offset and linear errors in sub-DAC,

residue amplifier and S&H stage;

- Digital non-linearity calibration [11], which using a

digital algorithm, corrects static non-linearities, in the

residue amplifier and S&H stage.

Using the above techniques, we essentially translate the analog

precision problem into the digital domain. This is in line with

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the trend of the new digital technologies that offer high speed,

but worse voltage resolution. Furthermore, the digital systems

become smaller and cheaper, while the analog counterparts

suffer from the low voltage environment. Therefore, several

advantages arise due to the translation of the analog problems

to the digital domain. We expect potential power savings

and/or speed improvements and it may help to overcome future

scaling problems.

It is clear that the above-mentioned correction methods relax

the analog design and especially the non-linearity calibration

algorithm allows us to use an open-loop residue amplifier,

instead of the standard closed-loop realization. The potential

of open-loop structures for high-speed applications has been

demonstrated [12], as well as the capability to achieve lower

power dissipation for specific speed, [11]. Furthermore, we

can employ a frequency-to-voltage (f/V) or a frequency-to-

current (f/I) converter to sense the clock frequency and to

adjust automatically the bias current of the amplifiers to the

smallest value that is necessary for the stages to settle to

the appropriate level, as to keep the power consumption to

a minimum level.III. SEVERAL CONFIGURATIONS OF THE MATRIX

The matrix of figure 2 gives us the possibility to combine

the blocks in several ways to implement different analog-

to-digital algorithms (serial or parallel) with extensive time

and hardware parallelization. A number of possibilities is

illustrated below.

A. One or More Standalone Pipelined ADCs

Figure 4 shows the proposed implementation of a standalone

pipelined ADC. We indicate with solid lines the BBs that are

active and the switches that are constantly on and with dashed

lines the inactive BBs and the turned-off switches.

S/H

Fig. 4. Standalone pipelined ADC

By connecting or disconnecting BBs we can respectively

increase or decrease the resolution of the ADC.

In this case, we have parallel simultaneous operating hard-

ware, in different time slots, employing a serial algorithm.

The matrix gives us the possibility to implement more than

one standalone pipelined ADC, depending on the size of the

matrix and the number of available S&Hs.

B. One or More Time-Interleaved ADCs

Figure 5 depicts a proposed implementation of a three

channel Time-Interleaved (TI) ADC on the matrix. This con-

figuration aims for high speed applications.

As one can see, our matrix gives the possibility to use less

or more BBs in series, providing flexibility in the resolution

of the converter.

S1S/H

S2

S3

Fig. 5. Time-Interleaved ADC

The front-end S&H is clocked three times faster than a

single BB. The active BBs and the turned-on switches are

indicated with solid lines, and the inactive BBs and the turned-

off switches with dashed lines. The switches S1, S2 and S3take actively part in the functionality of the TI ADC, since

they implement an analog demultiplexer.

In this case, we have parallel simultaneous operating hard-

ware, in different time slots, employing a parallel algorithm.

Like in the case of the pipelined configuration, we can

implement more that one time-interleaved ADC dependent on

the size of the matrix and the available S&Hs.

C. Cyclic ADC

The configuration of the matrix that allows the realization

of a cyclic converter, aiming for high resolution, low speed

and low power applications, is shown in the following figure.

S1S/H

S2

Fig. 6. Cyclic ADC

We use only two BBs and a front-end S&H while the rest

of the BBs are switched off (dashed BBs). The switches S1

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and S2 take active part in the implementation of the cyclic

algorithm.

This realization of the cyclic converter has some differences

from the typical case [13]. The main deviation from the typical

case is that we use two blocks instead of one, because when

the analog output of a BB is valid, the same BB cannot sample

this output. Another difference is that we use 1.5bit per block,

instead of just 1bit.

The front-end switch (S1) switches on, the first BB samples

the output of the S&H, and then the switch in parallel with

the BBs (S2) turns on and remains on until we resolve the

complete digital word. Subsequently, S2 goes off and S1 turns

on to provide a new sample from the S&H.

In this case, we have the same hardware operating in

different time slots, employing a serial algorithm.

D. Pipelined ADC Employing Averaging

As for some applications, the input-referred thermal noise

is not one of the most crucial requirements (e.g. digital

imagers, etc), we can under-design our BBs with respect to

thermal noise. This approach allows the utilization of smaller

capacitors and saves power and area, since the size of thecapacitors increases four times for every additional bit of

accuracy.

However, for applications where the noise is of high

concern, our matrix gives us the possibility to lower the

input-referred noise, employing noise averaging at the analog

outputs of the BBs, as shown in fig. 7.

S/H

Fig. 7. Standalone pipelined ADC employing averaging

In this configuration, we have parallel simultaneous op-

erating hardware. A part of the hardware (averaging BBs)

operates in the same time slot, while the rest of it operates in

different time slots, employing a serial algorithm.Depending on the size of the matrix and the accuracy

requirements, we can use different numbers of parallel-

connected BBs.

Using averaging in the pipelined architecture, we aim for

high accuracy applications.

IV. CONCLUSIONS

In this line of work, the feasibility of a flexible ADC matrix,

based on a single building block and an interconnection net-

work, has hereby been demonstrated and published for the first

time. We have paid extra attention on implementing flexibility

with minimal loss of performance. Several configurations have

been shown, aiming for different performance requirements.

The Time-Interleaved ADC configuration aims for high-speed

applications, the pipelined ADC employing averaging aims for

high accuracy, the cyclic ADC aims for low power and finally,

the standalone pipelined ADC covers the middle performance

space. Therefore, the presented structure provides flexibility

along many different axes, such as accuracy, speed and power

consumption and we are able to cover the performance area

pictured in fig. 1.

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