IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 10, OCTOBER 1999 1487

Fault Emulation: A New Methodologyfor Fault Grading

Kwang-Ting Cheng,Senior Member, IEEE, Shi-Yu Huang, and Wei-Jin Dai

Abstract—In this paper, we introduce a method that uses thefield programmable gate array (FPGA)-based emulation systemfor fault grading. The real-time simulation capability of a hard-ware emulator could significantly improve the performance offault grading, which is one of the most time-consuming tasksin the circuit design and test process. We employ a serial faultemulation algorithm enhanced by two speed-up techniques. First,a set of independent faults can be injected and emulated at thesame time. Second, multiple dependent faults can be simulta-neously injected within a single FPGA-configuration by addingextra circuitry. Because the reconfiguration time of mappingthe numerous faulty circuits into the FPGA’s is pure overheadand could be the bottleneck of the entire process, using extracircuitry for injecting a large number of faults can reducethe number of FPGA-reconfigurations and, thus, improving theperformance significantly. In addition, we address the issue ofhandling potentially detected faults in this hardware emulationenvironment by using the dual-railed logic. The performanceestimation shows that this approach could be several orders ofmagnitude faster than the existing software approaches for largesequential designs.

Index Terms—Emulation, fault grading, foult simulation, test-ing.

I. INTRODUCTION

I N today’s quality-conscious very large scale integration(VLSI) world, measuring a design’s quality by the fault

coverage is considered essential. Usually, the fault coveragefigure is derived by fault simulation, which is a very time-consuming process. Very few existing software fault simulatorscan handle a design with more than 200 K gates withoutresorting to some design for testability (DFT) technique.Furthermore, even for those tools that can handle such adesign, the process is still very time consuming [13] and couldlengthen the time to market.

In recent years, a lot of effort has been put into thedevelopment of all kinds of parallel algorithms that can runfault simulation on machines ranging from coarse-graineddistributed system to massively parallel connection machine[4], [7], [8], [15], [17]. Their policies include distributinggates or distributing faults on multiple processing elements(PE’s), partitioning the fault simulation kernel, or doing the

Manuscript received July 6, 1998; revised January 13, 1999. This paperwas recommended by Associate Editor R. Aitken.

K.-T. Cheng is with the Department of Electrical and Computer Engineer-ing, University of California, Santa Barbara, Santa Barbara, CA 93106 USA(e-mail: timcheng@ece.ucsb.edu).

S.-Y. Huang is with the Department of Electrical Engineering, NationalTsing Hua University, HsinChu, Taiwan, R.O.C.

W.-J. Dai is with Quick-Turn Design System Inc., Mountain View, CA94043 USA.

Publisher Item Identifier S 0278-0070(99)07733-7.

fault simulation in a pipelined manner. Also, some algo-rithms [6], [10]–[12] using a zero-delay model along withsome efficient techniques have successfully handled very largesequential circuits. On the other hand, a special purposehardware accelerator for fault simulation [4] has also beendevised and implemented in a board that plugs into a SUNworkstation. In [1], a concurrent fault simulation algorithm ispartitioned into pipeline stages. Each part is performed by aprocessing element controlled by a dedicated microprogram.This approach, requiring a large number of memory chips,achieves an order of magnitude run-time speed up over aconventional software fault simulator. However, the aboveapproaches, either software or hardware, are still inefficientfor handling large sequential designs.

Logic emulation systems [4], [19] are now commerciallyavailable for fast prototyping, real-time operation, and logicverification. A logic emulator consists of both hardware andsoftware. It can automatically implement the function of agate-level design on a board composed of dozens of fieldprogrammable gate array (FPGA) chips. Even larger emulatorcan be built by integrating several FPGA boards. The softwareaided implementation process can be divided into two phases,circuit compilation and bitstream downloadingas shown inFig. 1. The circuit compilation process maps the given gate-level netlist into the FPGA-based format. It involves circuitpartitioning, placement and routing for FPGA’s. The out-put of the compilation process is a bitstream representingthe configuration for target implementation. The bitstreamis then downloaded into the FPGA-boards by programmingeach lookup table (LUT) that defines the function of eachconfigurable logic block (CLB), and the routing switch thatdefines the interconnection between CLB’s. After the bitstreamdownloading is completed, the system is ready for emula-tion. Usually a hardware emulation engine is used to assistthe emulation process. Given a set of test vectors and itscorrect responses, the emulation engine handles the processof applying the test vectors, collecting the output responses,and checking if any mismatch occurs between the outputresponses and the prestored correct responses. One test vectoris emulated for each clock cycle. A state-of-the-art logicemulator can implement a logic design with up to three-milliongates and operate at a speed of 100 KHz to several MHz[23]. Accordingly, it can emulate 100 K to several milliontest vectors per second, which is about 10 000–1 million timesfaster than the traditional software simulators.

A number of methods have been proposed to use a logicemulation system for fault grading. Wieleret al. [21] proposed

0278–0070/99$10.00 1999 IEEE

1488 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 10, OCTOBER 1999

Fig. 1. The synthesis process in the FPGA-based emulator.

a serial fault emulation algorithm that emulates one faultycircuit at a time sequentially. A similar idea was also adoptedby Burgun et al. [2]. In these methods, the implementationof each faulty circuit is constructed from the fault-free circuitbefore the emulation process through a technique called staticfault injection which requires partial reconfiguration of theemulator. The details of this technique will be reviewed inSection II-A. The major drawback of these algorithms lies inthe large amount of time spent in reconfiguration.

In this paper, we propose a new approach to performfault grading using a FPGA-based logic emulation system.Beyond the serial fault emulation, we introduce two techniquesto further enhance the performance. First, we exploit theindependence between faults to allow concurrent emulation.Second, we propose an efficient technique called dynamicfault injection to reduce the reconfiguration time. Through theinsertion of extra hardware to the circuit under fault grading,this technique allows for the emulation of multiple structuraldependent faults within a single configuration. A similar ideawas also independently developed by Wieleret al. [20]. Incomparison, the proposed technique has a much lower areaoverhead (22%) than the one proposed in [20] (18 times). Likea real chip, a hardware emulator cannot simulate the unknownlogic value “ ” properly. We will also discuss the impactof the lack of “ ” value in the fault emulation environmentand deal with this problem with a dual-railed logic. Relativelyspeaking, the proposed method could be faster than the onebased on a logic simulation machine as proposed in [7] and [8],especially for large circuits. Although the latter is capable ofperforming extremely fast logic evaluation, (e.g., 800 millionprimitive gates per second [8]), its performance is still highlysensitive to the size of the circuit. On the other hand, an FPGA-based emulation system is less sensitive to the circuit sizeand can simulate one input vector within one clock cycle forcircuits it can implement.

The rest of this paper is organized as follows. In Section II,we describe our enhanced serial fault emulation algorithm

Fig. 2. Serial fault emulation process.

and then give a performance estimation. In Section III, wepropose a dual-railed logic to handle the unknown logic valuein the hardware emulation system. In Section IV, we presentthe experimental results that analyze the area overhead due toour speed-up techniques.

II. FAULT EMULATION

A. Primitive Scenario

A serial fault emulation process is shown in Fig. 2. In thepreprocessing stage, the collapsed stuck-at fault list is gener-ated and the fault-free netlist is compiled and programmed intothe FPGA’s. Since the circuit partitioning algorithm used in thetechnology mapper for FPGA’s will probably duplicate part ofthe original netlist to minimize the amount of interconnection

CHENG et al.: FAULT EMULATION 1489

(a) (b)

Fig. 3. Static fault injection by changing the netlist of a CLB. The netlist(a) before fault injection and (b) after fault injection.

across FPGA-chips, a single stuck-at fault in the originalnetlist may correspond to a multiple stuck-at fault in theFPGA-implementation. Therefore, the fault list generated foremulation is, in general, a set of multiple stuck-at faults.After the preprocessing, the algorithm enters a loop. At eachiteration, one fault is selected for emulation. The target faultis first injected to the fault-free implementation to convert itinto a faulty-circuit. This requiresrecompilation (preparingthe new bitstream) andreconfiguration(reprogramming theFPGA’s through downloading the bitstream generated in therecompilation phase). Once the fault injection is complete, thetest sequence is applied. The output response is compared withthe prestored correct response. If any mismatch is observed,the target fault is declared as detected by the given testsequence. This iterative process continues until all faults areinjected and emulated once.

One issue that arises in the hardware fault emulation systembut not in the software approaches is how to inject a fault intothe implementation. In the software approaches, it involvesonly netlist manipulation and takes constant time. But in theemulation system, it will involve the modification of the targetFPGA implementation, which is referred to asreconfigurationor reprogramming. Any stuck-at fault can be injected bysimply changing the contents of the affected CLB’s [21]. Forexample, consider the CLB shown in Fig. 3(a). To inject thes.a.0 fault at signal, we can simply change its contents to theone shown in Fig. 3(b). No global recompilation is required.A stuck-at fault of multiplicity requires reprogramming of atmost CLB’s. With the information extracted at compilation-time, we can directly manipulate the corresponding bitstreamof those affected CLB’s and then download the modifiedportion into the FPGA-boards to inject a fault efficiently.Current FPGA’s architecture requires the reprogramming ofan entire chip even if only one CLB needs to be changed. Butboard-level partial reprogramming is possible. the emulationsystem of [23] contains the chip-addressing circuitry on theboard to direct the bitstream to any individual FPGA-chip. Asa result, it allows partial reprogramming in terms of one chipat a time. According to the Xilinx’s FPGA Databook [22], ittakes about several milliseconds to reprogram a chip. This isabout the cost to inject a fault in our system. In the future, ifpartial reprogramming can be done at the CLB level, injectinga static fault can be even cheaper.

The total run time for such a process consists of twomajor parts: 1) The recompilation and reconfiguration time.For each fault injection, certain amount of computation isrequired to derive the information regarding to what needsto be changed in the mapped FPGA’s. The time spent in

(a) (b)

Fig. 4. Illustration of the independent fault set. (a) Independent fault set and(b) dependent faults.

this computation is referred to as recompilation time. Thefollowing reconfiguration of the FPGA’s also takes some time,which is referred to as reconfiguration time. If the sum ofthe recompilation time and the reconfiguration time for onefault injection is , the total time spent in recompilationand reconfiguration will be , where is the number offault injections. 2) Emulation time. Suppose the emulator cantypically operate at the speed of more than 1 MHz. Simulationof 100 K vectors takes only 0.1 s or less. Therefore, the actualemulation time is only a small fraction of the recompilationand reconfiguration time that dominates the total time of theentire process.

For large designs with large number of faults to be emulated,pure serial fault emulation may be too run-time expensivedue to the large number of recompilation and reconfigurations.Two techniques are proposed to enhance the performance. 1)Inject multiple independent faults simultaneously [9]. A setof faults is called independent if the fanout cones of thefaults in are mutually disjoint. Independent faults can beinjected simultaneously. By observing the output response tothe input stimuli, the detection of each single stuck-at fault ofan independent fault set can be determined without ambiguity.2) We add extra logic into the prototype design such that anumber of dependent faults can also be injected and emulatedwithin one FPGA-configuration. Using these techniques, thetotal number of recompilation and reconfigurations can bereduced dramatically.

B. Emulating Independent Faults Simultaneously

Definition 1: Output Image of a fault , denoted asImage , is the set of the primary outputs that are reachablestructurally from the faulty signal. In the case of a sequentialcircuit, it includes those primary outputs that are reachableby a path through FF’s.

Definition 2 [3]: A set of faults is called (structurally)independentas long as the output images of the faults inare mutually disjoint.

Consider the example in Fig. 4(a), Supposeis an indepen-dent fault set containing two faults and Then we canemulate and in a single run by injecting both faults intothe fault-free circuit simultaneously. From the output responsesof this circuit with double faults, the exact output responsesof the circuit with only and the circuit with only can bedetermined without ambiguity because Image and Image

are disjoint. If a fault effect appear at a primary output inImage , then is detected. Similarly, a fault effect appearat a primary output in Image , then is detected. In

1490 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 10, OCTOBER 1999

(a)

(b)

Fig. 5. Dynamic fault injection by adding extra circuitry. (a) A portion of an original circuit mapped into FPGA’s and (b) dynamic faults, signala

s.a.1 and signalg s.a.0, are injected byG1 and G2:

contrast, if the output images of and are not disjoint likethe case in Fig. 4(b), then these two faults cannot be emulatedsimultaneously due to the possible effect of fault masking, i.e.,it is possible that even though a fault (e.g.,) is detected bythe applied test sequence, the fault effect is masked in thepresence of another fault (e.g., .

In the preprocessing stage, the independent fault sets areidentified. All faults in each independent fault set are thenemulated at the same time during the subsequent emulationstage. In [9], an algorithm was proposed to damnify theindependent fault set for combinational circuits. We extendthis algorithm for sequential circuits. The average size of anindependent fault set for ISCAS89 benchmark circuits will bepresented in Section IV.

C. Dynamic Fault Injection

Exploiting the independency between faults can reduce thenumber of times that FPGA’s needs to be reconfigured. Butin general, the average size of an independent fault set forsequential circuits is quite small. Hence, we propose anothertechnique to further reduce the reconfiguration time. Thistechnique, calleddynamic fault injection,1 allows the injectionsof a large number of dependent faults in a single FPGA-configuration by adding extra supporting circuitry.

Fig. 5 illustrates the idea. Fig. 5(a) shows a portion of acircuit which has been mapped into the FPGA’s. The smallboxes represent the logic blocks (CLB’s). Supposestuck-at-one (s.a.1) and the stuck-at-zero (s.a.0) are not independent.Therefore, they cannot be injected and emulated in a singleconfiguration. However, by adding a fault activation controllerand two logic gates and as shown in Fig. 5(b), these

1This technique was also independently proposed in [2] and [20].

two faults can beinjected in a single FPGA-configuration.Note that the functionality of this FPGA-configuration isnow dependent on the output values of the fault activationcontroller. In Fig. 5(b), the fault activation controller has twooutputs, and One extra gate is also added at the location ofeach to be injected. For example, an OR gateis added forinjecting s.a.1 dynamically, i.e., whenis set to “1,” the faultis activated (because the output of an OR gate is a constant“1”). On the other hand, if is set to “0,” then no fault effect iscreated and CLB1 becomes fault-free. Similarly an AND gate,

, is added for injecting the s.a.0 fault dynamically. Whenis set to “1,” the fault is present. Whenis set to value ‘0,’

CLB2 is fault-free. The fault activation controller should bedesigned in such a way that only one dynamic fault is activatedat any time. For instance, initially the controller produces10 to emulate s.a.1. After all input vectors are emulated, weforce the controller to produce 01, which activates thesecond fault, s.a.0. Note that two passes of emulation in thiscase are still required. But since the emulation time is not thebottleneck, saving in the reconfiguration time will reflect inthe overall fault grading time. The performance estimation inSection IV will show the significant potential of this technique.

Since the injected faults are about to be activated one by oneduring the emulation stage, a circular shift register (CSR) canbe used to implement the fault activation controller. Each flip-flop (FF) of this CSR is responsible for activating one injecteddynamic fault. At the beginning of the emulation session,the content of this shift-register is initialized tofor emulating the fault dynamic fault. After the first faultis emulated, an external clock signal is applied to CSR tochange its content to , which will activate thesecond dynamic fault. Similar operations are performed for thefollowing activation of the rest of the injected dynamic faults.

CHENG et al.: FAULT EMULATION 1491

(a) (b)

Fig. 6. Mapping only four-input function to each CLB for dynamic fault injection. (a) A fault-free CLB regardless of the value ofx and (b) a CLBwith a dynamic fault (activated asx = 1).

Note that each FF can be used to activate a set of independentfaults in a more general case. With this dynamic fault injectiontechnique, we are able to inject a large number of faults perconfiguration at the cost of extra logic (the controller and onegate for each dynamic fault). In the extreme case, suppose theemulator has unlimited capacity for fault emulation, then noreconfiguration is needed because all faults can be injectedwithin one configuration.

Since recompiling the entire or partial circuit is time-consuming (involving repartitioning, replacement, and rerout-ing), we propose a technique to inject dynamic faults withoutchanging the layout of the FPGA’s. Our goal is to inject a set ofselected dynamic faults by only changing the affected CLBs’contents like the way we inject a static fault. Suppose a CLB iscapable of implementing any arbitrary five-input function. Weadopt a conservative policy that maps only four-input functionto each CLB. The intention is to reserve one input terminal ineach CLB for fault activation control signal. Fig. 6 illustratesthis idea. The function of a CLB is expressed in the Shannon-Expansion form. It contains two four-input functional blockssharing the same input signals These two functionalblocks are connected to a multiplexer controlled by a faultactivation signal In Fig. 6(a) the CLB’s output exhibits afault-free function regardless of the value ofbecause bothof its four-input functional blocks realize identical fault-freefunction. On the other hand, Fig. 6(b) shows a CLB with aninjected dynamic fault. When equals “0,” the output is fault-free. But when equals “1,” the injected dynamic fault isactivated and the faulty function is selected tothe CLB’s output. Recall that the function of isderived by evaluating the function of the CLB when the targetfault is present as shown earlier in Fig. 3.

The above scheme for dynamic fault injection can be donewithout changing the layout of the FPGA’s. In order toincorporate this scheme, the circuit compilation before the faultemulation process needs to be modified as follows.

1) Add a circular shift-register (CSR) to the design underfault simulation.

2) Map the design into CLB’s with the restriction that aCLB can only realize a function with at most four inputs.

3) Connect the output of each FF of the CSR to the

Fig. 7. The fixed layout of the fault activation signals generated by a CSR.(Only the interconnections needed for dynamic fault injections are shown.)

“reserved inputs” of a set of selected CLB’s as illustratedin Fig. 7.

4) Map the added interconnections into the routing chan-nels of the FPGA’s.

5) Download the configuration bitstream into the FPGAhardware.

After these modification, the fault injection can be doneby simply changing the contents of the affected CLB’s likeFig. 6(b). Recompilation is completely avoided because theinterconnections between CLB’s remains the same through-out the entire fault emulation process. This implementationtechnique trades emulation capacity for efficient dynamic faultinjection. Experimental results on ISCAS benchmark circuitsshow that the number of CLB’s increases by only 22% due tothis conservative policy. The entire procedure of fault gradingwith this idea is summarized in Fig. 8.

For a large design that requires more than one FPGAchips to implement, the shift register in each chip should beconnected in a global way that only one fault activation signalis activated in the entire system during any emulation session.

III. H ANDLING THE UNKNOWN LOGIC VALUE

A software fault-simulator typically uses the three-valuedlogic system, zero, one, and, where is an artificial logicvalue to represent the unknown. The emulation system, similar

1492 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 10, OCTOBER 1999

Fig. 8. Fault emulation procedure using proposed dynamic fault injection.

(a) (b)

Fig. 9. A primitive noninverting gate for handling three-valued logic usingdual-railed signals. (a) Original cell and (b) dual-railed cell.

to a real chip, do not have the notion of The lack ofvalue has both disadvantages and advantages. The presence ofthe hyperactive faults that cause thevalue to populate largeportion of the design creates a large number of unnecessaryevents in simulations using the value. Simulation for thesefaults is very computationally expensive and significantlydegrades the performance of the software fault-simulators.However, on the other hand, fault emulation system may not beable to differentiate the hard detected fault and the potentiallydetected fault because of the lack of thevalue. A fault iscalled hard detected if a fault effect (0/1 or 1/0) appears at aprimary output. While a fault is called potentially detectedwhen either (i.e., the fault-free value is one and thefaulty value is unknown ) or appears at a the primaryoutput after simulation. Fault emulation system will classifya potentially detected fault as either detected or not detecteddepending on the initial state of the emulation system. Forsynchronous circuits, the percentage of potentially detectedfaults is usually very low (Some results on ISCAS benchmarkcircuits will be presented in Section IV).

We can use a dual-railed logic to accommodate the unknownlogic value “ ” in our emulation system. The idea is touse two wires to represent a three-valued logic signal. Forinstance, 00 represents logic “0,” 11 represents logic “1,” and01 represents unknown “ ” while the unused code ten is adon’t care term that may be used to minimize the circuit. Thisencoding can be implemented by simple duplication of theoriginal netlist. For example, consider an AND gate shown inFig. 9(a). The new cell to implement the encoding scheme isgiven in Fig. 9(b). It doubles the fanins, the gate counts, andthe fanouts.

The correctness of the functionality can be verified by thetables in Fig. 10. Fig. 11 shows the transformation for aninverting NOR gate. The two wires of the output signal needto be swapped. These simple transformations are applicableto complex gates. We also need to duplicate all the FF’s

(a) (b)

Fig. 10. Verification of the AND cell of the dual-railed logic. (a) Originalcell operation and (b) dual-railed cell operation.

(a) (b)

Fig. 11. A primitive inverting gate for handling 3-valued logic usingdual-railed signals. (a) Original cell and (b) the cell implemented in hardwareemulator.

and implement them with set/reset features. At the beginningof an emulation run, the FF’s are reset to 01 to representunknown initial value “ ” One property that can be used toreduce the overhead is based on the observation that not everysignal has the possibility to have an unknown value. Thosesignals that are not reachable from the FF’s (only reachablefrom primary inputs), will never be contaminated by the “”value and, thus, do not have to use double rails. Instead, theyremain single railed. When these signals feed into the “”-contaminated region, they are duplicated and changed intodual-railed (i.e., “0” becomes 00 and “1” becomes 11). Theconcept is illustrated in Fig. 12. The overhead of using dual-railed logic in terms of the number of extra gates will bepresented in Section IV.

IV. EXPERIMENTAL RESULTS

Several experimental results on ISCAS-89 benchmark cir-cuits are presented in this section. Table I shows the averagesize of an independent fault set for some benchmark circuits.It indicates the average number of faults that can be injectedand emulated at the same time. This property allows about1.36 times speedup without any overhead when it is addedto the scenario of the serial fault emulation. Table II showsthe approximate area penalty of using proposed dynamic fault

CHENG et al.: FAULT EMULATION 1493

Fig. 12. Illustrating the dual-railed region.

TABLE ITHE AVERAGE SIZE OF INDEPENDENT FAULT SET

TABLE IITHE EXTRA NUMBER OF CLB’ S FOR DYNAMIC FAULT INJECTION

injection technique in terms of the number of extra CLB’s.The result is obtained by using the technology mapper in SIS[10]. The overhead of the fault activation controller, primarilyconsisting of FF’s, is relatively small and ignored. The averageoverhead for the proposed dynamic fault injection techniqueis about 22%.

Table III shows the percentage of the potentially detectedfaults that are obtained by running a software simulator,PROOFS [16], using two test sequences, one of which isgenerated by an automatic test pattern generation (ATPG)program and the other is random. The first number is thefault coverage counting only hard-detected faults. The secondnumber considers both hard-detected and potentially detected

TABLE IIITHE PERCENTAGE OF THEPOTENTIALLY DETECTED FAULTS

TABLE IVTHE AREA OVERHEAD OF USING DUAL-RAILED LOGIC

faults. If we do not use the dual-railed logic, the fault emulatorwould report a coverage within these two numbers. Sincethe difference between these two numbers is small, the faultcoverage reported by the fault emulator (without dual-railedlogic) would be very close to either one of the listed faultcoverages reported by the software simulator. Table IV showsthe estimated overhead of applying the dual-railed logic tohandle the “ ” logic value in terms of the number of extragates. The column under title “-region” represents the numberof gates that are reachable from present state lines and, thus,needed to be duplicated.

V. PERFORMANCE ESTIMATION

Suppose the circuit for fault emulation has gates andcollapsed faults. There areinput patterns. Some technical as-

1494 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 10, OCTOBER 1999

sumptions for estimating the fault emulation time are describedbelow. The reprogramming time of one FPGA-chip, denotedas , is assumed to be 0.5 s pessimistically. The bitstreammanipulation can be done off-line and thus its time is assumedto be negligible. The emulator is assumed to operate at thespeed of 1 MHz. The total fault grading time using the serialfault emulation algorithm can be expressed as

Time (serial fault emulation)

(reconfiguration time emulation time)

where is the implementation time of the original fault-free design. Consider a sample circuit with 100 K gates, 100 Kcollapsed faults, and a test sequence with 50 K input patterns.The second term becomes 100 K (0.5 0.05) 55 K s,about 14.5 h without fault dropping. Now if we incorporateboth techniques mentioned above, the fault emulation timecan be expressed as

Time (fault emulation)

where dynamic is the average number of dynamic faultsinjected in each configuration, Independent is the average sizeof an independent fault set, and is the time to reconfigureevery FPGA-chip. The second term of the above expressioncan be viewed as the total time for reconfiguration and the thirdterm the total emulation time. is related to the number ofchips required to implement the circuit under grade grading,expressed as

(reconfiguration time for a chip)*(number of chips)

(number of chips)(s).

Suppose there are 2020 CLB’s in each FPGA-chip. Theresults of Table II show that it takes about 4000 CLB’s toimplement a circuit with 20 K gates. By extrapolation, weassume that it takes 20,000 CLB’s (or 50 FPGA-chips) toimplement a 100 K gate circuit. Therefore,, being the timeto reconfigure 50 chips, will be s. Let us furtherassume that we inject 20 dynamic faults into each chip, (i.e.,one dynamic fault per column) and the size of the independentfault set, Independent, is 1.36 by the result of Table I. Then,the estimated fault emulation time of this 100 K gate circuitbecomes

s min min.

Based on this estimation, the reconfiguration time (i.e.,100 s) becomes negligible. The entire fault emulation time,reduced from 14.5-h to only 62.6 min as compared to theserial algorithm, is now dominated by the circuit emulation

time (i.e., 61 min). In general, the circuit emulation time isproportional to /Independent) as mentioned earlier.The reduction factor of the reconfiguration time, denoted asGain, can be re-expressed as follows:

This derivation indicates that the reduction factor onlydepends on the number of dynamic faults injected per chip.Increasing this factor will lead to a greater reduction. However,it may also cause a routing problem. Let us consider theextreme case for example. If we inject one dynamic fault intoeach CLB (i.e., 400 dynamic faults into each chip), then a faultactivation control signal described in Section II needs to beconnected to every CLB of the chip it controls. Therefore, thisnet will become a global one and very difficult to route. On theother hand, if we inject only one dynamic fault into a chip, thenthe proposed dynamic fault injection technique will behavevery much like a serial one. Since the reprogramming time ofthe FPGA-chips varies from vendors to vendors, in a specificemulation environment this factor needs to be carefully chosenin order to strike a balance between the routability and theoverall reconfiguration time reduction.

VI. CONCLUSION

Fault simulation for large sequential circuits remains avery time-consuming task. With the increasing performanceof field-programmable gate-array and logic emulation technol-ogy, a hardware fault emulation system has become not onlyfeasible but also very efficient as compared with the exist-ing software-based or hardware-accelerator-based approaches.This paper addresses the issues of realizing a fault emulatorbased on an existing logic emulation system. In addition toa primitive scenario of serial fault emulation, two techniquesare proposed to further speed up the process. The conceptof the independent fault set is exploited to allow parallelfault emulation, while the dynamic fault injection using extracircuitry attempts to break the performance bottleneck, i.e.,the reconfiguration time. The experimental results show thatthe overhead of our conservative policy of four-input CLBrealization for dynamic fault injection is modest. Meanwhile,the issue of incorporating the unknown logic value in theemulator is addressed. A dual-railed logic is used to augmentour emulator with the ability to simulate the unknown logicvalue and, thus, to differentiate the hard detected faults fromthose potentially detected faults. It is worth mentioning thatthe use of the dual-railed logic is not always necessary: 1) Forcircuits with a reset state, there will be no potentially detectedfaults assuming that the reset hardware is fault-free. 2) Forsynchronous circuits, the percentage of the potentially detectedfaults is usually very low. The performance estimation of theproposed emulation scheme shows that this novel approachcould improve the performance of fault grading significantly.

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Kwang-Ting (Tim) Cheng (S’88–M’88–SM’98), for a photograph and biog-raphy, see p. 1352 of the September 1999 issue of this TRANSACTIONS.

Shi-Yu Huang, for a photograph and biography, see p. 1352 of the September1999 issue of this TRANSACTIONS.

Wei-Jin Dai, photograph and biography not available at time of publication.