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276 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 2, JUNE 1998

Testing Configurable LUT-Based FPGAsWei Kang Huang, Fred J. Meyer, Member, IEEE, Xiao-Tao Chen, and Fabrizio Lombardi, Member, IEEE

Abstract We present a new technique for testing field

programmable gate arrays (FPGAs) based on look-up tables(LUTs). We consider a generalized structure for the basic FPGAlogic element (cell); it includes devices such as LUTs, sequentialelements (flip-flops), multiplexers and control circuitry. We usea hybrid fault model for these devices. The model is based on aphysical as well as a behavioral characterization. This permitsdetection of all single faults (either stuck-at or functional) andsome multiple faults using repeated FPGA reprogramming. Weshow that different arrangements of disjoint one-dimensional(1-D) cell arrays with cascaded horizontal connections andcommon vertical input lines provide a good logic testing regimen.The testing time is independent of the number of cells in thearray (C-testability). We define new conditions for C-testabilityof programmable/reconfigurable arrays. These conditions donot suffer from limited I/O pins. Cell configuration affects the

controllability/observability of the iterative array. We applythe approach to various Xilinx FPGA families and compareit to prior work.

Index Terms C-testability, field programmable gate array,programmability, reconfigurability, testing.

I. NOTATION AND DEFINITIONS

Horizontal The internal inputs (outputs) of an iterative array.

These propagate dependency between the CLBs

in the array.

Vertical The external inputs of an iterative array. These

can be directly specified in the test patterns and

require I/O blocks.Phase Each testing phase is a reprogramming of the

FPGA followed by test vector application. Since

reprogramming is slow, the number of phases is

a good measure of testing time.Session The application of every CLB test configuration to

those CLBs that are under test. Multiple sessions

are required if not all CLBs can be under test

simultaneously.

C-testable An FPGA is C-testable with a given testing

method if the number of programmings is

independent of the circuit size. In particular, for

an iterative array, it is independent of the length

of the array.The number of primary inputs to a CLB.

Manuscript received March 15, 1997; revised July 1, 1997. This work wassupported in part by the State of Texas Advanced Research Program.

W. K. Huang is with the Department of Electronic Engineering, FudanUniversity, Shanghai, China.

F. J. Meyer and F. Lombardi are with the Department of Computer Science,Texas A&M University, College Station TX 77843 USA.

X.-T. Chen is with FPGA Software Core Group, Lucent Technologies,Allentown, PA 18103 USA.

Publisher Item Identifier S 1063-8210(98)02949-7.

The number of primary outputs of a CLB.

The number of columns in the grid of CLBs.The number of rows in the grid of CLBs.

The number of CLBs

The number of I/O blocks.

For a given test method and FPGA family, the

number of configurations needed to test a single

CLB.

The part of due to the combinational par-

tition of the CLB.

The part of due to the sequential partition

of the CLB.

For a given method, the total phases needed for

the specified FPGA family FPGA.

For a given test method and FPGA family, the

number of test patterns needed to test a single

CLB.

The part of due to the combinational partition

of the CLB.

The part of due to the sequential partition.

For a given test method, for the specified

FPGA family FPGA (plus any extra clock cycles

needed to get the CLB response to chip I/O).

For a given FPGA, the number of sessions needed

by the BIST method [7].

For a given FPGA, the number of sessions needed

by the naive method [5].The regeneration period of a given iterative array.

(The number of CLBs traversed before the input,

output, and CLB configurations begin to repeat.)

The number of vertical (external) inputs to each

CLB in a given iterative array.

The number of iterative array vertical inputs that

differ for each CLB in one period. In the degen-

erate case of period 1,

II. INTRODUCTION

F

IELD programmable gate arrays (FPGAs) are widely

used for rapid prototyping and manufacturing of com-plex digital systems, such as microprocessors and high-speed

telecommunication chips [1]. FPGAs are commercially avail-

able from many vendors. Our prototypical FPGA is a two-

dimensional (2-D) grid of configurable logic blocks (CLBs).

The CLBs can be programmed to implement combinational

as well as sequential logic functions [1] and each CLB

is identical before programming. CLBs are separated by

a programmable interconnection network; the interconnect

consists of either programmable connector and/or switching

blocks [2], or a series of horizontal/vertical routing tracks

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HUANG et al.: TESTING CONFIGURABLE LUT-BASED FPGAS 277

and segments with programmable devices. Customization is

accomplished by configuring the interconnect and the CLBs

by loading them with appropriate data from an external storage

device. The FPGA also includes input/output blocks (IOBs),

which provide the interface between the package pins and the

internal logic.

The numbers of CLBs and IOBs vary widely depending on

the particular chip and manufacturer [2]. FPGAs are versatile

and in widespread use, due to their programmable nature and

their ease of reconfiguration [3]. Internal static configuration

(memory) elements determine the logic functions and the

interconnections. The SRAM in memory-based FPGAs can

be used to configure functions via look-up tables (LUTs).

Also, they often have a mode where the configuration SRAM

is usable as memory.

We focus on CLB testing for SRAM-based FPGAs that

implement functions via LUTs.

III. BACKGROUND

Testing FPGAs is addressed in the literature such as [4][7].These works and this paper deal with manufacturing test. Other

tests in the field, such as verifying correctly loaded configu-

ration data, are typically handled by architectural features for

reprogrammable FPGAs [2]. Reference [4] discusses testing

of row-based (segmented channel) FPGAs. The approach

sequentially tests every cell using a modified scan procedure,

providing 100% fault coverage of single stuck-at faults. It

requires many tests and does not fully exploit the regularity of

the FPGA to reduce test time. The methodology in [8] for

testing uncommitted segmented channel FPGAs for single

stuck-at faults is based on connecting the cells of each row

as a one-dimensional (1-D) unilateral array, such that the

FPGA could be tested as a set of disjoint arrays. This yieldsconsiderable reduction in both vectors and test circuitry.

Simultaneous testing of disjoint arrays helps achieve constant

test set size (C-testability), so that test cost will be independent

of chip size [9].

In [7], the FPGA is configured to conduct direct output

comparisons of pairs of logic cells using full cell control-

lability. Test generation and output response comparison are

handled internally using some of the logic resources in a built-

in self-test (BIST) arrangement. This requires at least one extra

session, i.e., a doubling of chip programmings so that the

cells previously used for test pattern generation and for output

comparisons can become cells under test. Fault simulation

established that 100% fault coverage can be accomplishedfor single stuck-at faults. In [10], the logic resources are

arranged as an iterative logic array (ILA) [9]. This allows

better scalability than the previous BIST arrangement [7];

however, it also requires another additional sessioni.e., a

tripling of chip programmings.

A simple testing arrangement (referred to as naive) was

mentioned in [5]. It connects together all input lines to

the CLBs (cells) under test from the IOBs, and uses the

remaining IOBs for direct observability of the output lines

of each cell under test. Fig. 1 shows a single programming

phase with the three leftmost CLBs under test. Each CLB

Fig. 1. One programming phase with the naive testing method.

Fig. 2. Interior of a Xilinx XC5200 CLB.

in the figure has three inputs and two outputs. Three IOBs

are consumed in order to provide the cells under test with

their input vectors. The cells under test have no connections

between them. Their output response is directly observed at the

IOBs. In each programming phase, only a few CLBs can betested in parallel. This is basically restricted by the number of

IOBs and the number of output lines of each CLB. In Fig. 1,

only three CLBs can be under test, because, after three IOBs

are used for CLB inputs, only seven IOBs remain to observe

output response.

IV. PROPOSED FAULT MODEL

Fig. 2 shows a portion of a Xilinx XC5200 CLB. A full CLB

consists of four stacked copies of the figure (with the carry in

(CI) and carry out (CO) signals rippled through)plus a little

extra logic. The portion in Fig. 2 has a single LUT with four

inputs, so it has 24 configuration bits to specify its function.Of the three multiplexers, M1 is a conventional multiplexer.

M2 and M3 are programmable multiplexers; each needs only a

single configuration bit to specify which input it passes. There

is also a D flip-flop.

Our generalized internal CLB structure permits these de-

vices: LUTs, programmable (configurable) multiplexers, con-

ventional multiplexers, and flip-flops. Some conventional logic

usually does not interfere with test generation.

We assume the interconnect and the IOBs have already

been tested; the interested reader should refer to [11] and [12]

for a detailed treatment. In our proposed testing strategy, we

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divide CLBs into independent sets (linear arrays). For our

fault model, within each linear array, we assume at most one

faulty CLB; otherwise, fault masking might occur. For the

single faulty CLB, the nature of the fault could take any form.

For simplicity of illustration, in our investigation, we limited

a CLB to a single faulty device. The nature of a device fault

varies with the device.

We model single device faults both physically (e.g., stuck-

at) and functionally [13]. This hybrid fault model is adaptable

to emerging FPGA technology and to different products as

they become commercially available [2]. The fault model was

shown suitable to FPGAs in [5] and confirmed by industrial

experiments. In particular, by device as follows.

For a LUT, a fault can occur in any one of the: memory

matrix, decoders, and input and output lines. A faulty

memory matrix makes some memory cells incapable of

storing the correct logic value (the LUT has a single bit

output, so this value is either 0 or 1) [2]. Any number of

memory cells in the LUT could be faulty. If the fault is

in the decoder, the erroneous address leads to reading the

contents of the wrong cell, i.e., a one-bit address fault. Thethird possible LUT fault is on the I/O lines, with respect

to which we allow any single stuck-at fault. The one-bit

decoder address fault can be collapsed to the stuck-at fault

of a LUT input line. So this fault type is detected when

the decoders are tested. A stuck-at fault on a LUT output

line is covered by the tests for the LUT memory matrix.

For a multiplexer, we use a functional fault model,

because the internal logic structure varies from FPGA

to FPGA [2]. Testing confirms the multiplexers ability

to select each input.

For the D flip-flops, we use a functional fault model. A

fault can cause a flip-flop to receive no data, to be unable

to be triggered by the correct clock edge, or to be unableto be set or reset.

Our testing objectives are as follows:

a 100% fault coverage under a single faulty device model

with neither delay nor area overhead;

ease of test pattern generation, because patterns are

generated for a CLB, not the whole FPGA;

efficient implementation of the testing process as mea-

sured by the amount of memory required to store the test

instructions (configuration bits and test patterns);

the number of programming phases must be as small as

possible, because reprogramming time is much greater

than test pattern application time [3].

V. TESTING A CLB

We generate test patterns in two steps according to the CLB

partitioning.

Consider initially a CLB made of a single LUT. We can

test the LUT memory matrix by reading all the memory bits

in two phases. The programmed memory matrix contents in

the second phase are complements of the first.

The scenario is different for testing stuck-at faults at the

LUT inputs. The LUT matrix contents must be arranged such

that the boolean difference is one for the input to be tested;

multiple patterns are required. Furthermore, each LUT output

must be observable at a primary CLB output. So we require

a sensitized path from the LUT output to a primary CLB

output. By definition of the combinational partition, this can

be achieved by configuring the multiplexers (or other devices)

in the partition.

We use a functional test for the multiplexers. Since a

multiplexer selects from among all inputs, each data input

must be active in at least one phase. Further, the functional test

consists of applying logic 1 to the selected input while holding

all others at logic 0, and a second test pattern with these logic

values reversed. The multiplexer output must be observable

from at least one primary CLB output. If a multiplexer is

not simultaneously controllable/observable, additional phases

could be required. We need at least phases to test a

multiplexer with inputs. A multiplexer can be tested with a

LUT (if connected); a possible way to accomplish this consists

of choosing a memory matrix for the LUT that satisfies the

multiplexer(s) testability conditions. In this way, test phases

can be overlapped (reduced).

A. Testing the Sequential Partition

The sequential partition includes the D flip-flops as well

as multiplexers and control circuits emanating from them or

only observable through them. During test generation, we seek

to overlap testing of programmable multiplexers with that of

flip-flops.

In some FPGAs, flip-flops are more complicated than the

D type. In particular, the Xilinx XC4000 family [2] has D flip-

flops plus added logic that can be programmed to add set/reset

capability. The S/R controllers are configurable to allow a set

function, a reset function, or neither. For the XC4000, this

requires three separate programming phases; however, testingof the S/R controllers can be overlapped with testing the

flip-flops.

1) Testing the D Flip-Flops: We functionally test the D

flip-flops. We test the input and hold function with the data

sequence 010 (or 101) at D. Separate phases are required

to test both rising and falling edge trigger mechanisms, if

applicable. We can test the set (reset) function by applying

the set (reset) signal after a flip-flop is in the 0 (1) state.

The set/reset disable functions must also be tested if present,

leading to another phase. To test the clock enable function, we

use the five-vector sequence given in Fig. 3. Some functional

tests can be overlapped to reduce the number of phases. We

can possibly also overlap phases with those for multiplexers,depending on the sequential partitions structure.

VI. PROPOSED TEST STRATEGY

Fig. 4 shows a linear iterative array. There is a cascaded

(horizontal) input reflecting the dependence of the cells in the

iterative array, and test vector is obtained from the IOBs

and applied to this input. Other (vertical) inputs to the cells

are not shown, but are also obtained directly from the IOBs.

The CLBs in the array are programmed to implement

functions: , etc. The period of the array, is the

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Fig. 3. Testing the enable function.

Fig. 4. Iterative array with period three.

number of cells we must traverse in order to repeat the

cascaded input. We do not allow all test patterns; the test

generation process must ensure the periodicity is satisfied

as it searches the input space. In Fig. 4 it must ensure that

. The programmed functions could

all be different, but we will constrain them to be identicalso,

if we have then various cells see inputs and

Speaking in terms of single-pattern (combinational)

testing, we only need to concatenate and to the

input vector (and schedule the corresponding vertical CLBinputs) and we will have every CLB experience test vector

The test set can then be compacted by eliminating unnecessary

patterns.

For successful testing, faulty outputs must also propagate

through the array. Again, the test pattern generation procedure

must ensure that excited faults propagate [9].

Our proposed approach depends not only on the number

of CLB inputs and outputs (compared with the number of

IOBs), but also on the nature of the array under test (either

combinational or sequential). The novelty of the approach

comes from using different types of array configurations to test

the CLBs. Initially, each CLB is divided into two partitions:

a combinational partition (which includes those cell outputs(and their fan-in nodes) that are combinational functions of

the cell inputs) and a sequential partition (which includes the

remaining devices). We use the following strategy.

For testing the combinational partition of each CLB along

an FPGA row, we program a 1-D (combinational) array.

Each LUT is loaded with values such that the iterative

arrays form a C-testable system (constant test set size).

Let there be independent iterative arrays with

horizontal inputs, horizontal outputs, and vertical

inputs. Then, we need IOBs for

controllability/observability when

For testing the CLB sequential partition, we program a

1-D (sequential) array and use the pipeline technique of

[8]. To reduce the number of required IOBs, as many

as possible vertical inputs are made common (i.e., they

will have identical logic values when test vectors areapplied). This is beneficial because, in a sequential array,

the requirements of controllability and observability are

far more stringent than for a combinational array of the

same size [8], [9]. Let the number of vertical inputs

with different logic values in the test process for the

pipeline technique be . So, IOBs IOBs)

are required for the primary horizontal inputs (outputs).

IOBs are used as primary vertical inputs for the

vertical inputs of the CLBs with different logic values

during the test process and IOBs are used as

primary common vertical inputs for those vertical inputs

that do not need to be distinguished. The total required

IOBs is then when

.

The issue of different possible arrangements for the CLB

inputs in each 1-D array must be considered with respect tothe number of IOBs and the number of programming phases.

In [14], we give different testing arrangements that depend

on the values of and and on whether the array is

combinational or sequential.

The implication of FPGA programmability is that the test

patterns for a CLB can be applied in different phases. Also,

in each phase different CLB input(s)/output(s) can be selected

as horizontal. So the C-testable process is not static as in

[8], [9]; for example, the regeneration period can be different

in different phases. The definition of C-testability remains

unalteredi.e., the number of phases is independent of the

array size.

VII. EVALUATION OF XILINX FPGAs

We applied our array-based testing method to three FPGA

families from Xilinx [2]the XC3000, XC4000, and XC5200.

We use the XC5200 for examples. Further details are in [14].

We measure testing complexity with the following:

the number of programming phases for testing a CLB is

where denotes the

number of programming phases for testing the combina-

tional (sequential) partition;

the number of patterns for testing the whole FPGA is

where denotes the number

of patterns for the combinational (sequential) partitions.For the XC4000, we omitted testing some logic in this

study; specifically, logic to bypass the sequential outputs,

RAM functionality of the LUT configuration memory, and

some embedded logic to aid carry arithmetic.

To test the combinational (sequential) logic module of a

CLB, and and

Hence, a CLB in an XC4000 FPGA requires a total of

tests and phases.

In each phase for testing the CLB sequential partition, we

need additional clock cycles to deliver the response to

the IOBs [8]. and hence, the total

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TABLE IVCLB ARCHITECTURAL COMPARISON

Naive Approach. Every CLB is tested independently,

hence BIST Approach. In each session, the CLBs are config-

ured into disjoint groups: the test pattern generators, pairs

of CLBs under test, and response comparators for each

test pair. We conclude that (For the

upper bound, we assumed that was barely

achievable.)

Array-Based Approach. We assume test invalidation oc-

curs in a 1-D array if there is more than one faulty

CLB. Since we configure the arrays along the rows of

the FPGA,

IX. ARCHITECTURES AND COMPARATIVE ANALYSIS

We compare the Xilinx FPGAs in the series 3000, 4000,

and 5200 with respect to their CLB structures and IOB

limitations. We compare each CLB architecture by consider-

ing programmability and controllability/observability and the

required programming phases. Further details are in [14].

A. Comparison of CLB Devices and Features

Table IV gives the numbers of D flip-flops, LUTs, and

programmable and conventional multiplexerstogether with

the test patterns and programming phases needed by the array-

based method. It also gives the configuration memory size

due to the flip-flops and programmable multiplexers. Thedifference between the XC3000 and XC4000 families is not

large. The XC4000 has an extra 8-bit LUT connected in series

with the other two LUTs. This partially affects controllability

and observability; however, some of the required tests for

the additional LUT can still be combined with the tests for

the other two LUTs. We consider the R/S control elementsequivalent to two MUXs each, so the XC4000 CLB has more

programmable MUXs. Also, six MUXs have four inputs.

Since the number of programming phases to test a MUX

depends linearly on the number of MUX input lines [5], these

need more phases (and test vectors) for the XC4000 compared

to the XC3000.

Two main XC5200 features contribute to its suitability tothe array-based testing approach. First, it can be treated as

four parallel simple logic cells (LCs) with little hassle. Like

the XC4000 LUTs, internal signals are not independent (due

to MUX and the extra logic). But these devices have

adequate controllability, so testing the dependent logic only

requires extra test patterns, not phases.

The second fortunate XC5200 feature is its simple sequen-

tial structure. This leads to two sequential phases, cf. 12

(13) for the XC3000 (XC4000). The XC4000 has several

programmable MUXs that are in the sequential partition, in

addition to the programmable R/S logic. The XC3000 has

TABLE V

QUALITATIVE COMPARISON OF XILINX FPGA FAMILIES

similar woes. Also, XC3000 sequential outputs feed back to

its LUTs. That feedback must be tested sequentially, because

the XC3000 flip-flops are always enabled.

X. CONCLUSIONS

We presented a new approach for testing LUT-based

FPGAs by utilizing their reprogrammability. Under a hybrid

(functional and/or stuck-at) single device fault model, we

can test an FPGA by configuring the CLBs as 1-D arrays:

the approachs novelty compared to previous work is that

we use different array structures for different testing needs.

This array-based technique takes into account the limited

controllability/observability due to limited chip I/O. In testing

with our approach we do not consider the actual application

configurations; the whole FPGA is fully tested, confirming its

programmability for all applications, and results in significantadvantages, such as a unique testing regimen independent

of how many applications there are and their specifics. It is

suitable for manufacturing test and to serve as a universal

power-on self-test. Our approach has no area/delay penalty cf.

design for testability approaches.

We analyzed the array-based technique with respect to the

numbers of chip reprogrammings and test patterns needed. We

demonstrated its applicability to three Xilinx FPGA families.

We draw the following general conclusions.

For our method, the number of chip programmings

to fully test all logic blocks (CLBs) is the same as

that to test a single CLB with perfect controllabil-

ity/observability. With CLBs, given that thereare I/O blocks, the number of clock cycles

to apply the test vectors is Since chip

programming time is typically at least equivalent to

10 000 cycles, our methods testing time is essentially

independent of FPGA size.

With our approach, all CLBs can be under test simulta-

neously. This is possible with neither the naive approach

[5] nor the BIST approach [7]. Table V compares Xilinx

families and test methods. We use and to denote

superiority and inferiority, respectively, while is

neutral. So means fewer tests, fewer phases, more

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HUANG et al.: TESTING CONFIGURABLE LUT-BASED FPGAS 283

IOBs cf. CLB outputs, and better CLB observability

compared to other families. For a test method, means

faster testing (fewer phases) for that family than with

other methods.

Our method uses only three different array layouts.

I/O limitations were never a problem, despite studying

FPGAs of various sizes and with various architectural

features.

We confirmed that the CLB architecture has a major

impact on array test complexity. In particular, LUTs

connected in series or programmable multiplexers with

many inputs are two characteristics that lead to more

chip programmings. As seen with the Xilinx XC5200,

a large CLB can still be very efficiently tested due

to the regularity of its internal organization and the

simplicity of its sequential partition. For the naive and

BIST approaches, a small number of I/O blocks adversely

impacts testing time. Our approach is largely independent

of I/O blocks, but can benefit only slightly from having

many CLB outputs.

ACKNOWLEDGMENT

The authors would like to thank the reviewers for providing

very detailed comments.

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Wei Kang Huang was born in Shanghai, China, in 1941 and graduated from

the Department of Physics, Fudan University, Shanghai, China, in 1965.From 1985 to 1987, he was a Visiting Scholar at the University of Arizona,

Tucson, and at the University of Colorado, Boulder. During the period from1994 to 1996, he was a Postdoctoral Research Associate at the Department ofComputer Science, Texas A&M University, College Station, where he pursuedresearch in testing and fault tolerance of FPGAs. Currently, he is a Professorin the Department of Electronic Engineering, Fudan University. He is a GroupLeader in the computer-aided design/computer-aided testing (CAD/CAT) area.His research interests include test generation and simulation, VLSI design,design for testability, and fault tolerance.

Fred J. Meyer (M95) received the B.Sc. (Hons.) degree in computer systemsengineering and the Ph.D. degree from the University of Massachusetts,Amherst, in 1984 and 1991, respectively.

He is a Research Associate in the Department of Computer Science atTexas A&M University, College Station. He was previously with the UnitedStates Air Force. His research interests are in distributed computer systemsand algorithms, reliable and secure communication protocols, reliable systemdesign and validation, and IC yield enhancement and assessment.

Xiao-Tao Chen was born in Shanghai, China, on April 28, 1964. He receivedthe B.S. and M.S. degrees in electronics engineering from Fudan University,Shanghai, China, and the Ph.D. degree in computer science from Texas A&MUniversity, College Station, in 1985, 1991, and 1997, respectively.

From 1985 to 1988, he was involved in data communication, and from1991 to 1994, he was a faculty member at Fudan University. Since 1989,he has been working on computer-aided testing (ATPG and DFT), designverification, computer architecture, and algorithms. He is currently with

Lucent Technologies, Allentown, PA, working on ORCA FPGA design anddevelopment.

Fabrizio Lombardi (M82) received the B.Sc. (Hons.) degree in electricalengineering from the University of Essex, U.K., in 1977. He received theMasters degree in microwave and modern optics, the Diploma in microwaveengineering, and the Ph.D. degree from the University College London, U.K.,in 1978, 1978, and 1982, respectively.

In 1977, he joined the Microwave Research Unit at the University CollegeLondon. Previously, he was with the University of Colorado, Boulder, andTexas Tech University, Lubbock. He is currently a Full Professor in theDepartment of Computer Science at Texas A&M University, College Station,where his research interests are in fault-tolerant computing, testing and designof digital systems, and parallel and distributed computer systems. Current

topics under investigation include design and test of programmable digitalsystems (such as FPGA and FPIC), defect tolerance for IC manufacturing,mapping for parallel processing applications, testing of arrays, and protocoldesign and verification.