001-91135Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev...

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001-91135 Owner: PAJE High-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *A New Product Introduction: High-Performance 4-PLL Clock Generator Cypress Delivers Industry-Leading Flexible Timing Solutions for Next-Generation Consumer Devices

description

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *A Cypress, the leader in programmable clocks for nearly two decades, designed the world’s first: Programmable clock generator Programmable skew buffer Programmable die for crystal oscillators Cypress has a broad clock portfolio 1,700 clock marketing part numbers Clock generators that generate frequencies up to 700 MHz with

Transcript of 001-91135Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev...

Page 1: 001-91135Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *A New Product Introduction: High-Performance 4-PLL.

001-91135 Owner: PAJE High-Performance 4-PLL Clock Generator New Product Introduction (Customer)Rev *A

New Product Introduction:High-Performance4-PLL Clock Generator

Cypress Delivers Industry-Leading Flexible TimingSolutions for Next-Generation Consumer Devices

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001-91135 Owner: PAJE High-Performance 4-PLL Clock Generator New Product Introduction (Customer)Rev *A

Consumer devices are becoming feature-rich and connectedThey integrate storage, media processing and connectivity to enhance the user experienceSo users can create, store and share digital media content anywhere and anytime

Sharing high-resolution media content requires faster data transfer standardsThe data storage transfer protocol has moved from SATA 1.0 to SATA 3.0Ethernet systems have migrated from 10 Gbps to 100 GbpsUSB 3.0 is replacing USB 2.0 for user connectivityData interconnect standards are moving from PCIe 1.0 to PCIe 3.0

Consumer devices must support multiple data standards, each with specific timing requirements

Consumer devices require highly integrated and flexible timing solutions

Consumer Devices Are Driving Faster Data Transfer Standards

CY274101 Reference Clocks for Data Transfer Standards

1 CY27410 programmable clock generator can generate up to 12 output frequencies 2 Cycle-to-Cycle Jitter3 High-speed current steering logic

PCIe 3.0 Hub

Ethernet MAC

SATA 3.0 Host

USB 3.0 Hub

100-MHz LVDS, 3-ps RMS Jitter

48-MHz LVCMOS, 100-ps CCJ2

25-MHz LVCMOS, 100-ps CCJ2

100-MHz HCSL3, 1-ps RMS Jitter

24 MHz CY27410

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001-91135 Owner: PAJE High-Performance 4-PLL Clock Generator New Product Introduction (Customer)Rev *A

Cypress, the leader in programmable clocks for nearly two decades, designed the world’s first:Programmable clock generatorProgrammable skew bufferProgrammable die for crystal oscillators

Cypress has a broad clock portfolio1,700 clock marketing part numbersClock generators that generate frequencies up to 700 MHz with <0.6-ps RMS Phase JitterClock buffers that support frequencies up to 1,500 MHz with <0.05-ps RMS Phase JitterIndustrial- and automotive-grade products

Cypress is a proven and reliable clock supplier that has sold over 2.5 billion unitsOffers predictable lead times of ≤6 weeks with greater than 99.4% on-time deliveryEnsures a stable supply for its customers with multiple assembly and test sites Supports legacy parts >20 years old

Pioneer in Programmable Clock Solutions

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Terms You Will Hear TodayCycle-to-Cycle Jitter (ps)The maximum difference in a clock period between two adjacent clock cycles, measured over 1,000 clock cycles

Phase Noise (dBc/Hz)Noise power relative to clock signal power, measured in a 1Hz window centered at a given offset frequency from the clock signal

RMS Phase Jitter (ps) The integration of Phase Noise over a specified bandwidth, most commonly 12 kHz to 20 MHz (see below)

RMS Phase Jitter = , where fc is the clock frequency

Voltage Controlled Frequency Synthesis (VCFS)A method by which the frequency of a clock signal is varied based on a control voltage input

Phase Noise Plot

Frequency (kHz)

Offset

1-Hz BW

Pow

er (d

Bc) Phase Noise

(dBc/Hz)

RMS Phase Jitter Plot

Frequency (kHz)

Pha

se N

oise

(dB

c/H

z)

f1

Phase Noise PN (f)

fc

fc

4a

f2

ට 10PN(f)/10 f2f1 𝑑𝑓2πfc

RMS Phase Jitter

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001-91135 Owner: PAJE High-Performance 4-PLL Clock Generator New Product Introduction (Customer)Rev *A

Terms You Will Hear TodayElectromagnetic Interference (EMI)A disturbance that affects an electrical circuit, often caused by electromagnetic radiation emitted by an external sourceClocks create electromagnetic radiation, because of their high frequency and periodic nature

Spread Spectrum (SS) ModulationA method used to vary the frequency of a clock signal to spread its energy across a wider frequency range, thus reducing EMI

Frequency Select A feature in a clock generator used to select a preprogrammed output frequency using external digital control pins Used also to selectively turn off the reference frequencies to certain peripherals to reduce power consumption

Glitch An undesired transition that occurs before the clock signal settles into its intended value

Glitches

Glitch

Time (ps)

Vol

ts (V

)

SS Modulation in the Frequency Domain

Pow

er (d

Bc)

Frequency (kHz)

SS EMI Reduction:Typically 10 dB

Using a crystal-based solutionUsing a crystal + CY EMI-reduction clock

FCC EMI Limit

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001-91135 Owner: PAJE High-Performance 4-PLL Clock Generator New Product Introduction (Customer)Rev *A

Design Problems Engineers FaceMultiple clocks in consumer devices increase the BOM cost and PCB areaUp to 12 reference clocks, including RTC1, may be required for the processors and peripherals (PCIe, USB, SATA, GbE)

High-frequency clocks produce enough EMI to violate regulatory emission standardsTraditional EMI-reduction solutions, such as ferrite beads and chokes, are expensive and add board spaceEMI problems threaten time-to-market because EMI testing is typically performed at the end of the development cycle

Consumer products require additional components to manage reference clocks Audio systems require Glitch-free clock switching to suppress burst noise2

Multifunction printers need to selectively turn off clocks to certain peripherals to reduce power consumptionConsumer devices with multiple systems-on-chip require their respective reference clocks to be in phase with each other

Cypress’s CY27410 4-PLL clock generator solves these problemsSaves board space by generating up to 12 programmable output frequencies on a single chip Reduces EMI using SS ModulationSimplifies system design with Glitch-free switching, Frequency Select and early/late clocks for phase control

Cypress’s high-performance clock generator is a single-chip solution that simplifies system design

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1 Real-time clock (32.768 kHz)2 Audible noise caused by high-frequency Glitches that occur during frequency switching

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Feature CY27410 5V49EE902 Si5338

VCFS Yes Yes No

Cascading PLL Yes No No

Zero Delay Buffer Mode Yes No Yes

Non-Zero Delay Buffer Mode Yes No No

Early/Late Clocks Yes No Yes

Glitch-Free Outputs Yes Yes No

Frequency Select Yes Yes No

On-Board Programming Yes No Yes

Real-Time Clocks Yes No No

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CY27410 vs. Competition

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Max. Output Freq. (single-ended) 250 MHz 200 MHz 200 MHz

Max. Output Freq. (differential) 700 MHz 500 MHz 700 MHz

Cycle-to-Cycle Jitter 30 ps 200 ps 30 ps

RMS Phase Jitter 0.7 ps 3 ps 0.7 ps

Number of Outputs 12 Single-Ended, 8 Differential 9 Single-Ended, 2 Differential 8 Single-Ended, 4 Differential

Current per PLL 20 mA 22.5 mA 45 mA

Standards PCIe 3.0, SATA 2.0, 10 GbE, USB 3.0

PCIe 1.0, SATA 2.0, 10 GbE, USB 3.0

PCIe 3.0, SATA 2.0, 10 GbE,USB 3.0

VDD 1.8, 2.5, 3.3 V 3.3 V 1.8, 2.5, 3.3 V

Programmability I2C No I2C

SS (Center) ±0.225% to ±2.50% ±0.5% ±0.2% to ±5%

SS (Down) -0.25% to -5.0% -0.5% -0.5%

Automotive Grade Yes No No

Feature CY27410 5V49EE902 Si5338

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CY27410 vs. Competition

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001-91135 Owner: PAJE High-Performance 4-PLL Clock Generator New Product Introduction (Customer)Rev *A

The CY27410 Is a Better Solution

And other components such as RTC and buffers

Simplify a conventional design using multiple timing components…

By selecting Cypress’s multi-output programmable clock…

To produce an integrated, low-cost timing solution for multiple applications.

With ferrite beads and chokes to reduce EMI

Separate chip for each data transfer standard

PCIe Clock 10GbE Clock

Multifunction Printer

Car Infotainment System

Femtocell

10GbE

Real-Time Clock ( RTC) Clock Buffer

4-PLL Clock Generator

Reference clocks for PCIe, SATA, GbE and USBSpread Spectrum Modulation to reduce EMILow-frequency support for RTCConfigurable as zero or non-zero delay buffer

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Clock Generators Clock Buffers

EMI Reduction Non-EMI Reduction Zero Delay Buffer (ZDB) Non-Zero Delay Buffer (NZDB)

Timing Solutions Portfolio (NDA)Programmable | High Performance | EMI Reduction | Automotive A1

CY2429x Max Freq: 200 MHz2-4 outputs, PCIe 1.1

75-ps CCJ4, Ind3, Auto A1

CY22050/150/801 Max Freq: 200 MHz3-6 outputs, 1 PLL250-ps CCJ4, Ind3

CY22800 Max Freq: 166 MHz

3 outputs, 1 PLL250-ps CCJ4, Ind3

CY2239x/CY229x/CY2238x Max Freq: 200 MHz

3-6 outputs, 3-4 PLL, I2C, Freq Select400-ps CCJ4, Ind3, Auto A1

CY2Xx (FleXO™) Max Freq: 690 MHz

1 output, Freq Margining< 0.6-ps RMS Jitter2, Ind3

CY254x/CY251xMax Freq: 166 MHz

3-9 outputs, 1-4 PLL, I2C, Freq Select100-ps CCJ4, Ind3

CY7B99x (RoboClock™) Max Freq: 200 MHz

8-18 outputs, Configurable Skew50-ps CCJ4, Ind3

CY23S02/05/08/09 Max Freq: 200 MHz

2-9 outputs, Spread Aware200-ps CCJ4, Ind3

CY23FS04/08 Max Freq: 200 MHz

4-8 outputs, Fail Safe5

200-ps CCJ4, Ind3

CY230x/EP0x Max Freq: 220 MHz

5-9 outputs, LVCMOS22-ps CCJ4, Ind3

CY2DLx/DMx/DPx/CPx Max Freq: 1.5 GHz

2-10 outputs, LVDS, LVPECL, CML< 0.05-ps RMS Jitter2, Ind3

CY230xNZ Max Freq: 133 MHz

4-18 outputs, LVCMOS250-ps CCJ4, Ind3

CY2994xMax Freq: 200 MHz

9-18 outputs, LVCMOS200-ps CCJ4, Ind3

Stan

dard

Pe

rfor

man

ceH

igh

Per

form

ance

App

licat

ion

Spec

ific

CY274xMax Freq: 700 MHz

12 outputs, PCIe 3.0, 4 PLL <0.7-ps RMS Jitter2, Ind3, Auto A1

CY294x/CY5107Max Freq: 1.4 GHz

1 output, 40/100 GbE, 1 PLL<0.15-ps RMS Jitter2, Ind3

CY276xMax Freq: 700 MHz

8 outputs, PCIe 3.0, 2 PLL <0.7-ps RMS Jitter2, Ind3, Auto A1

CY278xMax Freq: 200 MHz

4 outputs, PCIe 3.0, 1 PLL <0.7-ps RMS Jitter2, Ind3, Auto A1

Production Development/ConceptNew

4 Cycle-to-Cycle Jitter5 Automatic clock switching on failure of a clock source

1 AEC-Q100 -40ºC to +85ºC2 Integrated Phase Noise, 12-kHz to 20-MHz offset3 Industrial grade -40ºC to +85ºC

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Product Overview

Multifunction printersDigital TVsBlu-ray recordersHome gatewaysFemtocellsRouters and switches

Applications

High frequency: 700-MHz differential, 250-MHz single-endedPin select and I2C programming Twelve outputs: Eight configurable as differential or single-ended Four single-endedReference clock support for PCIe 3.0, SATA 2.0 and 10 GbERMS Phase Jitter <0.7 ps (typical)Additional features: Configurable as zero or non-zero delay buffer Glitch-free frequency switching Frequency Select Early/ late clocks PLL cascading Voltage Controlled Frequency Synthesis

Features

Preliminary Datasheet: Contact Sales

CollateralSampling: Q3 2014Production: Q4 2014

Availability

1 Crystal input2 Crystal output3 Reference clock inputs

4 Serial port5 Voltage input pin for VCFS6 Frequency Select inputs

Memory and

Control Logic

Out1Out2Out3POut3NOut4POut4NOut5POut5NOut6POut6N

XIN1

XOUT2

IN1P3

IN1N3

IN2P3

IN2N3

Four-PLL Spread-Spectrum Clock Generator

PLL

Input Block

Out7POut7NOut8POut8NOut9POut9NOut10POut10NOut11Out12

Divider

Divider

Divider

DividerPLL 1 Block

PLL 3 Block

PLL 2 Block

PLL 4 Block

Output Bank 2

Output Bank 1

Block Diagram

SCLK4

SDAT4

VIN5

FS26

FS16

FS06

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001-91135 Owner: PAJE High-Performance 4-PLL Clock Generator New Product Introduction (Customer)Rev *A

1. Visit the Cypress Timing Solutions website: www.cypress.com/go/timing

2. See our roadmap for Timing Solutions: www.cypress.com/go/TimingRoadmaps

3. Request a preliminary datasheet: Contact Sales

4. Contact us for questions: [email protected]

Here’s How to Get Started

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APPENDIX

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001-91135 Owner: PAJE High-Performance 4-PLL Clock Generator New Product Introduction (Customer)Rev *A

Product Selector Guide

Part Number No. of Outputs Programmability Grade Package

CY27410FLTXI 12 Field Industrial 48-QFN

CY27410LTXI - XXX 12 Factory Industrial 48-QFN

CY27430FLTXA 9 Field Automotive 48-QFN

CY27430LTXA - XXX 9 Factory Automotive 48-QFN

CY 274 XX F LTX X - XXX

Part Numbering Decoder

Configuration identifier: Blank = Field programmable, XXX = Factory programmedGrade: I = Industrial, A = AutomotivePackage Type: Pb-free QFN Programmability: F = Field programmable, Blank = Factory programmedProduct Type: 10 = Industrial, 30 = AutomotiveMarketing Code: 274 = Clock Generators Company ID: CY = Cypress

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001-91135 Owner: PAJE High-Performance 4-PLL Clock Generator New Product Introduction (Customer)Rev *A

References and LinksCypress Timing Solutions Website: www.cypress.com/go/timing

Timing Solutions Roadmap: www.cypress.com/go/TimingRoadmaps

Product Overview: www.cypress.com/go/CY27410

Programming and Evaluation Kits: www.cypress.com/go/TimingKits

Software: www.cypress.com/go/TimingSoftware

Application Notes: www.cypress.com/go/TimingAppNotes

Contact us for questions: [email protected]

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001-91135 Owner: PAJE High-Performance 4-PLL Clock Generator New Product Introduction (Customer)Rev *A

System BOM1 CY27410 IDT5V49EE902NLGI8 SI5338M-B-GMRClock Generator $ 7.50 $ 5.63 $ 8.80

Additional Single-Ended Outputs2 3.43 1.43

Additional Differential Outputs3 1.78 2.26

VCFS/Glitch-Free Outputs4 1.04

Low-Frequency Support5 0.46 0.46

Total System Cost $ 7.50 $ 11.30 $ 13.99

Savings by using CY27410 34% 46%

1 1ku Digikey pricing on 07/30 /2014 (SL15300 price is for 2.5ku)2 IDT5V49EE902 can generate nine LVCMOS frequencies and needs IDT5V19EE403NLG18 to generate the remaining three LVCMOS frequencies to match CY27410   SI5338 can generate eight LVCMOS frequencies and needs SL15300ZCT to generate the remaining four LVCMOS frequencies to match CY274103 IDT5V49EE902 can generate two differential frequencies and needs IDT74FCT3807DCGI to generate the remaining six differential frequencies to match CY27410  SI5338 can generate four differential frequencies and needs SI52144-A01AGM to generate the remaining four differential frequencies to match CY274104 SI5338 requires SI5351A-B-GT to provide VCFS and glitch-free outputs5 IDT and SiLabs require an external crystal MC-306 32.7680K-A0:ROHS (1ku pricing) to support low-frequency RTC outputs (32.768 kHz)

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CY27410 Value vs. Competition