Seattle Pacific University EE 1210 - Logic System DesignFSM-1 Elevator Controller We’re hired to...

Seattle Pacific University EE 1210 - Logic System Design FSM-1

Elevator Controller• We’re hired to design a

digital elevator controller for a four-floor building

00

01

10

11• 1st try: Design a counter that counts up and down

• 00, 01, 10, 11, 10, 01, 00, ...• Problem: Never stops!

• 2nd try: Add “Stop” button that disables counter

• Problem: Have to press button when elevator happens by

• We need a way to have user inputs into a complex system


Finite State Machines

• Counters - Next state based on current state

• If counter is in state ‘101’, next state is ‘110’

• No inputs (other than reset, enable)

• Finite State Machines

• Next state is a function of the current state and the inputs

• If the elevator is on floor 00 and the UP button is pressed on floor 10, then move to floor 01

• If current state is 00 If UP2, Next state is 01


A Finite State Machine

CombinationalLogic

For Next State

Comb.LogicFor

Outputs

OutputsStateFlipFlops

ClockClock

CurrentState

NextState

InputsElevator Buttons

Motor/Door Controls

Current floor/

direction

Next floor/ direction

Example shown for elevator controller


Gumball Machine

• We’re building a gumball machine

• 15 cents for a gumball

• Machine has a single slot, which can take dimes or nickels

• Subcontractor provides a coin sensor, which has two outputs:

• N is true if a nickel was input• D is true if a dime was input

• We must provide the output Open when 15 cents entered

GumballMachine

FSM

N

D

Reset

Clk

OpenCoin

SensorCandy

Release Mechanism


Gumball Machine

Tabulate typical input sequences:three nickelsnickel, dimetwo nickels, dimetwo dimes dime, nickel

Draw state diagram:Inputs: N, D, reset

Output: open

Diagram what is going on in a state diagramS0

S1 S2

S3[open=1]

S4

[open=1]

S5[open=1]

S6

[open=1]

S8[open=1]

S7

D

DD

D

N

N

N

N

Reset

Output (open) indicatedduring states in which isis asserted

Note: No change provided!

N’D’

S0

N

S1

D

S2N’D’

S0

N

S1

D

S2

N’D’

S0

N

S1

D

S2N’D’

S0

N

S1

D

S2N’D’

S0

N

S1

D

S2

N’D’

N’D’

N’D’

N’D’


A More Efficient Solution

Reuse states whenever possible

Symbolic State Table

0¢

5¢

10¢

D

D

N

N

N+D

Reset

15+¢[open=1] 15+¢

15+¢

0¢5¢

10¢X

15+¢

10¢

10¢5¢

X

X

5¢X

0¢

10¢

QCurrent

State

OpenOutput

0¢ 0

5¢ 0

10¢ 0

15+¢ 1

0010¢1010¢0110¢

115¢

1110¢0015+¢1015+¢0115+¢1115+¢

015¢105¢005¢110¢010¢100¢000¢

Q+Next State

NInput

DInput

QCurrent

State

Output Table

N’D’N’D’

N’D’

N’D’

D

N


Gumball Machine State Table

Encode states into binary numbers

Calculate total number of states: 4 (0¢, 5¢, 10¢, 15¢)

Use as many bits as needed for the states 4 states --> 2 bits

Encoding: 0¢: 005¢: 0110¢: 1015+¢: 11

Calculate total number of states: 4 (0¢, 5¢, 10¢, 15¢)

Use as many bits as needed for the states 4 states --> 2 bits

Encoding: 0¢: 005¢: 0110¢: 1015+¢: 11

Encoded State TableX100X111X110X100

011

X

X010X

101X010

1111111100000000

000

1

01111

1110000

Q1Q0Current

State

001001

11

1100100111

01100011011000

Q1+Q0

+

Next State

NInput

DInput

Q1Q0Current

State

OpenOutput

0 0 0

0 1 0

1 0 0

1 1 1

Output Table


Gumball Machine Implementation

Q1Q0

DN 00 01 11 10

00

01

11

10

Q1

Q0

D

N

D1

1

0

x

1 x 0

0

1

1

x

1

0 1

0 x

1

Q1Q0

DN 00 01 11 10

00

01

11

10

Q1

Q0

D

N

D0

1

1

x

0 x 0

0

1

0

x

1

1 0

1 x

0

D1= D + NQ0Q1’ + Q0’Q1

D2= NQ0’ + N’Q1’Q0 + NQ1 + DQ1Q0’

Open = Q1Q0

Note that the output is a function of only the state

If we chose D FF’s, we don’t have to convert Q’s to FF inputs

Q1Q0Current

State

OpenOutput

0 0 0

0 1 0

1 0 0

1 1 1


Inputs

• FSMs change state based on clock edges

• I.e. Rising clock edge clocks all FFs

This part can change only when clock “ticks”

CombinationalLogic

For Next State

Comb.LogicFor

Outputs

StateFlipFlops

ClockClock

Inputs

This part can change at any time

Synchronous Inputs: Change in synch with the clock. Obey setup and hold time.

Asynchronous Inputs: Change at any time. May violate setup and hold times.


Asynchronous vs. Synchronous Inputs

• Asynchronous • Synchronous• Example: Elevator pushbuttons

• Arrive at any time

• Usually asserted for many clock cycles

• FSM logic must not make any assumptions about input timing

• Example: Data arriving on a serial line from a computer

• Arrive synchronized exactly to a clock

• One bit of data per clock cycle

• FSM can assume that data changes once per clock cycle


Parity CheckerAssert output (parity) whenever input bit stream (synchronous) has odd # of 1's

QPresent State

InInput

Q+Next State

Even 0 0 Even 0

Even 0 1 Odd 1

Odd 1 0 Odd 1

Odd 1 1 Even 0

0 1 1 1 10 0 0 0 0 0

0 0 1 1 1 0 1 1 1 1 0

Clk

Input

Output

State Diagram

Even [0]

Odd [1]

Reset

InIn

In’

In’

QPresent State

ParityOutput

Even 0 0

Odd 1 1

Q+ = Q In

Parity = Q


Parity Checker

• Parity Checking is a type of Synchronous Serial Input FSM

• A single input

• Input is synchronized with clock (1 bit per clock cycle)

• Goal is to look for patterns in the input bit stream

D FF Implementation T FF Implementation

D QClr

ParityIn

Reset

T QPre

Clr

ParityIn

Reset

Q+ = Q In Parity = Q


Pattern Matcher

A string recognizer has one synchronous input (X) and one output (Z).The output is asserted whenever the input sequence …010…has been observed, as long as the sequence …100… has never been seen.

Sample input/output behavior:

00010000000Z:

01001011011X:

00010101000Z:

01001010100X:

This is a synchronous serial input problem

1. Work though sample inputs to understand problem2. Develop FSM to recognize patterns3. Implement using standard techniques


Pattern Matcher

1. Pick a reset state.2. Draw paths for strings to recognize (010

and 100)3. Fill in all of the missing transitions (each

state needs a path out for 0 and 1)

Reset signal places FSM in S0

Outputs 1Loops in State

S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0] 0+1

Reset

1

0 0

0

0 1

...010

...100

State S3: have recognized …010 if next input is 0 then have …0100 (state S6)

if next input is 1 then have …0101 = …01 (state S2)

0

1

State S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0

...01 State S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1

...0

0

...1

1

State S2: if input is 1, then have …1 (state S4)

State S5: recognizes …10 if input is 1, then have …01 (state S2)

...1011


Pattern Matcher - Implementation

1. Assign each state a binary number

2. Make the state transition table3. Make the output table

S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0] 0+1

Reset

1

0 0

0

0 1

0

1

0 1

11

Current State Input Next StateQ2 Q1 Q0 X Q2 Q1 Q0

0 0 0 0 0 0 10 0 0 1 1 0 00 0 1 0 0 0 10 0 1 1 0 1 00 1 0 0 0 1 10 1 0 1 1 0 00 1 1 0 1 1 00 1 1 1 0 1 01 0 0 0 1 0 11 0 0 1 1 0 01 0 1 0 1 1 01 0 1 1 0 1 01 1 0 0 1 1 01 1 0 1 1 1 01 1 1 0 X X X1 1 1 1 X X X

000

001

010

011

110

101

100


Pattern Matcher - Implementation

1. Assign each state a binary number

2. Make the state transition table3. Make the output table

Current State Output

Q2 Q1 Q0 Z0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 01 1 0 01 1 1 X

S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0] 0+1

Reset

1

0 0

0

0 1

0

1

0 1

11

000

001

010

011

110

101

100

Build the FSM:• Use three FF’s• Build next state logic based on

state transition table• Build output logic based on

output table

Seattle Pacific University EE 1210 - Logic System DesignFSM-1 Elevator Controller We’re hired to...

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