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SC2000/5 CPU and SubsystemsSC2000/5 CPU and Subsystems
Bob Mathews
DTV Source Applications
Broadband Entertainment Division
July 2001
CPU and subsystems - July 20014-2LSI Logic Confidential™
CPU and SubsystemsCPU and Subsystems
EZ4102 core Complete details in TinyRISC EZ4102 Tech. Manual
(doc.no. DB14-000080-01) EJTAG Debug Tools E-Bus - External System Bus SDRAM-B controller BBus DMA Controller (SC2005)
CPU and subsystems - July 20014-3LSI Logic Confidential™
SC2000 Block DiagramSC2000 Block Diagram
Channel
Debug Port
E-Bus
CPU/OSG/XPT/Periph SDRAM I/F
TinyRISC CPU
Transport Demultiplexer andDVB Descrambler
2 GP Peripheral DMA
Audio/Video Decoder(L64105 core)
VideoMixer and Encoder
On-Screen Graphics
A/V SDRAM I/F
ModemI/F
InfraredSmartCard 1
IEEE1284
SmartCard 0
UART 1TeleText
I2C GPIOUART 0
27 MHzClock
IEE1284 Smart Cards RS232C Telephone I/R RX I/R TX I2C Front Panel
S-Bus
I-Bus
EZ4102
CPU and subsystems - July 20014-4LSI Logic Confidential™
CPU SubsystemCPU Subsystem
EZ4102 Core and MDU BBCC and Cache Controller MMU Stub and Memory Map BBus interfaces Timers Interrupt controller EJTAG
CPU and subsystems - July 20014-5LSI Logic Confidential™
CPU Subsystem Block DiagramCPU Subsystem Block Diagram
CPU
External E-Bus
MDU
BBCC
I-Cache
D-Cache
C-Bus B-Bus
E-Bus ctrl
I-Bus ctrlInternal
I-BusTimers
Flex
Link
IRQ-Ctrl
MMU Stub
Internal S-BusS-Bus ctrl
ICE
Statistic
External ICE pins
4
CPU and subsystems - July 20014-6LSI Logic Confidential™
EZ4102 Block DiagramEZ4102 Block Diagram
4102 CPU
EZ4102 EasyMACRO Microprocessor Subsystem
Timers
UART
EJTAGFlexLink
CBus
Caches and Tags
BBus
EJTAG Interface
SerialICE™-1 Interface
MMU
EJTAG Extended Debug MACRO
BIU and Cache
andFastMDU
Controller (BBCC)
TLB RAM
PC Trace Output
ClockController
32-bit TinyRISC
22
CPU and subsystems - July 20014-7LSI Logic Confidential™
CPU FeaturesCPU Features
108 MHz TinyRISC EZ4102 Core 16 Kbytes two-way set associative instruction cache 8 Kbytes direct mapped data cache MDU - multiply/divide unit MMU – translates virtual addresses from the CPU
into physical addresses
CPU and subsystems - July 20014-8LSI Logic Confidential™
Instruction SetInstruction Set
Executes MIPS-I, MIPS-II and MIPS 16 instruction sets
Details in mips RISC ARCHITECTURE by Gerry Kane Approx. 40% code size reduction 16- and 32-bit code can be mixed 3 types of Instruction, Immediate, Jump and Register All instructions execute in 1 cycle except loads,
stores and move control
CPU and subsystems - July 20014-9LSI Logic Confidential™
TinyRISC OperationTinyRISC Operation
3-stage Pipeline, Fetch, Execute, Writeback 32-bit Memory and Cache interface Comprises a Register File, Co-Processor, ALU and Shifter
Register file supplies source operands to the execution units Register files handles the storage of results to the target
registers System Co-Processor processes exceptions including
interrupts ALU performs arithmetic and logical operations ALU performs address calculations Shifter operation is self explanatory
CPU and subsystems - July 20014-10LSI Logic Confidential™
Multiply and Divide UnitMultiply and Divide Unit
32 x 32 bit signed and unsigned Integer Multiplication 32 x 32 bit signed and unsigned Integer Multiplication and
Accumulation 5 cycle latency on all Multiplication 32 bit signed and unsigned Division 34 cycle latency for Quotient 35 cycle latency for Remainder Supports Move From and Move To instructions
CPU and subsystems - July 20014-11LSI Logic Confidential™
BBCC FeaturesBBCC Features
Basic BIU and Cache Controller Bridge between CPU C-Bus and B-Bus interfaces Controls access to on-chip caches Consists of the following modules:
Cache controller Queue controller B-Bus controller System Configuration module
CPU and subsystems - July 20014-12LSI Logic Confidential™
BBCC Block DiagramBBCC Block Diagram
TR4102 BBCC
CBus
WriteBuffer
Caches
B-Bus
ICE
I-Bus
ControllerS-Bus
E-Bus
Controller
Controller Controller
CPU and subsystems - July 20014-13LSI Logic Confidential™
BBCC Internal Block DiagramBBCC Internal Block Diagram
Queue
Cache
B-BusTR4102 B-Bus
BSYS
WriteBuffer
Reset and System
System
Refill Control
Queue Information
Queue Control
Cache Information
Cache RAMs
Conf iguration
(CBus)
Register
Register Control
Configuration
Output
Controller
Controller
Controller
CPU and subsystems - July 20014-14LSI Logic Confidential™
Cache Controller FeaturesCache Controller Features
16 Kbytes two-way set associative I-cache 8 Kbytes direct mapped D-cache Programmable block refill sizes for I-cache and D-
cache Instruction Set 0 Line Locking Software Cache Test Mode
CPU and subsystems - July 20014-15LSI Logic Confidential™
Cache Controller OperationCache Controller Operation
Controls the Instruction and Data Caches Identifies Instruction and Data transactions to see if line is
in Cache If line is in Cache then it performs requested transaction
Cache Controller informs the Queue Controller of hit or miss
Cache Controller lets the Bus Controller read and write from and to the Cache and Tag RAMs
The Caches are clocked at 108 MHz
CPU and subsystems - July 20014-16LSI Logic Confidential™
Queue ControllerQueue Controller
Orders memory requests to SDRAM-B Consists of three queues:
Instruction fetch queue Data fetch queue Data store queue (32-bit write buffer)
Operation QC monitors the EZ4102 memory transaction signals and enters
requests into appropriate queues QC arbitrates among requests in the queue and generates
requests to the Bus Controller QC issues Ready signals and stalls the system when necessary
CPU and subsystems - July 20014-17LSI Logic Confidential™
B-Bus ControllerB-Bus Controller
B-Bus is bus interface between CPU and: S-Bus, E-Bus, I-Bus and ICE Port
32-bit Address and Data Bus width 0 to n Wait States 1, 2, 4 and 8 word Burst transactions Write burst transactions Back-to-back transactions Bus Error and Retry reporting Multiple Bus Masters possible
CPU and subsystems - July 20014-18LSI Logic Confidential™
MMU StubMMU Stub
Operates when the MMU soft mapping is disabled. Hard Maps kseg0 and kseg1 virtual CPU addresses
to the lower 512 MB of physical memory
Virtual address Physical address
0x8000.0000 - 0x9FFF.FFFF (kseg0) 0x0000.0000 to 0x1FFF.FFFF
0xA000.0000 - 0xBFFF.FFFF (kseg1) 0x0000.0000 to 0x1FFF.FFFF
(MMU soft mapping is not used by LSI FTA application code.)
CPU and subsystems - July 20014-19LSI Logic Confidential™
Global Memory MapGlobal Memory Map
Address[31:29]
VirtualAddress Area
PhysicalAddress Area
Used Name
000 – 0110x0000.0000
to0x7FFF.FFFF
0x0000.0000to
0x7FFF.FFFFNo kuseg
1000x8000.0000
to0x9FFF.FFFF
0x0000.0000to
0x1FFF.FFFFYes kseg0
1010xA000.0000
to0xBFFF.FFFF
0x0000.0000to
0x1FFF.FFFFYes kseg1
110 - 1110xC000.0000
to0xFFFF.FFFF
0xC000.0000to
0xFFFF.FFFFNo kseg2
CPU and subsystems - July 20014-20LSI Logic Confidential™
CPU Memory MapCPU Memory Map
Cache(kseg0)
Non-Cache(kseg1)
PhysicalAddress Start
PhysicalAddress End
Size Description
Yes Yes 0x0000.0000 0x00ff.ffff 16 MB S-bus address space
N/A N/A 0x0100.000 0x03ff.ffff 48 MBReserved for expansion ofSMEM
N/A N/A 0x0400.0000 0x0fff.ffff 192 MB Reserved
Yes Yes 0x1000.0000 0x13ff.ffff 64 MBE-Bus address space(32 bit)
Yes Yes 0x1400.0000 0x17ff.ffff 64 MBE-Bus address space(16 bit)
No Yes 0x1800.0000 0x1bff.ffff 64 MBE-Bus address space(8 bit)
N/A N/A 0x1c00.0000 0x1dff.ffff 32 MB Reserved
No Yes 0x1e00.0000 0x1eff.ffff 16 MB I-Bus address space
Yes Yes 0x1f00.0000 0x1ffe.ffff 15.9 MBE-Bus address space(boot vector)
No Yes 0x1fff.0000 0x1fff.0003 4 bytes BBCC register
No Yes 0x1fff.0004 0x1fff.ffff 63.9 KB ICE port registers
CPU and subsystems - July 20014-21LSI Logic Confidential™
E-Bus ControllerE-Bus Controller
External system bus connects to external memory and peripherals discussed in later section
CPU and subsystems - July 20014-22LSI Logic Confidential™
I-Bus ControllerI-Bus Controller
Provides CPU access to internal SC2000 registers including A/V and peripheral function
Software must use non-cache addresses to access this region
I-Bus controller manages acknowledge handshakes and wait states to these registers
No software configuration required
CPU and subsystems - July 20014-23LSI Logic Confidential™
I-Bus Address MapI-Bus Address Map
Subsystem CPU Start Address CPU End Address Size
CPU and E-Bus 0xbe00.0000 0xbe0f.ffff 1 Mbyte
SDRAM Controller 0xbe10.0000 0xbe1f.ffff 1 Mbyte
Transport 0xbe30.0000 0xbe3f.ffff 1 Mbyte
A/V Decoder 0xbe40.0000 0xbe4f.ffff 1 Mbyte
OSG 0xbe60.0000 0xbe6f.ffff 1 Mbyte
Mixer / Encoder 0xbe50.0000 0xbe5f.ffff 1 Mbyte
Peripherals 0xbe20.0000 0xbe2f.ffff 1 Mbyte
Reserved 0xbe70.0000 0xbeff.ffff 9 Mbytes
CPU and subsystems - July 20014-24LSI Logic Confidential™
TimersTimers
Four general-purpose timers Timers 0/1 run at 54 MHz Timers 4/5 run at 108 MHz One-shot mode or continuous count down mode
Timer 2 - Watchdog Resets the CPU if watchdog expires twice and interrupt is not
serviced Timer 3 - Access Surveillance
Monitors accesses from CPU as well as the E-Bus write pipeline Generates bus error if timer expires before access completes
Interrupt capability provided for all timers
CPU and subsystems - July 20014-25LSI Logic Confidential™
Interrupt ControllerInterrupt Controller
Decoder Encoder OSGTransport GPIO’sDMA 1284Modem i2cTeletext Infra Red SmtCrdsUarts Timers
R R R R R R R R R 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Interrupt Controller
(CQBUSINTS) 0-31,
SC2000Interrupt
ControllerModule
Status Register
(1 = Pending)
The incoming interrupts from theSC2000’s peripherals, are routed to any of the 6 CPU Core interrupts, byexclusiviely setting the corresponding bitin one of the six CQBusIntX registers.
CQBusInt5 CQBusInt4 CQBusInt3 CQBusInt2 CQBusInt1 CQBusInt0
IP5 IP4 IP3 IP2 IP1 IP0 sw1 sw0 0 0 0 0ExcCode MIPS CPU CoreCause Register
(IP Bits givePending Status)
INT5 INT4 INT3 INT2 INT1 INT0 SW1 SW0 IEC0 MIPS CPU CoreStatus Register(INT Bits allow
masking of interrupts)SC2000’s MIP CPU Core
CPU and subsystems - July 20014-26LSI Logic Confidential™
Interrupt ControllerInterrupt Controller
22 I-Bus Interrupt Lines Interrupts from all subsystems are grouped onto one bus
all_intp[31:0] Can be routed to any of the six MIPS core interrupt inputs Level-sensitive interrupts
INTC registers Interrupt Control - CQBUSINT[5:0] - creates interrupt matrix Interrupt Status - CQBUSINTS - provides status of I-Bus interrupts MIPS Cause register - provides status of six MIPS interrupts MIPS Status register - provides mask capability for six MIPS
interrupts Interrupt priority and handling is software-driven
CPU and subsystems - July 20014-27LSI Logic Confidential™
SC2000 Product TrainingSC2000 Product Training
EJTAG Debug Tools
CPU and subsystems - July 20014-28LSI Logic Confidential™
EJTAG Debug ToolsEJTAG Debug Tools
Agenda Overview Features Benefits Description
CPU and subsystems - July 20014-29LSI Logic Confidential™
EJTAG Debug OverviewEJTAG Debug Overview
EJTAG is a non-intrusive on-chip debug standard adopted by the MIPS partners.
LSI Logic follows the EJTAG revision 1.5.3 specification for its TinyRISC and MiniRISC CPU cores.
Current EJTAG Debug Solution: Runs only on PC platforms (Windows 95, 98, NT). Supported with LSIDBG.EXE (download DIL 2.x) Works only with Green Hills MULTI 1.8.9 (or later) toolchain. Does not support PC Trace (i.e. supports only hardware
breakpoints). All features are not available in all probes
CPU and subsystems - July 20014-30LSI Logic Confidential™
EJTAG Debug EnvironmentEJTAG Debug Environment
PC
Green HillsMULTI 1.8.9
BDMR4102Evaluation Board
EJTAGProbe
P ara lle l C ab le EJTAG
With EJTAG Connector
Macraigor Raven probe and EPI Majic Probes supported.EPI (Embedded Performance In. solution supports both run-time control and PC Trace capture.LSI Logic Milpitas uses Macraigor probe extensively; has no experience with EPI probe.
CPU and subsystems - July 20014-31LSI Logic Confidential™
EJTAG FeaturesEJTAG Features
Non-intrusive communication between debug resources and EJTAG probe through standard JTAG interface Test Access Port.
DMA access through EJTAG interface for memory inspection/manipulation and code download.
Processor access through EJTAG interface, eliminating debug code on target.
Dedicated debug exception vector and instructions. Software Debug Break (SDBBP) Debug Exception Return (DERET)
CPU and subsystems - July 20014-32LSI Logic Confidential™
EJTAG Features (cont.)EJTAG Features (cont.)
Special CP0 registers for debug exception processing. Debug Exception Program Counter (DEPC) register Debug Exception Save (DESAVE) register
Hardware single step - automatic generation of debug exception after each executed instruction.
Break module consisting of: 2 Instruction Break channels 2 Data Break channels 2 Processor Break channels
Real-time program counter trace for monitoring CPU execution.
CPU and subsystems - July 20014-33LSI Logic Confidential™
EJTAG Probe AdvantagesEJTAG Probe Advantages
EJTAG Probe Advantages over Emulators: Low pin-count interface needed to connect EJTAG Probe to
target system. No probing effects on target signals. EJTAG Probe can be re-used for other processor derivatives. EJTAG interface on target board can also be used for board
testing and diagnostics. EJTAG Probe Advantages over ROM Monitors:
No need for debug monitor on target board. No serial port required on target system.
Required for code download/flash programming on EVB2005
CPU and subsystems - July 20014-34LSI Logic Confidential™
CPU System with EJTAG Resources CPU System with EJTAG Resources
CPU
M M U
BreakM odule
BBCC
PCTrace
EJTAGInterface
M emory
Cache
Data
V irtual Address
PhysicalAddress
Break Trigger
PC Trace Output
TAP Port
Data
PhysicalAddress
CBus BBus
Ext
Deb
ug
MA
CR
OE
asyM
AC
RO
CPU and subsystems - July 20014-35LSI Logic Confidential™
EasyMACRO ModuleEasyMACRO Module
Provides basic debug capabilities. Full EJTAG interface enabling:
Fast code download DMA access Processor access via EJTAG probe
Debug exception processing with: Associated CP0 registers EJTAG Debug instructions for software breaks
Hardware Single Step
CPU and subsystems - July 20014-36LSI Logic Confidential™
Extended Debug MACROExtended Debug MACRO
Break Module Provides hardware breaks triggered by instruction and
data transactions on virtual and physical addresses as well as data values.
Eliminates inserting SDBBP instructions into application code.
Allows breaks in ROM code. Real-time Program Counter Trace
Monitor CPU execution (cache or un-cached) in virtual address space.
CPU and subsystems - July 20014-37LSI Logic Confidential™
EJTAG RegistersEJTAG Registers
Occupies address range 0xFF30.0000 to 0xFF3F.FFFF. Debug Control Register (DCR) Break Module Registers
Extended CP0 Debug Registers: Debug register indicates cause of debug exception. DEPC contains address in user application where execution
should resumed after debug exception. DESAVE is used as temporary storage when saving register file. Full access is only available in debug mode.
CPU and subsystems - July 20014-38LSI Logic Confidential™
EJTAG Interface OverviewEJTAG Interface Overview
PIN DESCRIPTION
TCK Test Clock InputTDI_DINT Test Data Input / Debug InterruptTDO_TPC Test Data Output / Target PC OutputTMS Test Mode Select InputTRST Test Reset InputRST Reset InputDCLK Processor ClockPCST PC Trace Status Information
CPU and subsystems - July 20014-39LSI Logic Confidential™
Break Module OverviewBreak Module Overview
Instruction Break Channel Compares instruction break address with virtual address of
instructions fetched from memory or cache. Data Break Channels
Compares a data break address with virtual address of load/store data transactions from memory, cache, or I/O.
Load/store data can also be compared. Processor Bus Break Channels
Compares a break address with physical address of all bus transactions, which includes:
Instruction fetches Data load/store from memory, cache, or I/O.
Data Value can also be compared.
CPU and subsystems - July 20014-40LSI Logic Confidential™
PC Trace OverviewPC Trace Overview
PC Trace outputs the following: Status codes identifying type of executed instructions (one
code per clock cycle). Virtual address is output serially when sequential program flow
is altered by a jump, branch, or an exception. Output Trace is used by debug host to explore behavior
of CPU; Routines executed Interrupts serviced
CPU and subsystems - July 20014-41LSI Logic Confidential™
PC Trace Overview (cont.)PC Trace Overview (cont.)
The EJTAG probe will record a trace around an event triggered by the Break module.
Allows trace of processor execution even with caches enabled.
On-chip debug logic can detect any changes in program flow. Code branches are output via EJTAG debug port in real-time
and captured in trace memory of EJTAG probe. Host computer software will re-construct address of all
executed instructions by processing raw trace data.
CPU and subsystems - July 20014-42LSI Logic Confidential™
More Information on EJTAGMore Information on EJTAG
EJTAG Revision 1.5.3 Specification Intranets Sites:
MIPS Applications web site http://eng-www/documents/consumer/applications
MIPS System Software web site http://saltlake
Source for download of LSI MIPS tools MIPS Marketing web site
http://planet/products/consumer/mips/mipsmktg
CPU and subsystems - July 20014-43LSI Logic Confidential™
SC2000 Product TrainingSC2000 Product Training
E-Bus - External System Bus
CPU and subsystems - July 20014-44LSI Logic Confidential™
Ebus - external system busEbus - external system bus
Agenda for Ebus discussion Features / Overview Signals Mux/demux bus configuration Ebus address areas Timing overview Ebus register descriptions Boot read Examples Ebus programming guide External bus master mode ATA interface support (SC2005)
CPU and subsystems - July 20014-45LSI Logic Confidential™
Ebus featuresEbus features
Highly flexible, highly programmable bus interface Programmable timing for control, address and data Programmable wait states Burst mode support (e.g. synchronous flash)
Multiplexed or demultiplexed bus configuration 64 Mbyte virtual Ebus address space Automatic scatter/gather operations Six chip selects - CSn[5:0]
CSn5 can be used as MEMSTBn (via strap option) Support for external bus master
CPU and subsystems - July 20014-46LSI Logic Confidential™
System block diagramSystem block diagram
CPU
External E- Bus
MDU
BBCC
I-Cache
D-Cache
C-Bus B-Bus
E-Bus ctrl
I-Bus ctrlInternal
I-BusTimers
Fle
xLin
k
IRQ-Ctrl
MMU Stub
Internal S-BusS-Bus ctrl
SerialICE port
Statistic
External ICE pins
CPU and subsystems - July 20014-47LSI Logic Confidential™
CPU address
Address SpaceName
Noncachekseg1
Cachekseg0
Bbusaddress
Ebusaddress
External ROM(Flash memory)
0xBFDF.FFFF -0xBFC0.0000
0x9FDF.FFFF -0x9FC0.0000
0x1FDF.FFFF -0x1FC0.0000
0xDF.FFFF -0xC0.0000
8-bit Ebusaddress area
0xBBFF.FFFF -0xB800.0000
0x9BFF.FFFF -0x9800.0000
0x1BFF.FFFF -0x1800.0000
0xFF.FFFF -0x00.0000
16-bit Ebusaddress area
0xB7FF.FFFF -0xB400.0000
0x97FF.FFFF -0x9400.0000
0x17FF.FFFF -0x1400.0000
0xFF.FFFF -0x00.0000
32-bit Ebusaddress area
0xB3FF.FFFF -0xB000.0000
0x93FF.FFFF -0x9000.0000
0x13FF.FFFF -0x1000.0000
0x13FF.FFFF -0x1000.0000
Ebus address mapEbus address map
CPU and subsystems - July 20014-48LSI Logic Confidential™
Ebus signals - internal bus masterEbus signals - internal bus master
AD[31:0] - multiplexed address/data bus ADDR[7:0] - fixed address outputs ALE - address latch enable BEn[3:0] - byte enables for four byte lanes CSn[5:0] - chip select outputs
Watch out for default values - see CEPINMODE register EACKn - acknowledge input INTn[4:0] - interrupt inputs MEMSTBn - memory strobe RDn - read strobe WRn - write strobe
CPU and subsystems - July 20014-49LSI Logic Confidential™
Mux/demux bus configurationMux/demux bus configuration
Mux bus - 32-bit address/data AD[31:0] signals used Required for external devices with 32-bit data bus External address latch required
Demux bus - 24-bit address, 16-bit data Can be used by 8- and 16-bit peripherals with maximum
24-bit addressing (16 Mbytes per chip select) No external components required AEN bit is set, AHLDF field is zero
CPU and subsystems - July 20014-50LSI Logic Confidential™
Ebus addressingEbus addressing
8-, 16- and 32-bit devices are mapped to specific CPU/Ebus address areas
32-bit 0x1000.0000 to 0x13FF.FFFF 64 Mbytes 16-bit 0x1400.0000 to 0x17FF.FFFF 64 Mbytes 8-bit 0x1800.0000 to 0x1BFF.FFFF 64 Mbytes
Note: Only the lower 24 address bits are physically output in the demux mode
Automatic scatter/gather operations Scatter used for Ebus writes Gather used for Ebus reads BEn[3:0] signals are used to control four byte lanes
CPU and subsystems - July 20014-51LSI Logic Confidential™
first_ack next_ack last_ack
0ns 50ns 100ns 150ns
54 MHz
access_ready
RDn
Ebus timing overviewEbus timing overview
An Ebus cycle consists of three internal timing references:
first_ack - beginning of cycle next_ack - used for burst transactions last_ack - end of cycle
CPU and subsystems - July 20014-52LSI Logic Confidential™
Ebus timing controlEbus timing control
Independent timing control for each address area Areas 5 to 0 - correspond to CSn[5:0] All device using common chip select must conform to Ebus
timing for that area Symmetrical timing control for:
CSn[5:0] RDn WRn MEMSTBn ALE
Additional timing control for: Address setup/hold, data setup/hold
CPU and subsystems - July 20014-53LSI Logic Confidential™
Ebus acknowledge modesEbus acknowledge modes
Self-acknowledge mode EACKn input is disabled (XACK bit is reset) Bus cycle width is determined by number of wait states
Device-acknowledge mode Ebus generates programmed wait states
EACKn input is ignored during this time After wait states have expired, Ebus checks for
EACKn assertion to complete cycle Zero waits states can be used in device acknowledge
mode
CPU and subsystems - July 20014-54LSI Logic Confidential™
Ebus register summaryEbus register summary
Address compare registers CEACMPx
Strobe timing registers CERWx, CECSx, CEMSTBx, CEALE
Configuration registers CECFGx, CEWAITx
Default registers CERWD, CECFGD, CEWAITD
Global registers CEBUSMODE, CEPINMODE, CEFLUSH, CEBOOT
CPU and subsystems - July 20014-55LSI Logic Confidential™
Ebus address compare registersEbus address compare registers
CEACMPx One for each chip select
any Ebus address not decoded is subject to default register settings
Address compare enable bit (EN) Address compare value for CPU address
i.e. 0x1XXX.0000 Ebus address maximum 64 Mbyte address range
Compare mask control same resolution as ESB, but larger address range 64k, 128k, 256k, … 16M, 32M, 64M
CPU and subsystems - July 20014-56LSI Logic Confidential™
Ebus strobe timing registersEbus strobe timing registers
CERWx RDn and WRn timing control CECSx CSn[5:0] timing control CEMSTBx MEMSTBn timing control CEALE ALE timing control
Assertion/deassertion control relative to first_ack, next_ack, last_ack
Programmable delay for assertion/deassertion time Common scheme used for all strobe timing registers
CPU and subsystems - July 20014-57LSI Logic Confidential™
Ebus configuration registersEbus configuration registers
CECFGx Determines mux/demux bus (AEN, AHLDF bits) AHLDF - Full address hold time
AHLDF = 0 used for demux bus AHLDF > 0 used for address hold in mux mode
BUSHR/BUSHW bus inactive time after last_ack (minimum one clock) also defines address hold time for last_ack edge
AHLDR/AHLDW address hold time for next_ack only
CPU and subsystems - July 20014-58LSI Logic Confidential™
Ebus configuration registersEbus configuration registers
SAMPD - read sample delay from next_ack, last_ack use SAMPD = 0 for most devices use SAMPD > 0 for pipelined devices (i.e. sync flash)
SYN27 - synchronize to 27 MHz valid only for slower synchronous devices
XACK used to enable/disable EACKn input
MSTB determines whether to use memory strobe timing defined by
CEMSTB0 or CEMSTB1 register RBC/WBC
controls read/write burst mode
CPU and subsystems - July 20014-59LSI Logic Confidential™
Ebus wait statesEbus wait states
CEWAITx Determines overall cycle time of each Ebus transaction WAITF - programmable wait states for first access
wait counter starts on first_ack edge WAITN - programmable wait states for next access
wait counter starts on next_ack edge used only for burst mode accesses
CPU and subsystems - July 20014-60LSI Logic Confidential™
Ebus global registersEbus global registers
CEBUSMODE CDD0 - enabled CSn0 to use default register settings WBE - write buffer enabled (used for write bursts) XPOS - polarity select for the EACKn input XSYNC - synchronize the EACKn input
CEPINMODE Need to enable CSn3 and CSn4 outputs (defaults are set
for external bus master) Also configures chip selects as interrupt outputs to
external processor
CPU and subsystems - July 20014-61LSI Logic Confidential™
Ebus boot readEbus boot read
Chip Select 0 used for boot access Default timings set to maximum wait states, non-
burst mode Optimize Ebus setting in initialization code
Default registers can be used to switch chip select settings
CPU and subsystems - July 20014-62LSI Logic Confidential™
first_acklast_ack
pot. first
AD[23:8]
AD[7:0]
RD
CLK54
CSn[x]
RDn
AD[31:16]
ADDR[7:0]
ACKn
AD[7:0]
Ebus read for a typical 8/16-bit deviceEbus read for a typical 8/16-bit device
Demux mode Wait states = 9, read sample delay = 0 CSn assertion = 0T, deassertion = 1T RDn assertion = 1T, deassertion = 1T Device acknowledge mode enabled, EACKn is active low
CPU and subsystems - July 20014-63LSI Logic Confidential™
first_acknext_ack
next_acknext_ack
last_ack pot. first_ack
D0
A0
BEn0
A1
BEn1
A2 A3
BEn2 BEn3
D1 D2 D3A0,B0
CLK54
CLK27
RDn
AD[31:0]
ALE
ADDR[7:0]
BEn[3:0]
MEMSTBn
CSn[x]
ACKn
Ebus read timing for sync FLASHEbus read timing for sync FLASH
CPU and subsystems - July 20014-64LSI Logic Confidential™
Ebus programming guideEbus programming guide
Program configuration - CECFGx register Determine if demux vs. mux is required Determine if self-acknowledge or device-acknowledge
mode is required Determine if burst mode is required Program address hold times
Program CSn, RDn, WRn, MEMSTBn timing Program wait states - CEWAITx Program and enable chip select decode - CEAMPx
CPU and subsystems - July 20014-65LSI Logic Confidential™
Ebus programming examplesEbus programming examples
Refer to the DTV source software located at: /source/drivers/cpusys/ebus.s contains real Ebus programming examples for:
16-bit asynchronous flash (using demux mode) 16-bit device acknowledge components (using demux mode) 32-bit device (using mux mode)
CPU and subsystems - July 20014-66LSI Logic Confidential™
Ebus external bus master modeEbus external bus master mode
Pin Name Ext. Bus Master Description I/OCSn3 XBREQn Bus request
ICSn4 XBGRANTn Bus grant
OCSn[2:0] INTn[2:0] Interrupt OADDR[4] XBERRORn Bus error OADDR[5] XEACKn Acknowledge IADDR[6] XADDVAL Address/data valid IADDR[7] XREQn Access request I
CPU and subsystems - July 20014-67LSI Logic Confidential™
External bus master - CEPINMODEExternal bus master - CEPINMODE
Use this register to configure the proper pin functions on CSn[5:0]
CSn3 defaults to XBREQn CSn4 defaults to XBGRANTn CSn5 is configured by strap option
CPU and subsystems - July 20014-68LSI Logic Confidential™
External bus master functionsExternal bus master functions
External master must use 32-bit mux mode Not conventional SDP-2000 implements external bus master for the
SONIC ethernet device used to download program directly to system memory
CPU and subsystems - July 20014-69LSI Logic Confidential™
SC2005 - ATA disk drive supportSC2005 - ATA disk drive support
ATA interface connects to E-Bus additional four pins added (chip selects, DMA)
SC2005 supports transfer of A/V PES packets to/from the ATA interface
PIO mode 4 or DMA mode 2 supported Data rates up to 16.6 Mbytes/sec Ultra DMA is NOT supported
Internal PES transfers use the new DMA engine
CPU and subsystems - July 20014-70LSI Logic Confidential™
ATA interface connectionsATA interface connections
ATA Interface Signal SC2005 Signal
CSEL Use a GPIO or external signal
CS0- ATA_CS0n (GPIO24)
CS1- ATA_CS1n (GPIO25)
DA[2:0] ADDR[4:2]
DASP- Use a GPIO or external signal
DD[15:0] AD[15:0]
DIOR- RDn
DIOW- WRn
DMACK- DMACKn (GPIO26)
DMARQ DMARQ (GPIO27)
INTRQ Use one of the GPIO[31:28] interrupt inputs
IORDY EACKn (configured as active high, or useexternal inverter)
PDIAG- Use a GPIO or an external signal
RESET- RESETn
CPU and subsystems - July 20014-71LSI Logic Confidential™
SDRAM-B Controller FeaturesSDRAM-B Controller Features
108 MHz SDRAM clock Supports 2, 4, 8 or 16 MB of total SDRAM Supports 16, 64 and 128 Mbit SDRAM sizes 16-bit wide data bus
Can interface to one 16-bit wide device or two 8-bit wide devices
Supports 2k/4k refresh cycles every 32/64 ms Serves as memory interface for:
CPU, Transport, OSG, and peripherals DMA interface to A/V channel buffer in SDRAM-A
(A/V SDRAM-A controller is part of A/V decoder)
CPU and subsystems - July 20014-72LSI Logic Confidential™
SDRAM(s)
SMEMCPU EZ4102
TRANS
OSG
I-Bus
S-bus
DQ
Addr.Ctrl.
PERIPH
DECOD
SDRAM-B:
2, 4, 8 or 16 MB size supported
SDRAM clients
S-Bus ControllerS-Bus Controller
I-Bus Ctrl
S-Bus CtrlSDRAM-BCtrl
CPU and subsystems - July 20014-73LSI Logic Confidential™
SDRAM-B Controller OperationSDRAM-B Controller Operation
Receives requests from the buffer clients (subsystems) Services requests in the order chosen by the Arbiter Generates the SDRAM Read, Write and Precharge
commands Generates the Refresh commands
CPU and subsystems - July 20014-74LSI Logic Confidential™
Programmable SDRAM ParametersProgrammable SDRAM Parameters
SDRAM addressing configuration (SDCONF) Bank size (2 or 4) Row size (2k or 4k) Column size (256, 512 or 1k)
SDRAM timing configuration (SDPARAM) tRCA - Activate to Command with Auto Precharge tCRA - Command with Auto Precharge to Activate tRCD - Row to Column Interval tRAS - Activate to Precharge Interval tRP - Precharge to Activate Interval
Configuration done (SCDONE) Set this bit last, 200 usec min after power-up
CPU and subsystems - July 20014-75LSI Logic Confidential™
SDRAM Startup SequenceSDRAM Startup Sequence
Precharge All banks 8 Auto Refresh commands Mode Register set up 3 clock cycles after the Mode Register Command, SDRAM
accesses begin
CPU and subsystems - July 20014-76LSI Logic Confidential™
BBus DMA engineBBus DMA engine
General features Transfers to any device on the BBus Utilizes EZ4102 BBus protocols 4 DMA channels provided Fixed priority – channel 1 has highest priority Monitors a maximum of 16 requests Utilizes bus mastering
CPU and subsystems - July 20014-77LSI Logic Confidential™
BBus DMA engineBBus DMA engine
General features (cont.) Includes configurable data transfer handling
programmable word size (8-, 16-, 32-bit) programmable auto-increment or auto-decrement
DMA transfer modes retain hold on BBus until transfer is complete, or use programmable DMA on/off timers
CPU and subsystems - July 20014-78LSI Logic Confidential™
BBus DMA engineBBus DMA engine
Used to support ATA PES data transfers Between demux cyclic buffers and ATA Data register on
the E-Bus Use incrementing (16-bit) source/target address for
demux cyclic buffer Use non-incrementing source/target address for ATA Data
register
CPU and subsystems - July 20014-79LSI Logic Confidential™
BBus DMA engineBBus DMA engine
Start Code Detection Programmable 32-bit match pattern DMA engine examines data during transfers Interrupt is generated when pattern match detected Next four bytes (i.e. picture type) also provided
Can be used by software to determine picture boundaries in PES data stream
CPU and subsystems - July 20014-80LSI Logic Confidential™
BBus DMA engineBBus DMA engine
Five DMA interrupts available: Transfer complete or bus error (one for each channel) Start code detection interrupt Available in the CISTATUS, CIENABLE, CIACK registers