Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 1 ~ User Evaluation and Overview Chris Johnston Paul Lyons Donald Bailey for Real Time Image Processing on FPGAs of a Visual Language Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 2 ~ User Evaluation and Overview Chris Johnston Paul Lyons Donald Bailey for Real Time Image Processing on FPGAs of a Visual Language Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 3 ~ I MAGE P ROCESSING O N FPGA s T HE P ROBLEM A REA CLBs Block RAM DLL IO Logic textual data instructions on 1 GHz processor 15MHz - 100MHz Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 4 ~ P ROCESSING O PTIONS T HE P ROBLEM A REA Stream Processing Pipelined architectures required pixel n Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 5 ~ P ROCESSING O PTIONS T HE P ROBLEM A REA Stream Processing Pipelined architectures required pixel n+1 pixel n Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 6 ~ P ROCESSING O PTIONS T HE P ROBLEM A REA Stream Processing Pipelined architectures required pixel n+2 pixel n pixel n+1 Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 7 ~ P ROCESSING O PTIONS T HE P ROBLEM A REA Stream Processing Pipelined architectures required pixel n+3 pixel n pixel n+1 pixel n+2 pixel n+3 Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 8 ~ P ROCESSING O PTIONS T HE P ROBLEM A REA Stream Processing Random Access Processing Pipelined architectures required pixel n+4 Parallel architectures required Hybrid Processing pixel n pixel n+1 pixel n+2 pixel n+3 Pixel clock rate 15 MHz-100MHz Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 9 ~ T HE P ARALLEL P IPELINE P ROBLEM E XISTING L ANGUAGES Pipelined architectures required Parallel architectures required par{ c 1 =a 1 *b 1 c 2 =a 2 *b 2 c 3 =a 3 *b 3 } par{ c=a*b d=c+8 e=d*2.3 } Stream Processing Random Access Processing Hybrid Processing Problem: representing complex temporal relationships using conventional notations that arent up to the job par{ Q = F 1 (P); R = F 2 (Q); S = F 3 (R); T = F 4 (R); U = F 5 (R); V = F 6 (S); W = F 7 (V, T, U); } F2F2 RQ F1F1 P F6F6 V F3F3 S F4F4 T F5F5 U F7F7 W Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 10 ~ T HE P ARALLEL P IPELINE P ROBLEM E XISTING L ANGUAGES Pipelined architectures required Parallel architectures required par{ c 1 =a 1 *b 1 c 2 =a 2 *b 2 c 3 =a 3 *b 3 } par{ c=a*b d=c+8 e=d*2.3 } Stream Processing Random Access Processing Hybrid Processing Problem: representing complex temporal relationships using conventional notations that arent up to the job par{ Q = F 1 (P); R = F 2 (Q); S = F 3 (R); T = F 4 (R); U = F 5 (R); V = F 6 (S); W = F 7 (V, T, U); } F2F2 RQ F1F1 P F6F6 V F3F3 S F4F4 T F5F5 U F7F7 W Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 11 ~ A V ISUAL L ANGUAGE F OR I MAGE P ROCESSING V ERTIPH High level overview Calculations Scheduling operations Architecture View (dataflow-oriented) Computational View (complex temporal relationships) SchedulingView (FSM) Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 12 ~ A V ISUAL L ANGUAGE F OR I MAGE P ROCESSING frame 0 field retrace 1 end of frame frame 1 new field vertical blanking end of field new frame reset histogram histo write port High level overview Calculations Scheduling operations Architecture View (dataflow-oriented) Computational View (complex temporal relationships) SchedulingView (FSM) V ERTIPH colour conversion filter pixel labelling bounding box Epochs Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 13 ~ E VALUATIONS P APER- B ASED E VALUATION Cardboard mockup presented to a number of subjects (8) Subjects performed three simple design tasks Subjects filled in a questionnaire and discussed their experiences after the task Subjects were generally very positive about the system Counting rice grains (very simple) AV & SV Scheduling of the same task Barrel distortion correction: CV (gave algorithm) Wires and clock edges drawn by hand 2 FPGA & IP experts 6 novices Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 14 ~ P APER- B ASED E VALUATION E VALUATIONS Novices found the tasks difficult, and didnt see the need for pipelining All participants would draw a diagram to help explain the design Architecture View useful, intuitive, encouraged top-level design Pipeline notation useful and aided understanding But pipelining problem challenging for a number of participants JBL notation useful and helped associate functions and controls Majority said intuitive to read and use Scheduling view disconnected from the other views Several would not use Too graphical Well balanced or AV good, CV badDual text/graphical editor? ? ? 4 4 D C A- A D B A A Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 15 ~ E VALUATIONS L IVE E VALUATION Design tasks with a focus on control structures concurrent designs complex pipelines Subjective opinions about usability Correctness and style of resulting designs - does VERITPH produce a stylistic bias? Scoured the world to find suitable participants 3 with experience implementing IP algorithms on FPGAs 1 with experience implementing signal processing on FPGAs low level HDLs like VHDL; 1 with Handel-C parallel & (all but one participant) pipeline designs mixed top-down & bottom-up approaches familiar with problem domain locked in to particular approaches simple Architectural View tasks filter design without time limit (Architectural & Computational) barrel distortion (Computational with instructions) Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION ~ 16 ~ L IVE E VALUATION E VALUATIONS Multi-view design process different but useful could accept enforced top-down design preferred VERTIPH to wiring tools in VHDL Computational View mixed reviews prefer initial text editing, graphics generated from text liked separation of pipeline and parallel designs Pipeline control confusion about need to use special construct useful as a whole Control structures useful and intuitive Type editor and junction box junction box needs external and internal pins connected by default B+ C+ A D B-3 Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION This is to certify that has been awarded a grade of VERTIPH B Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION Paul L y ons 2009 CHINZ 2009 VERTIPH OVERVIEW AND EVALUATION B A CTORNESS The EU's actorness-rating vis vis the PA T HE EU This is to certify that has been awarded a grade of in