© LATTICE SEMICONDUCTOR CORPORATION 2000 Uudet mikropiirit High Density January 2008 1 Lattice...

© LATTICE SEMICONDUCTOR CORPORATION 2000

Uudet mikropiirit

High Density

January 2008 1

Lattice Confidential

High DensityispLSI Families


Uudet mikropiirit

High Density

January 2008 2


High Density

Product Line ExpansionPins

Logic Density

8K 25K14K0.7K 50K

300+

240

120

28

0

1992ispLSI 1000

1985GAL

1994ispLSI 2000/3000

ispLSI 1000E/2000V/3000E/60001996

1998ispLSI 2000E/2000VE

5000V/8000/ispGDX

400+


Uudet mikropiirit

High Density

January 2008 3


ispLSI Families

ispLSI 1000/EThe Premier High-Density Family- 125MHz/7.5ns Pin-to Pin- 2000 - 8000 PLD Gates- 44-Pin to 128-

Pin Pkgs

ispLSI 3000High-Density WithPerformance- 125MHz/7.5ns Pin-to Pin- 7000 - 20,000

PLD Gates- Boundary Scan Test- 160-Pin to 432-

Ball Pkgs

ispLSI 2000/E/V/VESuperFAST System Performance- 200MHz/3.5ns Pin-to-Pin- 5V/3.3V- 1000 - 6000 PLD Gates- Boundary Scan Test (VE)- 44-Pin to 176-Pin Pkgs

ispLSI 6000High-Density WithOn-Chip Memory- 70MHz/15ns Pin-to Pin- 25,000 PLD Gates- 4K Bit FIFO or RAM- Register/Counter Module- Boundary Scan Test- 208-Pin Pkg

ispLSI 8000/VSuperBIG CPLDs

- 100MHz/8.5ns Pin-to Pin- 5V/3.3V/2.5V- 25,000 - 50,000

PLD Gates- Boundary Scan Test- 204-Ball to 432-

Ball Pkgs

ispLSI1000/E

ispLSI2000/E &

2000V/VE

ispLSI3000

ispLSI6000

ispLSI8000/V

ispLSI3000

ispLSI 5000VSuperWIDE CPLDs

- 125MHz/7.5ns Pin-to Pin- 3.3V/2.5V- 12,000 - 24,000 PLD Gates- Boundary Scan Test- 272-Ball to 388- Ball Pkgs

ispLSI5000V

ispLSI1000/E


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High Density

January 2008 4


Original ispLSI Families (1K/E, 2K and 3K)

NOTE: The 3000 Family Utilizes a 24XVRA8 “Twin GLB” Structure

16V8 22V10 20XV10 20RA10 6002 Prog. Variable XOR Asynch Prod. Term Macrocell Product Clocks Sharing/ Term Input Distribution Registers

ispLSIGLB

18XVRA4

Key GAL Features


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High Density

January 2008 5


1032 Block Diagram Example


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High Density

January 2008 6


The 1000/E Family Generic Logic Block

Predictable Propagation Delay

Can Implement 90% of ALL 4-bit MSI Functions

Extremely Flexible and Versatile


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High Density

January 2008 7


1000/E Generic Logic Block: Multi Mode

Individual Outputs are Independently Configurable


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High Density

January 2008 8


1000/E Output Routing Pool

– Connects GLB Outputs to I/O Cells

– Greater Flexibility in Pin Assignment

– Improved Routibility

– Predictable Delay


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High Density

January 2008 9


1000/E Output Routing Pool Bypass

High-Speed Path

Faster Tpd & Tco


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High Density

January 2008 10


1000/E Family Clock Network

Three Global Clocks To GLBs

Two Global Clocks To I/O Cells

ispLSI 1016 has 3 Global Clocks


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High Density

January 2008 11


1000/E Simplified I/O Cell Diagram


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High Density

January 2008 12


1000/E I/O Cell Configurations

– Input, Output and Bi-directional Cells


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High Density

January 2008 13


ispLSI 1000 Family

ispLSI

1016 ispLSI

1024 ispLSI

1032 ispLSI

1048/

1048C

Density(PLD Gates)

Speed:Fmax (MHz)

Speed:Tpd (ns)

Macrocells

Registers

Inputs & I/Os

Pins/Package

2000

111

10

64

96

36

44-PLCC44-TQFP44-JLCC

4000

91

12

96

144

54

68-PLCC100-TQFP68-JLCC

6000

91

12

128

192

72

84-PLCC100-TQFP84-CPGA

8000

80

15

192

288

106/110

120-PQFP128-PQFP133-CPGA


Uudet mikropiirit

High Density

January 2008 14


• 2nd Generation ispLSI 1000 Product Family

• Identical Pin-Out to ispLSI 1000 Family– Except for Addition of Global Output Enable Pins

• Provides Much Higher System Performance– ispLSI 1016 Tpd=10ns, Fmax=110 MHz

– ispLSI 1016E Tpd=7.5ns, Fmax=125 MHz

• Improved I/O Register Speed for Faster Processor Bus Applications

• Additional Global OE Pins for Better Tri-State Control and Higher Performance

• Enhanced GRP Architecture– More Predictable Delay

– Higher Routability

– Better Utilization

• Add Programmable Output Slew Rate Control to Reduce Ground Bounce and Switch Noise

ispLSI 1000E Family

Enhancements

Provides Improvement Over ispLSI 1000 Family!


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High Density

January 2008 15


ispLSI 1000E Family

• Lattice’s 2nd Generation 1000 Family

• High System Performance

• Higher Routability

• Higher Utilization

ispLSI

1016E

Density(PLD Gates)

Speed:Fmax (MHz)

Speed:Tpd (ns)

Macrocells

Registers

Inputs & I/Os

Pins/Package

Availability

2000

125

7.5

64

96

36

44-PLCC44-TQFP

NOW

ispLSI

1048E

8000

91

10

192

288

110

128-PQFP128-TQFP

NOW

ispLSI

1032E

6000

90/125

10/7.5

128

192

72

84-PLCC100-TQFP

NOW


Uudet mikropiirit

High Density

January 2008 16


1032 vs. 1032E Comparison

• 1032 and 1032E Identical Except for:– 1032E Adds 2 Global Output Enables

– 1032E Has Enhanced Routing Resources

• Provides a Performance Migration Path for the 1032

Pinout Difference


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High Density

January 2008 17


ispLSI 2000 Family


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High Density

January 2008 18


ispLSI 2000 Family

• Supports Most Popular Density and I/O Range– 32 to 128 Macrocells

– 32 to 128 I/O

– 44 to 176 Pin Packages

• Alternative Solution In Terms of Density and I/O Ratio

• Twice As Much I/O for a Given Density as Compared to ispLSI 1000/E Family

Product Strategy

• ispLSI 2000 Family Targeted for– Highest Performance

– Lowest Cost


Uudet mikropiirit

High Density

January 2008 19


ispLSI 2000 Family Architecture

ispLSI 2064 Block Diagram

Consistent and Predictable GRP

GLB With Optimum Input-to-Output Ratio

Global Output Enables

Fast or Slow Slew Rate

Megablock OutputEnables

Flexible Clocking Schemes


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High Density

January 2008 20


ispLSI 2000 Family GLB

JK-,T- and D-type flip flops20 product terms for all four outputs

Multiple clocks for synchronous and asynchronous applications18XVRA4

Product Term Sharing XOR for combinatorial and registered functions


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High Density

January 2008 21


ispLSI 2000 Family ORP

• 1:1 ratio of GLB outputs to I/O Cells

• Increased routability over the 1000 Family


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High Density

January 2008 22


ispLSI 2000 Family I/O Cell


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High Density

January 2008 23


ispLSI 2000 Family Summary

Architecture Enhancements

Architecture Optimized for Performance and Cost

• Enhanced GRP Architecture– More Predictable GRP Delay

– Higher Routability

– Better Utilization

• Additional Global OEs– Enhanced Tri-State Control

– Provide Higher OE Performance

• Eliminates I/O Register– Faster Tpd

• Eliminates Clock Polarity Option– Faster Tco

• Provides Output Slew Rate Control– Reduce Ground Bounce

and Switching Noise

• Emphasizes TQFP Packaging for ISP Capability


Uudet mikropiirit

High Density

January 2008 24


ispLSI 2000 Family

• Double The I/Os Of 1000 Family

• Fastest High-Density PLD Family

• New TQFP Options Enhance ISP Capability

ispLSI

2032 ispLSI

2064 ispLSI

2096 ispLSI

2128

Density(PLD Gates)

Speed:Fmax (MHz)

Speed:Tpd (ns)

Macrocells

Registers

Inputs & I/Os

Pins/Package

1000

180

5.0

32

32

35

44-PLCC44-TQFP48-TQFP

2000

125

7.5

64

64

70

84-PLCC100-TQFP

4000

125

7.5

96

96

104

128-PQFP128-TQFP

6000

100

10

128

128

138

160-MQFP176-TQFP


Uudet mikropiirit

High Density

January 2008 25


ispLSI 2000 Family

Density vs I/O

Macrocells

0

32

64

96

128

0 32 64 96 128 160 192 224 256

I/Os

2032

2064

2096

2128

1016/E

1024

1032/E

1048C/E

2000 Family Provides Twice the I/OCompared to 1000/E Family


Uudet mikropiirit

High Density

January 2008 26


ispLSI 2000E Family


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High Density

January 2008 27


ispLSI 2000V Family


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High Density

January 2008 28


ispLSI 2000V Family

• Lattice First 3.3V High-Density Family

• 2000V Family Will Support JTAG Programming Scheme

• Targeted to be Fastest 3.3V CPLD in the Market

• Strengthens Lattice ISP Position

ispLSI 2000V is the First 3.3V ISP CPLD Family in the Market!

Product Strategy

Total ISPTotal ISP


Uudet mikropiirit

High Density

January 2008 29


ispLSI 2000V Family

• Industry’s First 3.3V ISP CPLD Family

• 2000V Family Supports Open-Drain Outputs

• Density Migration Path

• Support Mixed 3.3V/5V Systems

• JTAG Programming

ispLSI

2032LV/

2032V ispLSI

2064V ispLSI

2096V ispLSI

2128V

Density(PLD Gates)

Speed:Fmax (MHz)

Speed:Tpd (ns)

Macrocells

Registers

Inputs & I/Os

Pins/Package

1000

100

7.5

32

32

35

44-PLCC44-TQFP

2000

100

7.5

64

64

70/37

44-PLCC44-TQFP

100-TQFP84-PLCC

4000

80

10

96

96

104

128-PQFP128-TQFP

6000

80

10

128

128

138/74

176-TQFP160-PQFP100-TQFP84-PLCC


Uudet mikropiirit

High Density

January 2008 30


ispLSI 3000 Family


Uudet mikropiirit

High Density

January 2008 31


ispLSI 3000 Family

• High Density / High Functionality / High Speed

• Provides Higher Density and Higher Pin-Count Devices– 160 to 448 Macrocells

– 130 to 258 I/O Counts

– 160 to 304 Packages

• Increased Functionality for Higher System Integration

• Achieve Highest Performance– 3192: 10ns (Tpd), 100MHz (Fmax)

• Predictable Delay

• Boundary Scan Testability Supported

Product Strategy

Emphasizes Lattice ISP Technology!


Uudet mikropiirit

High Density

January 2008 32


ispLSI 3000 Family Architecture

3256 Functional Block Diagram

128 I/Os, 256 Macrocells

384 Registers

Global External andInternal Clocks

GRP and ORP for MaximumRouting and Utilization

In-System Programmable


Uudet mikropiirit

High Density

January 2008 33


ispLSI 3000 Family

• Highest Density Device

• Boundary Scan Testability

• Twin GLB Architecture

• More Global Clocks

• Enhanced GRP Routing Resources

• No Fanout Variation In The GRP

• Global Output Enables

• Programmable Slew Rate

Architecture Enhancements


Uudet mikropiirit

High Density

January 2008 34


ispLSI 3000 Family ORP

• 2:1 ratio of GLB outputs to I/O Cells


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High Density

January 2008 35


ispLSI 3000 Family I/O Cell

I/O Cell Functionality the Same as the 1000 Family

Test OE to All I/O Cells

Global OEs to All I/O Cells


Uudet mikropiirit

High Density

January 2008 36


ispLSI 3000 Family

Density(PLD Gates)

Speed:Fmax (MHz)

Speed:Tpd (ns)

Macrocells

Registers

Inputs & I/Os

Boundary Scan Test

Pins/Package

Availability

ispLSI

3256A

11000

90

12

256

384

130

Yes

160-MQFP160-PQFP*

NOW

7000

125

7.5

160

320

162

Yes

208-MQFP272-BGA*

NOW

ispLSI

3256E

12000

100

10

256

512

258

Yes

304-MQFP320-BGA

NOW

14000

100

10

320

480

162

Yes

208-MQFP208-PQFP320-BGA*

NOW

ispLSI

3320

9000

100

10

192

384

194

Yes

240-MQFP272-BGA

NOW

ispLSI

3192ispLSI

3160ispLSI

3160

20000

90

12

448

672

226

Yes

432-BGA

2Q98

ispLSI

3448

* Contact Factory for Availability


Uudet mikropiirit

High Density

January 2008 46


Introduction to VantisProgrammable Logic Devices

MACH 1 and MACH 2 CPLD FamiliesMACH 5 FamilyMACH 4 Family

JTAG ISP


Uudet mikropiirit

High Density

January 2008 47


Agenda

• Vantis value propositions

• Vantis MACH 1 CPLD Family

• Vantis MACH 2 CPLD Family

• Vantis MACH 5 CPLD Family architecture

• Vantis MACH 4 CPLD Family architecture

• Compare and Contrast

• JTAG ISP


Uudet mikropiirit

High Density

January 2008 48


Vantis Value Propositions

• SpeedLocked performance

• Ease-of-Use

• Multiple Density - I/O combinations

• Reliability

• Advanced system integration features


Uudet mikropiirit

High Density

January 2008 49


Mach 1 and 2


Uudet mikropiirit

High Density

January 2008 50


MACH 1 & MACH 2 Architectures

Principal performance features of the MACH 1 & MACH 2 Architectures are:

• Central switch matrix

• Product-Term (PT) arrays -- programmable “AND” planes

• Logic Allocators -- fixed “OR” planes

• Multimode macrocells

• PAL Block OE (Output Enable) Product-Terms


Uudet mikropiirit

High Density

January 2008 51


MACH 1 & MACH 2 Features and Characteristics

• Original MACH Architectures

• Highly Routable

• Power Management Feature– Per Macrocell and Per Block power-down

• Guaranteed SpeedLocked Timing– up to 12 PT for M1

– up to 16 PT for M2

• Multiple Density and I/O Combinations

• Commercial and Industrial Devices Available

• Up to sixteen Product-Term functions are accommodated


Uudet mikropiirit

High Density

January 2008 52


MACH 1 & MACH 2

• Speed Performance– Commercial as fast as tPD = 5 ns (FCNT = 182 MHz)

– Industrial as fast as tPD = 7.5 ns

• Mid-Range Densities– 32 to 128 macrocells

– 32 to 64 I/Os

– 4 to 16 output enable controls

Performance: Speeds and Densities


Uudet mikropiirit

High Density

January 2008 53


MACH 1 & MACH 2

• Devices are In-System Programmable (‘SP’ devices only)

• Devices are JTAG (IEEE 1149.1) compatible (‘SP’ devices only)– Do not have a boundary-scan register so test is not possible

• PCI-compliant (Speed Grades 7 ns, 10 ns and 12 ns

• Device I/Os are “Bus-Friendly”

• Devices have a programmable security bit

• Devices follow a pre-set power-up procedure

• Power Management Feature -- Full or Half-Power

Performance: System Capabilities


Uudet mikropiirit

High Density

January 2008 54


Performance: Technology & Support

MACH 1 & MACH2

• Leading-edge process technology– The EE6.5 process

– L(EFF) = 0.5 micron

• Supported by DesignDirect and IDE software

• Low-cost entry-level tool

• Windows GUI interface


Uudet mikropiirit

High Density

January 2008 55


MACH 1 & MACH 2 CPLD Families

100

84

68

44

32 48 64 96

Macrocells

Pins

MACH111(SP)-5(5)

MACH215-12

MACH120-12

MACH131-7

MACH211(SP)-7(7)

MACHLV210A-10

MACH131SP-5

MACH221-7

208

MACH231SP-10

MACH231-6

144

128 256


Uudet mikropiirit

High Density

January 2008 56


MACH 1 Block Diagram

Clock/Input Pins

Dedicated Inputs

Switch Matrix

26

Logic

Allocator

(FixedOR

Plane)

16

Output

MCs

Output Macrocell Feedback

I/O Pin Feedback

I/O Cells

I/O Pins

PAL Block

P-T

Array

(Prog.AND

Plane)

16 16 16


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High Density

January 2008 57


MACH 1 P-T Array & Logic Allocator

4

4

4

FromSwitchMatrix

To Macrocell

(Max. 12 P-Ts)

Product-TermArray

ProgrammableAND- Plane Fixed OR- Plane


Uudet mikropiirit

High Density

January 2008 58


MACH 1 Macrocell

D Q

PAL-BlockAsynchronous

Preset

From LogicAllocator

CLK0

To Switch Matrix

AR

AP1

0 To I/O Cell(4-12 P-Ts)

CLKn


Preset

1

0


Uudet mikropiirit

High Density

January 2008 59


MACH 2 Block Diagram

Clock/Input Pins

Switch Matrix

22/26

8 Output

MCs

Output Macrocell Feedback

I/O Pin Feedback

I/O Cells

I/O Pins

PAL Block

8

Buried

MCs

Buried Macrocell Feedback

P-T

Array

(Prog.AND

Plane)

Logic

Allocator

(FixedOR

Plane)


Uudet mikropiirit

High Density

January 2008 60


MACH 2 P-T Array & Logic Allocator

4

Product-TermArray

FromSwitchMatrix

To Macrocell

(Max. 16 P-Ts)

4

ProgrammableAND-Plane

Fixed OR-Plane


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High Density

January 2008 61


MACH 2 Output Macrocell


Preset

From Logic Allocator

Block CLK0..CLKn

To Switch Matrix

To I/O Cell


Reset

4~16 P-Ts1

0

1

0 AP

D/T/L Q

AR


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High Density

January 2008 62


MACH 2 Buried Macrocell

AP

D/T/L Q

AR


Preset


To Switch Matrix

From I/O Cell

10


Reset

4~16 P-Ts

1

0

Block CLK0..CLKn


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High Density

January 2008 63


MACH 1 & MACH 2 Comparison

MACH 1 MACH 2

Focus I/ O Density

Max P-T/ MCell 12 16

PT Clocks No MACH 215

Macrocells 1 per I/ O 2 per I/ O

StorageElements

Register RegisterLatched

Inputs Direct DirectRegisteredLatched

Inputs perPAL Block

26 26/ 32


Uudet mikropiirit

High Density

January 2008 64


MACH 1 & MACH 2 Summary

• Fastest

• PFQP, TQFP and PLCC packages

• Pin-for pin compatibility– Between MACH1xx and MACH2xx devices

– MACH111 and MACH 211; MACH131 and MACH231, etc.

• In-System Programmable (ISP) (‘SP’ devices only)

• Commercial and Industrial versions available

• Guaranteed propagation delays -- SpeedLocking

• Universal Software Support

• Full availability

• Cost effective logic solution


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High Density

January 2008 65


Mach 5


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High Density

January 2008 66


MACH 5(A) CPLD Family Overview

• MACH 5(A) Family Performance Characteristics

• MACH 5(A) Architecture– MACH 5(A) Internal “Components” and Subsystems

• MACH 5(A) Timing and Delay


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High Density

January 2008 67


MACH 5(A) Performance Characteristics

• Fifth Generation MACH Architecture

• Hierarchical signal routability

• Both 5 V and 3.3 V versions

• Up to 32 Product-Terms per macrocell, with true XOR capability


Uudet mikropiirit

High Density

January 2008 68


MACH 5(A) Performance Characteristics (cont’d)

• Power Management Feature– Four PAL block-based power versus speed options

• Synchronous and Asynchronous clocking– Single- & Dual-edge clocking

• Fixed, predictable delays


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High Density

January 2008 69


Performance: Speed and Densities

• High Densities– 128 to 512 macrocells

– 16 to 64 output enable controls

• Speed Performance– Commercial tPD = 5.5 ns (fCNT = 182 MHz)

– Industrial tPD = 7.5 ns

• Nine packages offered– Accommodate from 68 to 256 signal I/Os

• Multiple package/density options


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• 5V and 3.3V JEDEC-compliant

• In-System programmable

• JTAG (IEEE 1149.1) compliant

• PCI-compliant (Speed Grades -5, -7, -10 and -12)

• M5A devices can be hot-socketed


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High Density

January 2008 71


Performance: System Capabilities (cont’d)

• Mixed supply voltage system-safe

• I/Os are “Bus-Friendly”– M5A I/Os have programmable pull-up option

• Individual device I/Os are slew-rate controllable

• Devices have a programmable security bit

• Power Management capability– Block-by-block basis

– Four levels of power reduction


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High Density

January 2008 72


Performance: Technology and Support

• Leading-edge process technologies:

– EE8 process -- 0.25 micron (Leff), 3.3V

» All M5A devices

– EE7 process -- 0.35 micron (Leff), 3.3V

» M5-320, M5-384, M5-512

» All M5LV (3.3v) devices

– The EE6.5 process -- 0.5 micron (Leff)

» M5-128, M5-192 and M5-256


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January 2008 73



• Supported by DesignDirect software

– Low-cost entry-level tool with DesignDirect

» Windows GUI interface

» OEM Package with synthesis and simulation

• Supported by Vantis MACHXL software

– Design entry ports to universal tools

• Supported by ispDesignExpert software


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High Density

January 2008 74


Performance: MACH 5(A) Advancements

• Greater density range

• More I/O and Density points

• More packages

• Higher speed

• More clocking options

• Lower power dissipation

• Lower cost


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High Density

January 2008 75


MACH 5(A) Architecture

• MACH 5(A) Principal Performance Features:

• Three levels of interconnect

• Product-Term arrays

• Logic Allocators

• Multimode Macrocells

• Control (Clock, Set and Reset) Generators

• OE (Output Enable) Generators


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High Density

January 2008 76


Non-HierarchicalOne Large switch matrix

(pre-MACH5)

HierarchicalDistributed switch matrices

(MACH 5(A))

One Large Switch Matrix

Segment Level Interconnect

Block Level Interconnect

MACH 5(A) Architecture

• MACH 5(A) has three levels of interconnect – Within a PAL block (Local level)

– Within a Group of Four PAL blocks (Block Level)

– Between Segments (Segment Level)


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High Density

January 2008 77


Block:(16 MCs)

4

4

JTAGPort

Segment Interconnect

Pin (Global) Clocks

BlockInterconnect

DeviceI/Os

Segment:(4 Blocks,64 MCs)

MACH 5(A) Architecture: Blocks & Segments


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High Density

January 2008 78


Segments PAL Blocks Macrocells Device*2 8 128 M5(A)-128/n3 12 192 M5(A)-192/n4 16 256 M5(A)-256/n5 20 320 M5(A)-320/n6 24 384 M5(A)-384/n8 32 512 M5(A)-512/n

*n denotes the number of package signal I/Os

MACH 5(A) Architecture: Device Composition


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High Density

January 2008 79


MACH 5(A) Architecture: PAL Block Components

MACH 5(A) PAL Blocks are self-sufficient with their own:

• Product-Term (Logic) Array

• Logic Allocator

• Sixteen Macrocells

• Control Generator– Clock generator (Four clocks)

– Set/Reset Generator (Three set/reset lines)

• Output Enable (OE) Generator (Two per Block)

• I/O Pin Connections -- function of the higher level


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January 2008 80


2

*Control Generator provides: 4 configurable clocks and 3 configurable set/reset lines.

Product-Termarray

(16X4 for Macrocells+4 for clock/clock enable+3 for set/reset+2 for output enable)

16

32

32

32

OE Generator2

Input register paths

BlockFeeder

Inter-connectFeeder

Macro

cells

I/O

s

Log

ic A

llocato

r

Control Generator *

MACH 5(A) Architecture: PAL Block Layout

Blo

ck

Inte

rco

nn

ect


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High Density

January 2008 81


LogicAllocator

Maximum of5 - 8 Clustersper Macrocell* To Macrocell

*Maximum allowed depends on Macrocell number.Each cluster can be directed to only one Macrocell.

A “Cluster” is a sum-of-products function with either 3 or 4 product terms

MACH 5(A) Architecture: Product-Term Array


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January 2008 82



ModeSelectio

n

Blo

ck C

lock

(0

-3)

Blo

ck S

et/

Rese

t (0

-2)

To I/O Pin

Combinatorial orRegistered Output

D Q

“Fast”Path

O/PBfr&

MUX

MACH 5(A) Architecture: The Macrocell


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High Density

January 2008 83


MACH 5(A) Architecture: Macrocell Modes

• Combinatorial

• D-Type flip-flop

• Latch

• T-Type flip-flop (synthesized)

• J-K flip-flop (synthesized)

• S-R flip-flop (synthesized)


Uudet mikropiirit

High Density

January 2008 84


Blo

ck C

lock

(0

-3)

Blo

ck S

et/

Rese

t (0

-2)

ModeSelectio

n

To PAL BlockI/O Pad 0 (MC 0)

orI/O Pad 15 (MC15)

(Optional)

D Q

O/PBfr&

MUX

From PAL BlockI/O Pad 3 (MC 0)

orI/O Pad 12 (MC 15)

To Array Logic(Optional)

MC0 or

MC15

MACH 5(A) Architecture: Input Registers

• Macrocells 0 and 15 of each MACH 5(A) PAL block can be used as input registers

• The respective macrocells must be accessed via PAL block I/O pads 3 and 12

• The output ports of the input registers can be directed either to the matrix as a logic input to the device or to the I/O pads of the PAL block


Uudet mikropiirit

High Density

January 2008 85


Set/Reset GeneratorClock Generator

MACH 5(A) Architecture: Control Generator

• Inputs:– Four Synchronous Global Pin Clocks

– Four Product-Terms

– Three of the Four can be chosen

• Outputs:– Four Conditioned Block Clock lines

• Inputs:– Three Product-Terms

• Outputs:– Three Conditioned Block Set/Reset lines

• The Control Generator Consists of the:

– Clock Generator

– Set/Reset Generator


Uudet mikropiirit

High Density

January 2008 86


CLK0

PT1

CLKINCE

PINCLK(0:3)

PT2

PT0

PT3

CLK

Product-TermsPT(0:3)

BlockClock

Lines 0-3

CLK1

CLK2

CLK3

2TO1MUX

2TO1MUX

CE

CE

+ EDGE- EDGE

CLKINCE

2TO1MUX

PINCLK0123

PINCLK0123

PINCLK0123

4TO1MUX

4TO1MUX

4TO1MUX

MACH 5(A) Architecture: Clock Generator


Uudet mikropiirit

High Density

January 2008 87


Product-TermsPT(0:2)

SET/RST1

SET/RST0PT0

PT1

PT2SET/RST22TO1

MUX

2TO1MUX

BlockSet/ResetLines 0-2

MACH 5(A) Architecture: Set/Reset Generator


Uudet mikropiirit

High Density

January 2008 88


Output EnableGenerator

Vcc

FromMacrocell

To / From Device Pin

Input (if Output Bufferis High Impedance)

One MUXper I/O

MACH 5(A) Architecture: OE Generator

• The Output Buffer can be:– Permanently enabled -- Vcc connected

– Permanently disabled -- Ground connected

– Selectively enabled -- driven by OE Generator


Uudet mikropiirit

High Density

January 2008 89


2

Block Feeder

• 32 Inputs per PAL block

• Each Input is an 8:1 MUX– Seven Inputs from

– Block Interconnect

– One Input from

– Local Feedback

Interconnect Feeder

• 3:1 DEMUX for every signal fed to the Block Interconnect

Product-Termarray

(16X4 for Macrocells+4 for clock/clock enable+3 for set/reset+2 for output enable)

16

32

32

32

OE Generator2

BlockFeeder

Inter-connectFeeder

Mac

roce

lls

I/O

s

Lo

gic

All

oca

tor

Control Generator

MACH 5(A) Architecture: Interconnect

Blo

ck

Inte

rco

nn

ect


Uudet mikropiirit

High Density

January 2008 90


MACH 5(A) Segment Interconnect Lines

• Block interconnect lines connect to the segment interconnect lines through a 3 to 1 demultiplexor

• The difference between any two MACH 5(A) densities: – The number of segments

– The number of Segment Interconnect Lines:

» M5(A)-128 has 128 lines







Uudet mikropiirit

High Density

January 2008 91


MACH 5(A) Timing Model: Introduction

• The MACH 5(A) Timing Model is used to estimate delay that a signal incurs as it passes through the device

• Different input types are subject to different delay factors owing to the different routing and treatments afforded them

• Different input types shown in the timing model are:– Regular inputs and inputs fed back from intern macrocell outputs

– Pin (“global”) clock inputs

– PT clocks and enables for flip-flops and latches

– Inputs directly connected to input registers.


Uudet mikropiirit

High Density

January 2008 92


OUT IN

(INTERNAL FEEDBACK)

(EXTERNAL FEEDBACK)

TPT

TEA

TER

COMB/ DFF/ LATCH/ TFF*/ SR*/ JK*

* SIMULATEDTS(S/A)

TH(S/A)

TSAL

THIAL

TSRR

TCES

TCEH SR

Q

PIN (“GLOBAL”) CLK

CE

TPD i

TCO(S/A)i

TPDLi

TGOAL

TSRi

SR

INPUT REG/INPUT LATCH

CE

TSIR(S/A)

THIR(S/A)

TSIL

THIL

TSRR

TCES

TCEH

TCO(S/A)i

TPDILi

TGOAL

TSRi

Q

TPL1

TPL2

TPL3

TBLK

TSEG

TSLW

TBUF

MACH 5(A) Timing Model


Uudet mikropiirit

High Density

January 2008 93


MACH 5(A) Timing Model: Parameters

• Questions related to the application of the MACH 5(A) Timing Model delay parameters might be as follows for a “regular” input:

– Does the path cross into a second PAL block within the same segment?

» If so, add the tBLK delay constant

– Does the path cross into a PAL block of a different segment?

» If so, add the tSEG delay constant

– Does path involve PAL blocks programmed for reduced power?

» If so, apply the appropriate tPLx delay constant(s)

• If none, some or all of the above apply, consider the appropriate constants and proceed on the path to the “Logic” delay constants


Uudet mikropiirit

High Density

January 2008 94


MACH 5(A) Timing Model: “Adder” Parameters

• Product-Term Adder– tPT: Delay of 0.3 ns delay per PT cluster beyond first

• Power Management Adders (Technology dependent)– tPL1: EE6.5: 5.0 ns; EE7: 4 ns; EE8: 4 ns

– tPL2: EE6.5: 9.0 ns; EE7: 6 ns; EE8: 6 ns

– tPL3: EE6.5: 17.5 ns; EE7: 9 ns; EE8: 9 ns

• Interconnect Adders (Device Speed Grade dependent)– tBLK: “-5”: 1.5 ns; “-7”: 1.5 ns; Others: 2.0 ns

– tSEG: “-5”: 4.5 ns; “-7”: 5.0 ns; Others: 6.0 ns


Uudet mikropiirit

High Density

January 2008 95


MACH 5(A) Timing Model: Internal Delay

tPDi: Internal combinatorial propagation delay

• When a signal path utilizes product-terms of more than one PAL Block:

– tPDi must be considered for each such PAL Block

• When a signal path utilizes product-terms of a given PAL Block and is fed back to the same PAL Block to utilize further product-terms:

– tPDi must be considered for each pass through that PAL Block


Uudet mikropiirit

High Density

January 2008 96


MACH 5(A) I/O and Density Options

• A designer has many macrocell and package options

• MACH 5(A) has a number of macrocell (MC) density and I/O combinations

• Designing with MACH 5(A) allows designer to consider:» Six different macrocell densities

» Eight (M5) and six (M5A) different I/O options

• Designer can select packages having:» A given number of I/Os with different MC densities

» A given MC density but different numbers of I/Os

» Beware of “Bond-out” issues with device/package migrations!!


Uudet mikropiirit

High Density

January 2008 97


(Signal)

I/Os

Package Type BGA PQFP TQFP

Package Type BGA PQFP TQFP

Hot-socketing Pull-up/bus-friendly 3.3 or 5V operation

M5A-128

M5A-128

M5A-128

M5A-384

M5A-192

M5A-192

M5A-192

M5A-256

M5A-256

M5A-256

M5A-256

M5A-320

M5A-320

M5A-320

M5A-384

M5A-384 M5A-512

M5A-512

M5A-512

M5A-512

tPD = 5.5 ns tPD = 6.5 ns

128 192 256 320 384 512 Macrocells

256

192

160

120

104

74

BGA 352 BGA

256

PQFP 208

PQFP 160

TQFP 144

TQFP 100

Pkg Pins

High DensityHigh IO

MACH 5A: Package / Density Options


Uudet mikropiirit

High Density

January 2008 98


Mach 4


Uudet mikropiirit

High Density

January 2008 99


MACH 4(A) CPLD Family Overview

• Training Module covers:

• MACH 4(A) Family performance features and characteristics

• MACH 4(A) Architecture– MACH 4(A) internal “components” and subsystems

• MACH 4(A) SpeedLockingTM


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• Ease of Use -- Pin locking -- SpeedLockingTM

-- Flexible control

-- First-Time-FitTM

-- Fast-Refit-TimeTM

-- High Speed


• Fourth Generation EE CMOSMACH Architecture

• Multiple switch matrices– high routability

– pin locking

• 5 V and 3.3 V versions

• Up to 20 Product-terms per macrocell, with true XOR capability


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• Dedicated input registers/latches

• Power management feature– PAL block-based programmable power-down mode

• Flexible clocking– Four global clocks with selectable edges

– Synchronous or Asynchronous mode for each macrocell


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High Density

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Performance: Speed and Densities

• MACH 4

• Densities– 32 to 256 macrocells

– 32 to 384 registers

– 1250 to 10,000 PLD Gates

– 32 to 128 I/Os

• Speed– commercial 7.5 ns tPD

– 154 MHz fMAX & 111 MHz fCNT

• MACH 4A

• Densities– 32 to 512 macrocells

– 32 to 768 registers

– 1250 to 20,000 PLD gates

– 32 to 256 I/Os

• Speed– commercial 5.0 ns and 6.5 ns

tPD

– 250 MHz fMAX & 182 MHz fCNT


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High Density

January 2008 103


Performance: System Capabilities – I/O

• JTAG (IEEE 1149.1) compliant– In-System programmable

– boundary scan testing

• PCI-compliant (Speed Grades – -50/-55/-60/-65/-7/-10/-12)

• 5 V and 3.3 V JEDEC-compliant– Mixed supply voltage system-safe


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January 2008 104



• Device I/Os & Inputs– MACH 4 devices: Bus-friendly

– MACH 4A devices: Programmable Bus-friendly or Pull-up controlled by one global bit

– Individual I/O slew-rate control

• Programmable security bit prevents:– Fuse map read-back

– Accidental programming

• Hot-socketing– In MACH 4A devices


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January 2008 105



• Leading-edge process technology– EE8 process: 0.25 mm (Leff), 3.3V

– EE7 process: 0.35 mm (Leff), 3.3V

• Supported by ispDesignExpert, DesignDirect-CPLD, Vantis MACHXL & MACH-Synario

• Programming Support– In-System-Programming using VantisPRO

– Industry standard programmers

– ATE

– Embedded programming


Uudet mikropiirit

High Density

January 2008 106


MACH 4(A) Architecture Overview

• Architecture types– Based on macrocell to I/O ratio

– 1:1 Architecture and 2:1 Architecture

• Multiple switch matrices– Input, Central and Output

• PAL blocks– Product-Term arrays

– Logic allocators

– Multimode macrocells

– I/O cells

– Control and OE generators


Uudet mikropiirit

High Density

January 2008 107


CSM

ISM

33/34/36

PAL OSM

8\16

M4(A) Multiple Switch Matrix Architecture


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Clock/Input Pins

Dedicated Inputs

33/34/36

Internal Feedback

External Feedback

PAL Block (33/34/36V16)

I/O Pins

Cen

tral S

wit

ch

Matr

ix

Log

ic A

llocato

r

Ou

tpu

t S

wit

ch

Matr

ix

8 I

/O C

ells

Input Switch Matrix

16MCs

Log

ic A

rray

16

16

16 8

...

PAL Block

I/O Pins

ClockGenerator

MACH 4(A) (2:1 Arch.) Block Diagram


Uudet mikropiirit

High Density

January 2008 109


Device

M4A(3,5)-32/32 M4(LV)-32/32

M4A(3,5)-64/32 M4(LV)-64/32

M4A(3,5)-96/48 M4(LV)-96/48

M4A(3,5)-128/64 M4(LV)-128/64

M4A(3,5)-192/96 M4(LV)-192/96

M4A(3,5)-256/128 M4(LV)-256/128

M4A3-384

M4A3-512

Number of Inputs to PAL Block

33

33

33

33

34

34

36

36

MACH 4(A) PAL Block Inputs


Uudet mikropiirit

High Density

January 2008 110


MUX

MUX

MUX

From Macrocell 1

From Macrocell 2

From I/O Direct

Registered/latched

To C

en

tral S

wit

ch

Matr

ix

MACH 4(A) (2:1 Arch.) Input Switch Matrix

• Total eight 4:3 muxes per PAL block

• Every 2 macrocells share one 4:3 mux


Uudet mikropiirit

High Density

January 2008 111


Number of Inputs 33/34/36 33

Number of PTs 90 98

For logic use 80 80

For OE use 8 16

For global PALinitialization

2 2

2:1 arch. 1:1 arch.

MACH 4(A) (2:1 Arch.) Product-Term Logic Array

Notes:

• M4(A)-192/96 & M4(A)-256/128 have 34 inputs per PAL block

• M4A3-384 & M4A3-512 have 36 inputs per PAL block


Uudet mikropiirit

High Density

January 2008 112


MACH 4(A) (2:1 Arch.) Synchronous Logic Allocator

Ton+1

From

n+1

From

n+2

Ton-2

Ton-1

From

n-1

Product Term Cluster

Logic Allocator

To m

acro

cell n

nn

– PT cluster steered to 1 of 4 macrocells

– Up to 20 PTs per function

– XOR capability


Uudet mikropiirit

High Density

January 2008 113


Ton+1

From

n+1

From

n+2

Ton-2

Ton-1

From

n-1

Product Term Cluster

Logic Allocator

To m

acro

cell n

nn

MACH 4(A) (2:1 Arch.) Asynchronous Logic Allocator

Where are the other two product terms?– one for the asynchronous, product-term clocking

– one for the asynchronous set and reset


Uudet mikropiirit

High Density

January 2008 114


MACH 4(A) (2:1 Arch.) Synchronous Macrocell

Swap

AP AR

D/T/L Q

1

0

Power-UpReset

PAL-BlockInitialization

Product Terms


Block CLK0Block CLK1Block CLK2Block CLK3

To Input Switch Matrix

To OutputSwitchMatrix


Uudet mikropiirit

High Density

January 2008 115

Lattice ConfidentialTo InputSwitch Matrix

Swap

AP AR

D/T/L Q

1

0

Power-UpReset

IndividualInitialization

Product Term


Block CLK0Block CLK1

Individual ClockProduct Term

To OutputSwitchMatrix

MACH 4(A) (2:1 Arch.) Asynchronous Macrocell


Uudet mikropiirit

High Density

January 2008 116


MACH 4(A) (2:1 Arch.) Output Switch Matrix

I/OCell

I/OCell

I/OCell

I/OCell

macro-

cell

Macrocell drives one of 4 I/Os

I/O can choose one of 8 macrocells

MUX I/OCell

macro-cell

macro-

cellmacro

-cell

macro-

cellmacro

-cell

macro-

cell

macro-

cell

macro-

cell


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High Density

January 2008 117


Input register: Programmable Zero-Hold-Time Fuse

To InputSwitch Matrix

Q D/L

Block CLK0Block CLK1Block CLK2Block CLK3

From OutputSwitch Matrix

Individual OEProduct Term

Power-Up Reset


MACH 4(A) (2:1 Arch.) I/O Cell


Uudet mikropiirit

High Density

January 2008 118


GCLK2

GCLK3

Block CLK0(GCLK0 or/GCLK1)




GCLK0

GCLK1

MACH 4(A) (2:1 Arch.) Clock Generator

– 4 Clock Signals common to all Macrocells within a PAL Block

– Only 2 global clock signals in M4(A)-32/32 & M4(A)-64/32: GCLK0 connects to GCLK2; GCLK1 connects to GCLK3


Uudet mikropiirit

High Density

January 2008 119


Clock/Input Pins

Dedicated Inputs

33

Internal Feedback

External Feedback

PAL Block(33V16)

I/O Pins

Cen

tral S

wit

ch

Matr

ix

Log

ic A

llocato

r

Ou

tpu

t S

wit

ch

Matr

ix

16 I

/O C

ells

Input Switch Matrix

16Output

MCsLog

ic A

rray

16

16

16 16

...

PAL Block

I/O Pins

ClockGenerator

MACH 4(A) (1:1 Arch.) Block Diagram


Uudet mikropiirit

High Density

January 2008 120


MACH 4(A) (1:1 Arch.) Input Switch Matrix

MUX

MUX

From Macrocell

From I/O Direct

To C

en

tral S

wit

ch

Matr

ix

• Total sixteen 2:2 muxes per PAL block

• Every macrocell has one 2:2 mux


Uudet mikropiirit

High Density

January 2008 121


Number of Inputs 33/34/36 33

Number of PTs 90 98

For logic use 80 80

For OE use 8 16

For global PALinitialization

2 2

2:1 arch. 1:1 arch.

MACH 4(A) (1:1 Arch.) Product-Term Logic Array


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High Density

January 2008 122


Macrocell can driveone of 8 I/Os

I/O can chooseone of 8 macrocells

MUX I/OCell

macro-cell

macro-cell

macro-cell

macro-cell

macro-cell

macro-cell

macro-cell

macro-cell

I/OCell

I/OCell

I/OCell

I/OCell

I/OCell

I/OCell

I/OCell

I/OCell

macro-cell

MACH 4(A) (1:1 Arch.) Output Switch Matrix


Uudet mikropiirit

High Density

January 2008 123


From OutputSwitch Matrix

Individual OEProduct Term


MACH 4(A) (1:1 Arch.) I/O Cell


Uudet mikropiirit

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January 2008 124


MC to I/O Ratio

Focus

Max PT/MC

PT Clocks

Storage Elements

Input Types

Inputs/PAL Block

1:1 Arch.

1:1

I/O

20

Yes

Register/Latch

Direct

33

2:1 Arch.

2:1

Density

20

Yes

Register/Latch

Direct/Registered/Latched

33/34/36

MACH 4(A) Architectures Comparison


Uudet mikropiirit

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MACH 4(A) SpeedLockingTM

• SpeedLocking assures guaranteed timing– independent of the path taken through device

• No expander or PT adders required

• Ensures complete predictability

• All MACH 4(A) devices have SpeedLocking


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January 2008 126


OUT

Internal Feedback

External Feedback

Q

COMB / DFF / TFF /LATCH / SR* / JK* * simulated

tSS(T)

tSA(T)

tH(S/A)

tS(S/A)L

tH(S/A)L

tSRR

S/R

tPDi

tPDLi

tCO(S/A)i

tGO(S/A)i tSRiINPUT REG/

INPUT LATCH

tSIRS

tHIRS

tSIL

tHIL

tSIRZ

tHIRZ

tSILZ

tHILZ

tPDILi

tICOSi

tIGOSi

tPDILZi

Q

tPL

tSLW

tEA

tER

tBUF

CentralSwitchMatrix

IN

PIN CLK



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Adder Parameters


Output Buffer tBUF : Output Buffer delay adder

tSLW: Slow slew rate delay adder

Low Power tPL : Power down mode delay adder

Notes:

• tPL is an adder to setup time in synchronous data path

• tPL is an adder to clock to output time in asynchronous data path


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Feature MC I/O IN Ck OE FF Icc (mA) PackagesM4(LV)-32/32 32 32 2 2 32 32 25 44PLCC, 44TQFP, 48TQFPM4(LV)-64/32 64 32 2 2 32 96 25 44PLCC, 44TQFP, 48TQFPM4(LV)-96/48 96 48 8 4 48 144 50 100TQFPM4(LV)-128/64 128 64 6 4 64 192 70 100PQFP, 100TQFPM4(LV)-192/96 192 96 16 4 96 288 85 144TQFPM4(LV)-256/128 256 128 14 4 128 384 100 208PQFP, 256BGA

MACH 4 devices are available in: -7/-10/-12/-15 commercial grade-10/-12/-14/-18 industrial grade

Devices are dual-marked with commercial and industrial grades with industrial marks are one-speed grade slower, e.g. M4LV-256/128-7VC -10VI

MACH 4 Product Selection Guide


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Feature MC I/O IN Ck OE FF Packages

M4A(3,5)-32/32 32 32 2 2 32 32 44PLCC, 44TQFP, 48TQFP

M4A(3,5)-64/32 64 32 2 2 32 96 44PLCC, 44TQFP, 48TQFP

M4A(3,5)-96/48 96 48 8 4 48 144 100TQFP

M4A(3,5)-128/64 128 64 6 4 64 192 100PQFP, 100TQFP

M4A(3,5)-192/96 192 96 16 4 96 288 144TQFP

M4A(3,5)-256/128 256 128 14 4 128 384 208PQFP, 256BGA

M4A3-384 384 192 0 4 192 576 176TQFP(128), 208PQFP(160), 256BGA(192)

M4A3-512 512 256 0 4 256 768 176TQFP(128), 208PQFP(160), 256BGA(192), 352BGA(256)

MACH 4A devices have following speed options: (contact Vantis rep for availability)-50/-55/-60/-65/-7/-10/-12 commercial grade, -7/-10/-12/-14 industrial grade

Devices are dual-marked with commercial and industrial grades e.g. M4A3-256/128-7VC -10VI

MACH 4A Product Selection Guide


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32 64 96 128 192 256

Macrocells

M4A-32/32(3V & 5V)

5.0 ns

M4A-64/32(3V & 5V)

5.0 ns

*M4A-96/48(3V & 5V)

5.0 ns

M4A-128/64(3V & 5V)

5.0 ns

M4A-256/128(3V & 5V)

5.0 ns

M4A-192/96(3V & 5V)

5.0 ns

M4A-384/128(3V only)

6.5 ns

M4A-512/128(3V only)

6.5 ns

M4A-384/160(3V only)

6.5 ns

M4A-512/160(3V only)

6.5 ns

M4A-384/192(3V only)

6.5 ns

M4A-512/192(3V only)

6.5 ns

M4A-512/256(3V only)

6.5 ns

384 512

352 BGA

256 BGA

208 PQFP

176 TQFP

144 TQFP

100 TQFP/PQFP(*M4A-96/48 is only in 100TQFP)

44 PLCC48 TQFP44 TQFP

Note: All devices in same package are footprint compatible. Where a device has less I/Os it is a subset of other devices

MACH 4A Package Migration


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ispLSI and Mach Comparison


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Compare and Contrast

• Architecture

• Performance

• System Integration Features

• Two Comparisons– ispLSI2032VE -vs- M4A3-32/32

– ispLSI5512V -vs- M4A-512/256


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M4A3-32/32 -vs- ispLSI 2032VE

Feature M4A3-32/32 IspLSI 2032VE

Macrocells 322 Blocks

328 GLBs

I/Os + Inputs 32 + 2 32 + 3

Inputs to Array 33 18/GLB

PT Allocation Steering Sharing

Asynchronous Y Y

Architecture


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tPD 5.0ns 4.0ns/6.0ns

tCO 4.0ns 4.0ns

tSU 3.0ns 3.5ns

ProgrammingTime

4.2 sec 1 sec

Performance


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JTAG ISP Y Y

I/O Voltage 3.3, 5.0 3.3, 5.0

IOL 24mA 8mA

ProgrammingCycles

100 10,000


Features


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Feature M4A3-512 IspLSI 5512V

Macrocells 51232 Blocks

51216 GLBs

I/Os Up to 256 Up to 288

Inputs to Array 36 68

PT Allocation Steering Sharing

Asynchronous Y Y

M4A3-512 -vs- ispLSI 5512V

Architecture


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tPD 7.5ns 8.5ns/10ns

tCO 5.5ns 5.0ns

tSU 5.5ns 7.5ns

Performance


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JTAG ISP Y Y

I/O Voltage 3.3, 5.0 2.5, 3.3, 5.0

IOL 24mA 8mA

ProgrammingCycles

100 10,000


Features


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Comparison Summary

• ispLSI and MACH architectures have significant differences and similarities

• Differences:– Basic architecture and structure of routing schemes

– Macrocell features

These differences make the architectures complimentary.

• Similarities:– Feature sets

– Performance

The similarities allow the architectures to work together.


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ISP


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MACH JTAG & ISP Overview

• MACH parts having JTAG and In-System Programming (ISP) capabilities

• JTAG » Boundary Scan tests

» Software vendors

• In-System Programming (ISP)» Benefits of ISP

» Concurrent ISP

» ISP Procedures and resources

» Software tools overview


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JTAG 5-Pin Standard and Vantis 6-Pin Interface

• JTAG 5-Pin Standard programming port adds an optional TRST* (Test Reset) pin:

– used to asynchronously reset the TAP controller

– active LOW -- connect to Vcc/HIGH when not used

• Vantis 6-Pin Interface adds an ENABLE* pin for some MACH4xx parts:

– Used for programming

– Active LOW -- connect to GND/LOW if not required

– Devices using the Vantis 6-pin port are M4-96/96, M4-128 and M4-256 only


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** MACH 1 and MACH 2 Devices are JTAG-Compatible but not JTAG-Compliant

MACH Devices with the JTAG Feature

• MACH JTAG-ISP parts with JTAG 4-pin standard:

– MACH1XXSP**

– MACH2XXSP**

– MACH4-32

– MACH4-64

– MACH4-96/48

– MACH4-192

– MACH5XX

• JTAG-ISP parts with Vantis 6-pin programming port:

– MACH4-96/96

– MACH4-128

– MACH4-256

• To comply with JTAG 4-pin standard, connect TRST* to HIGH and ENABLE* to LOW


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JTAG Instructions

• Public and Private Instructions

• IEEE 1149.1/JTAG-compliant devices have the following mandatory public instructions:

– BYPASS

– SAMPLE/PRELOAD

– EXTEST

• MACH 1XXSP and 2XXSP parts have only the BYPASS instruction– No JTAG test capability, yet JTAG-compatible

• Private Instructions are used only by the manufacturer


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JTAG Optional Public Instructions

• Other public instructions include:– IDCODE

– HIGH-Z

– USERCODE (MACH 4 devices only)

• MACH devices have private instructions for programming and testing

– Used by Vantis for internal testing


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MACH In-System Programming

• No special programming pins required for MACH devices

• Regular 4-pin JTAG-standard port used to shift in:– Programming instructions

– Programming data

• Multiple MACH devices can be programmed in a serial boundary scan chain

– Non-Vantis devices are put in BYPASS mode


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Vcc-Independent Signal Level Programming

• MACH devices are Vcc level-independent programmable

• Devices powered by 5v and 3.3v can be programmed with the same data voltage level -- independent of Vcc level

• Programmable MACH devices with Vcc of 5v or 3.3v require data signals of 5v or less for In-System Programming

• Devices powered by 5v and 3.3v Vcc levels can be included in the same chain


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MACH JTAG-ISP Software

• VantisPRO (formerly MACHPRO)

• In-System Programming on a PC– DOS, Win 3.1, Win95 and Win NT 4.x versions

– DOS version is ideal for batch programming

• In-System Programming on Automated Test Equipment (ATE)– Use the output from VantisPRO for

» HP3070

» Teradyne

» GenRad

» Asset Intertech

• Embedded Programming– Code is resident in an on-board microprocessor

– Allows for remote design update


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VantisPRO

• Programs MACH devices in a JTAG chain having other non-Vantis JTAG-compliant devices

• Uses MACH JEDEC maps generated by any MACH design software tool

• Bulk erases the device

• Serializes the JEDEC (fusemap) file

• Bypasses devices not to be programmed

• Shifts the JEDEC data into the device

• Programs JEDEC data into the appropriate cells


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Parallel Port

Target Board

JTAGDevice

MACH5-256

MACH4-96

MACH5-128

PC

Ten-Wire Cable4-wires: Standard JTAG1-wire: TRST*1-wire: ENABLE*1-wire: Vcc3-wires: Ground

JTAG-ISP Programming Cable

• Cable plugs directly into a IBM-compatible PC parallel port

• Lattice cable can be used by selecting– Project|Advanced Options…|Use Alternate Port Mapping


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In-System Programming Procedure

• Use DesignDirect software to create a JEDEC (fusemap) file

• Load VantisPRO software onto the PC– With DesignDirect, VantisPRO is already loaded by default

• Create a Chain file describing the JTAG chain– List devices in order from TDI to TDO

– Specify “program” or “bypass” for each device

– The Chain file may consist of a single device

• VantisPRO does the rest!


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WHAT YOU NEED WHERE TO FIND IT

JEDEC File

VantisPRO

Cable Schematic

Any CAE tool that supports Vantis

www.vantis.com, Vantis Sales

www.vantis.com, Vantis Sales

In-System Programming Resources


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Concurrent Programming of Multiple Devices

• VantisPRO can program many devices at once

• Programming “wait” time is shared between all devices

• Verification is performed serially

• Concurrent programming further reduces costs of programming


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JTAG Chain Size

Program and PatternVerify Time

(HP 3070 @ 1 MHz)

(1) MACH4-128

(3) MACH4-128

(10) MACH4-128

4.7 seconds

5.3 seconds

7.9 seconds

MACH Concurrent Programming on the HP 3070


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TMSTCK

TDO

TDI

(Non-VantisDevice)

BYPASS

(Non-VantisDevice)

BYPASS

BYPASS

(Non-VantisDevice)

Concurrent Programming of Multiple Devices

• 10 MACH devices ATE-programmed in less than 8 seconds

• Some fast PCs can accomplish the same in 50 to 60 seconds


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MACH Starter Kit

• MACH Starter Kit includes:– Software - CD ROM with DesignDirect Base software and VantisPRO

– Programming cable - Six-foot long and buffered

– MACH ISP demo board with M4-32/32-7JC & M4-64/32-7JC sample devices

– MACH ISP manual

• VantisPRO software and cable schematic information available at:– Web site: www.vantis.com


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Literature and Support

• www.vantis.com/literature has all data sheets and application notes available. There are always additional in development.

• [email protected] can answer all questions regarding MACH devices and software.

• Technical call center: (888)VANTIS-1

• Reference design program for IP needs– SDRAM Controller

– PCI Target

– Page-mode DRAM Controller

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