( JB+á 7T-SRAM B B B¥BvB¦ B B B^B B B]Bt...
1
7T-SRAM SOI-7T-SRAM : : (i) WBL INV(R) nMOS N1 (i) WBL INV(R) nMOS N1 (ii) WWL RWL nMOS N3,N4 nMOS N5 (ii) WWL RWL nMOS N3,N4 nMOS N5 “1” “1” (FTI) RBL WBL GND VDDM GND WWL WL for N5 BC for N3 BC for N2 : M2 0.8 0 Me Sh b re (Ex. 4 word x 2 bit ) (Ex. 4 word x 2 bit ) - 90nm - V DD = 0.6V - : V tn / V tp = 0.39 / −0.44V - : - SRAM : - 90nm - V DD = 0.6V - : V tn / V tp = 0.39 / −0.44V - : L / W = 0.10 / 0.16µm L / W = 0.10 / 0.16µm - SRAM : 8K-bit (256word x 32bit) 8K-bit (256word x 32bit) - - 0.7mV 51.1mV 0.7mV 51.1mV ‘1’-Write ‘1’-Write ‘1’-write mode ‘1’-write mode read mode read mode 100 150 200 250 5.0 ] Occurrences µ = 0.80 ns σ = 0.10 ns σ/µ = 12.7 % µ = 2.63 ns σ = 0 55 ns 1 % 0.211 0.211 0.127 0.127 (/µ) (/µ) 0 50 100 150 200 250 300 -25 75 100 ‘ [mV] Occurrences µ = 0.7 mV σ = 7.7 mV µ = 50.9 mV σ = 7.7 mV Body-bias - (σ/µ): - (σ/µ): 11.0 11.0 0.15 0.15 ( ) ( ) - - 1/73x 1/73x 0.60x 73x 73x Body-tied ( ) Body-bias Body-tied ( ) V th / 3σ = V th /10 V th / 3σ = V th /10 Low 1 '0 '0' W W ) L L L. Chang, 2005 Symposium on VLSI Technology L. Chang, 2005 Symposium on VLSI Technology WBL WBL WBLB WBLB RBL RBL RWL RWL WWL WWL 8T-SRAM 8T-SRAM SOI SOI ? ? - - - - - - 8T-SRAM 13% - - 8T-SRAM 13% - - SRAM SRAM / 7T-SRAM / 7T-SRAM 7/8T-SRAM 7T-SRAM 7/8T-SRAM 7T-SRAM - (73x) (0.57x) - - - (73x) (0.57x) - - (-40%) (-40%) Scaling Scaling 90nm 90nm 65nm 65nm - - - - - - - - - - ?? ?? 6T-SRAM: 6T-SRAM: - - β - - β 8T/7T-SRAM: , β = 1 8T/7T-SRAM: , β = 1 V DD V DD V DD V DD WL=“High” WL=“High” “High” Q “High” Q “High” “High” “High” “High” 6T-SRAM 6T-SRAM “Low” QB “Low” QB WBL WBL RWL RWL RBL RBL WWL WWL “Low” QB “Low” QB “High” Q “High” Q “Low” “Low” “High” “High” “High” “High” 7T-SRAM N1 N1 P2 P2 P1 P1 WBL WBL RWL RWL RBL RBL WWL WWL VSSM(L) VSSM(L) VSSM(R) VSSM(R) VDDM VDDM N2 N2 N3 N3 N4 N4 N5 N5 WBL WBL RBL RBL 7T-SRAM 7T-SRAM T. Suzuki, 2006 Symposium on VLSI Circuits T. Suzuki, 2006 Symposium on VLSI Circuits Lower V th for same I off Lower V th for same I off Y. Hirano et al., VLSI Technology 2007. Y. Hirano et al., VLSI Technology 2007. Hybrid Trench Isolation SOI MOSFET Hybrid Trench Isolation SOI MOSFET Body Body N N + P P - P P + N N + N N - Gate Gate Gate Gate Body Body N N + P P - P P + N N + N N - Gate Gate Gate Gate Y. Hirano et al., IEDM 2003. Y. Hirano et al., IEDM 2003. X-X’ X-X’ Y-Y’ Y-Y’ - Tr. (V th ) - ( I on /I off ) - - - Tr. (V th ) - ( I on /I off ) - - V1 V1 V2 V2 N1 N1 P2 P2 P1 P1 WBL WBL RWL RWL RBL RBL WWL WWL INV(R) INV(R) N2 N2 N3 N3 N4 N4 N5 N5 INV(L) INV(L) VSSM(R) VSSM(R) VSSM(L) VSSM(L) SRAM SRAM V th SRAM V th SRAM V th V th 90nm SRAM 90nm SRAM SRAM SRAM 8T/7T-SRAM: 8T/7T-SRAM: T-SRAM T-SRAM ABC(Active Body-biasing Controlled)-SOI ABC(Active Body-biasing Controlled)-SOI SOI-7T-SRAM SOI-7T-SRAM - / - - / - 43% 36% 43% 36% N : # of shared memory cells (MCs) N : # of shared memory cells (MCs) 1.00 1.10 1.20 1.30 1.40 1.50 0 8 16 24 32 -3.00 -2.00 -1.00 0.00 1.00 2.00 64word 128word 256word Timing slack (t WWL -t body ) [ns] Timing slack (t WWL -t body ) [ns] ( N =32 ) ( N =32 ) Area overhead (prop./conv.) Area overhead (prop./conv.) vs. / vs. / V WWL V WWL V body V body N < 8: N < 8: time time N > 8: N > 8: V WWL V WWL V body V body time time (2) (2) ( ( 3) 3) (V th ) (4) (4) (V th ) (5) (5) (1) (1) RBL(prop.) RWL RBL(conv.) BL out (prop.) BL out (conv.) 8.19ns 4.69ns CLK RBL(prop.) RWL RBL(conv.) BL out (prop.) BL out (conv.) 8.19ns 4.69ns CLK WWL VSSM(L) V1(conv.) V1(prop.) V2(conv.) V2(prop.) 3.05ns 4.80ns WBL CLK V body (N1) VSSM(L) V1(conv.) V1(prop.) V2(prop.) 3.05ns 4.80ns WBL CLK V body (N1)
Transcript of ( JB+á 7T-SRAM B B B¥BvB¦ B B B^B B B]Bt...
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7T-SRAM
SOI-7T-SRAM
:: (i) WBL INV(R) nMOSN1
(i) WBL INV(R) nMOSN1
(ii) WWL RWLnMOS N3,N4 nMOS N5
(ii) WWL RWLnMOS N3,N4 nMOS N5
“1”“1”
(FTI)
RBLWBLGND VDDM GND
WWL
WL
forN5
BC forN3
BC forN2
: M2
0.8
0
Me
Shbre
(Ex. 4 word x 2 bit )(Ex. 4 word x 2 bit )
- 90nm- VDD = 0.6V- :
Vtn / Vtp = 0.39 / −0.44V
- :
- SRAM :
- 90nm- VDD = 0.6V- :
Vtn / Vtp = 0.39 / −0.44V
- : L / W = 0.10 / 0.16µmL / W = 0.10 / 0.16µm
- SRAM : 8K-bit (256word x 32bit)8K-bit (256word x 32bit)
--
0.7mV 51.1mV0.7mV 51.1mV
‘1’-Write‘1’-Write
‘1’-write mode‘1’-write mode read moderead mode
100
150
200
250
5.0
]
Occ
urre
nces µ = 0.80 ns
σ = 0.10 nsσ/µ = 12.7 %
µ = 2.63 nsσ = 0 55 ns
1 %
0.2110.211 0.1270.127( /µ)( /µ)
0
50
100
150
200
250
300
-25 75 100
‘ [mV]
Occ
urre
nces
µ = 0.7 mVσ = 7.7 mV
µ = 50.9 mVσ = 7.7 mV
Body-bias
- (σ/µ):- (σ/µ):
11.011.0 0.150.15 ( )( )
--
1/73x1/73x 0.60x
73x73x
Body-tied ( )
Body-bias
Body-tied ( )
Vth / 3σ = Vth/10 Vth / 3σ = Vth/10
Low
1'0'0'WW
)
LL
1'0'0'WW
)
LL
L. Chang, 2005 Symposium on VLSI Technology L. Chang, 2005 Symposium on VLSI Technology
WBLWBL WBLBWBLB RBLRBLRWLRWLWWLWWL
8T-SRAM8T-SRAM
SOISOI??
--
--
-- 8T-SRAM 13%-- 8T-SRAM 13%
--
SRAMSRAM
/7T-SRAM
/7T-SRAM
7/8T-SRAM7T-SRAM7/8T-SRAM7T-SRAM
- (73x) (0.57x)--
- (73x) (0.57x)-- (-40%)(-40%)
ScalingScaling
90nm90nm90nm90nm
65nm65nm65nm65nm
---
---
-
-
-
-
????
6T-SRAM:6T-SRAM: -- β-- β
8T/7T-SRAM: , β = 18T/7T-SRAM: , β = 1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
WL=“High”WL=“High”
“High”Q
“High”Q
“High”“High” “High”“High”
6T-SRAM6T-SRAM
“Low”QB
“Low”QB
7T-SRAM-SRAM
WBLWBLRWLRWL
RBLRBL
WWLWWL
“Low”QB
“Low”QB“High”
Q“High”
Q
“Low”“Low” “High”“High”
“High”“High”7T-SRAM
N1N1
P2P2 P1P1
WBLWBLRWLRWL
RBLRBL
WWLWWL
VSSM(L)VSSM(L) VSSM(R)VSSM(R)
VDDMVDDM
N2N2
N3N3
N4N4
N5N5WBLWBL
RBLRBL
7T-SRAM7T-SRAM
T. Suzuki, 2006 Symposium on VLSI Circuits T. Suzuki, 2006 Symposium on VLSI Circuits
Lower Vthfor same Ioff
Lower Vthfor same Ioff
Y. Hirano et al., VLSI Technology 2007.Y. Hirano et al., VLSI Technology 2007.
Hybrid Trench Isolation SOI MOSFET
Hybrid Trench Isolation SOI MOSFET
Body
Body
NN++PP--
PP++
NN++
NN--
Gate
Gate
Gate
Gate
Body
Body
NN++PP--
PP++
NN++
NN--
Gate
Gate
Gate
Gate
Y. Hirano et al., IEDM 2003.Y. Hirano et al., IEDM 2003.
X-X’X-X’
Y-Y’Y-Y’
- Tr. (Vth)-
( Ion/Ioff )--
- Tr. (Vth)-
( Ion/Ioff )--
V1V1 V2V2N1N1
P2P2 P1P1
WBLWBLRWLRWL
RBLRBL
WWLWWL
INV(R)INV(R)
N2N2N3N3
N4N4
N5N5
INV(L)INV(L)VSSM(R)VSSM(R)VSSM(L)VSSM(L)
SRAMSRAM
VthSRAM
VthSRAM
VthVth
90nm SRAM90nm SRAM
SRAMSRAM 8T/7T-SRAM: 8T/7T-SRAM:
T-SRAMT-SRAM ABC(Active Body-biasing Controlled)-SOIABC(Active Body-biasing Controlled)-SOI
SOI-7T-SRAMSOI-7T-SRAM
- /-- /-
43%36% 43%36%N : # of shared memory cells (MCs)N : # of shared memory cells (MCs)
1.00
1.10
1.20
1.30
1.40
1.50
0 8 16 24 32-3.00
-2.00
-1.00
0.00
1.00
2.0064word
128word256word
Tim
ing
slac
k(t
WW
L-
t bod
y) [
ns]
Tim
ing
slac
k(t
WW
L-
t bod
y) [
ns]
( N =32 )( N =32 )
Area
ove
rhea
d (p
rop.
/con
v.)
Area
ove
rhea
d (p
rop.
/con
v.)
vs. / vs. /
VWWLVWWL
VbodyVbody
N < 8:N < 8:
timetime
N > 8:N > 8:VWWLVWWL
VbodyVbodytimetime
(2)(2) ((3) 3) (Vth)(4)(4) (Vth) (5)(5)
(1)(1)
RBL(prop.)
RWL
RBL(conv.)
BLout(prop.)
BLout(conv.)
8.19ns
4.69ns
CLK
RBL(prop.)
RWL
RBL(conv.)
BLout(prop.)
BLout(conv.)
8.19ns
4.69ns
CLK
WWL
VSSM(L)
V1(conv.)
V1(prop.)
V2(conv.)
V2(prop.)
3.05ns
4.80ns
WBL
CLK
Vbody(N1)
VSSM(L)
V1(conv.)
V1(prop.)
V2(prop.)
3.05ns
4.80ns
WBL
CLK
Vbody(N1)
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