~ EDA lab ~ Interconnect Verification for SOC Jing-Yang Jou Department of Electronics Engineering...

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Interconnect Verification for SOC

Jing-Yang Jou

Department of Electronics Engineering

National Chiao Tung University

Hsinchu, Taiwan

E-mail: [email protected]

URL: http://eda.ee.nctu.edu.tw/jyjou



Outlines

• Interconnect verification– Motivation– The port order fault (POF) model– The integration verification – Automatic verification pattern generation

(AVPG)



Verification Throughput

• The factors that govern simulation-based verification throughput:– The speed of the simulator– The complexity of the design– The size of the test (verification) bench



System Design Verification

• SOB verification– Components are designed, verified, manufactured, and

tested (fault free building blocks )– Limit to detecting faults in the interconnection among the

components

• SOC verification– Components are design error free building blocks– Limit to detecting the misplacements of the

interconnection among the components

• Reduce the verification complexity– Port Order Fault (POF) model



Outlines

• Interconnect verification– Motivation– The port order fault (POF) model– The integration verification – Automatic verification pattern generation

(AVPG)



Basic Assumptions of the POF Model

• A faulty component has at least two I/O ports misplaced in the integrated design

• Components (IPs) are fault free

• Only the interconnection among the components could be faulty



POF Variety (1/3)

• Type-I POF

4-bit Adder

B3A3 B2A2 B1A1

B0

A0

S3 S2 S1

S0

CINCOUT



4-bit Adder

B3A3 B2A2 B1A1 B0A0

S3 S2 S1 S0

CINCOUT

• Type-II POF

POF Variety (2/3)



POF Variety (3/3)

4-bit Adder

B3A3 B2A2 B1A1 B0A0

S3S2S1S0

CINCOUT

• Type-III POF



Typical Errors in the Integrated SOC Design

• VCs are connected with wrong port orders

• VCs with incompatible communication protocols are directly connected– PCI vs. AMBA

• Interface parameters are not properly configured– Baud rate 2400 vs. baud rate 9600

TXRX

TXRX

TXRX

TXRX



Outlines

• Interconnect verification– Motivation– The port order fault (POF) model– The integration verification– Automatic verification pattern generation

(AVPG)



Interconnect Testing

IP2IP1

wrapperwrapper

Applypatterns

Observeresponses



Interconnect Verification

IP2IP1

wrapperwrapper

Applypatterns

Observeresponses



Integration Verification

BLK1

BLK2

BLK4

Apply patternsT to PIs

Interconnect A

Verification Patterns

Generation

BLK3

BLK5

Interconnect B

Observeresponses R

from POs

Output

Analyzer

BLK6

Interconnect C



• Verifying the interconnect A, B, and C– Apply patterns T to PIs and observe responses R from POs

• The generation of T depends on the functionalities of BLK1 ~BLK6

• Complexity of cores increases and more cores are involved– T becomes harder to generate

• Solution ?




System Chip with P1500 Cores



• IEEE P1500 – Establishes the mechanism that test patterns of any

CUT can be applied to PIs of the system chip and test results can be propagated to POs of the system chip via user defined TAMs

– Pre-defined operations: core-internal test, core-external test, bypass, isolation, and normal modes




Interconnect Verification

IP2IP1

wrapperwrapper

Applypatterns

Observeresponses



Integration VerificationApply patterns

T to PIs

Interconnect A

Observe

responses R

from POs


Generation

BLK3

Output

Analyzer

BLK1

core

1

wrapper

core

2

wrapper

BLK2

normal mode

core

4

wrapper

BLK4

external test mode

external test mode



Integration VerificationApply patterns

T to PIs

Interconnect C

Observeresponses R

from POs


Generation

BLK3

OutputAnalyzer

bypass mode BLK1

core1

wrapper

core2

wrapper

BLK2

external test modeBLK4

bypass mode

SoSi

Si So

BLK5

normal mode

core6

wrapper

BLK6

core4

wrapper

VerifiedInterconnect B



Verification Features• Reduce the complexity of POF verification

– Focus on the functionality of the added block solely when generating the verification patterns

• Exercise the core via the normal operation path to verify the interconnect– Consistency check of simulation results and

expected ones

• Reuse the hardware overhead incurred in the testing phase



Outlines

• Interconnect verification– Motivation– The port order fault (POF) model– The integration verification– Automatic verification pattern generation

(AVPG)



Automatic Verification Pattern Generation (AVPG)

• Fault Activation– All N!-1 POFs have to be activated

• Fault Propagation– Determined by simulation outputs

• Undetected Port Sequences (UPSs) Calculation– Outputs analysis



bench |PI| |PO| lits pats. F.C. time(sec) c17 5 2 12 5 1 1

c880 60 26 703 243 0.99999999 70 c1355 41 32 1032 64 1 13 c1908 33 25 1497 51 1 42 c432 36 7 372 38 1 5 c499 41 32 616 33 1 8

c3540 50 22 2934 145 1 727 c5315 178 123 4369 371 1 931 c2670 233 140 2043 521 0.99999999 721 c7552 207 108 6098 1627 0.99999999 1826 c6288 32 32 4800 30 0.99999999 175

des 256 245 7412 428 1 159 alu4 14 8 1278 22 1 3

apex6 135 99 904 234 0.99999999 406 i9 88 63 1453 139 1 25 i8 133 81 4626 266 1 415 i7 199 67 1311 292 1 103 i6 138 67 1037 165 1 77 i5 133 66 556 155 1 63

duke2 22 29 1746 74 1 83 rot 135 107 1424 524 0.99999999 246 x1 51 35 2141 275 0.99999999 34 x3 135 99 1816 249 0.99999999 171 x4 94 71 1040 352 0.99999999 69

pair 173 137 2667 217 1 443

Experimental Results



• Interconnect verification provides a sufficient high level of confidence on verifying the correctness of the core-based system (SOC) design

• Proposed AVPG can generate efficient verification patterns with high POF coverage

Conclusions

~ EDA lab ~ Interconnect Verification for SOC Jing-Yang Jou Department of Electronics Engineering...

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