1

“abcnasic” SEU strategies

• Simple ideas and proposals

• Assumptions based on :

• Tentative to limit the triplications where strictly needed

• In criticality order

Criticality Method Example

Very critical Block triplication

Critical Commands

Critical ECC (Hamming)Local triplication

Sequencers

Less specific FIFO controls

Low DICE cell Baseline every where else (?)

2

“abcnasic” SEU strategies• Protection about the “DCL” functions

Read

Read

L1Bu

ffer

Read

out P

ort F

IFO

DCL

An soft error on DCL may result in one or a few packets loss, if properly protected.

One option would be the use of a watchdog synchronized to DCL_BUSY

This has to be evaluated by model and simulation

(Applying full triplication on the DCL logic would be a killer, because of the peak current activity)

Write

Watchdog

Busy Reset

3

“abcnasic” SEU strategiesChip to chip data path chain on module/hybrid

T.fifo

ABCN-Last-1 ABCN-Last

ABCN-Last-1 data pending

WEWE

ABCN-Last-2 data pending

To HCC

Header Data Header Data Header Data

T.fifo

4

“abcnasic” SEU strategies• Minimum service of the Readout function

aCSR

SerializerReadout

Actually the “Readout” is the most “”unknown” part for concerns about soft errors, but the function is critical (serializer has to be able to send packets)

An option is to provide a “minimal” mode (after soft error or by addressable command) which is :BYPASS (to adjacent chip data : ie only passing data through w/o local chip interruption)This BYPASS mode should be fully soft error protected

R3L1

bCSR

ADJBypass (soft error or command)

5

Dice Cell

S. BonaciniCERN

6

Dice CellS. Bonacini CERN

Double DFF with interleaved subblocks to separate redundant nodes

4.5um

The DICE cell is currently ported to the current version of the IBM 130nm cell library (not Artisan) by Filipe De Sousa