© 2007 National Tsing Hua University IC-DFN Workshop, Las Vegas, USA, 2007/02/10 Application and...

IC-DFN Workshop, Las Vegas, USA, 2007/02/10

© 2007 National Tsing Hua University

Application and Validation of 3D Electromagnetic and

Thermal Modeling

Keh-Jeng Chang, Ph.D.

Associate Professor

Department of Computer Science

National Tsing Hua University, Hsinchu, Taiwan

[email protected]

- 2 -© 2007 National Tsing Hua University

Acknowledgements

The authors want to thank the following institutes for providing this research with generous resources:

National Science Council, Taipei Ministry of Economic Affairs, Executive Yuan, Taipei Ministry of Education, Executive Yuan, Taipei TSMC, Hsinchu UMC, Hsinchu Silvaco International, Santa Clara Clear Shape Technologies, Sunnyvale


Major References

1. Silvaco International, “TCAD for Flat Panel Display,” Technical Presentation Slides, Jan. 2006, Hsinchu, Taiwan.

2. Y.H. Tai, Design and Operation of TFT-LCD Panels, ISBN 957-11-4291-3 (Chinese Language), June 2006, Taipei, Taiwan.

3. K.J. Chang, “Accurate On-Chip Variation Modeling to Achieve Design for Manufacturability,” 4th IWSOC, July 2004, Banff, Canada.

4. K.J. Chang et al., “Verifying On-Chip Inductance Extraction with Silicon Measurement,” www.eetimes.com, Nov. 2003.

5. J.F. Huang et al., “Modeling Sub-90nm On-Chip variation Using Monte Carlo Method for DFM,” 12th ASP-DAC, Jan. 2007, Yokohama, Japan.

6. J. Xiong et al., “Robust Extraction of Spatial Correlation,” 6th ISPD, April 2006, San Jose, USA.

7. K.M. Cham et al., Computer-Aided Design and VLSI Device Development, 2nd edition, Kluwer ISBN 0-89838-277-7, 1988.


Outlines

The emerging needs of 3D models3D research summaryApplications of 3D modelsValidations of 3D modelsIn a nutshell


The Emerging Needs of 3D Models

A “fishbone” viewpoint of 3D research subjects

Art/social

Biological/medical

CFD/naval

Molecular/atomic

Mechanical

Thermal

Optical/optoelectrical

Material/chemical

DC+TEM (deterministic)

Full-wave (deterministic)

Statistical

3D


3D Research Summary (Algorithms)

Modeling (1D, 2D, 3D)EmpiricalSimulated

SimulationsFinite difference (with or without time domain)Finite elementBoundary elementMonte Carlo / Markov / Brownian

Governing mathematicsMaxwell’sPoisson / LaplaceFourierBand gapet al.


3D Research Summary (Inputs/Outputs)

Models based on profiles/structures of nanodevicesDimensions on x-axis, y-axis, and z-axis

Cartesian coordinates dominate 3D modeling in electronics

Material propertiesPermittivityPermeabilityStressResistivityLeakageThermal conductivityet al.

3D mechanical / thermal / electromagnetic nanodevice models

Electrical and non-structural model/characterizationSPICE-level circuit simulations


3D Research Summary (Bright Future)

Commercially successful (profitable) and sustainable stories in 3D modeling for the electronicsAnsoftAnsysSilvacoMatlabSigrityBrion (merged to ASML)Numerical Technologies (merged to Synopsys)Etc.


TFT Process Profiles / Structures


Applying 3D Models to TFT-LCD

Vertical structure of a pixel and its equivalent circuit


TFT-LCD Designs to Prevent Mura

Source: Silvaco ‘06

Note: Validating mura product defects through 3D TFT-LCD models is an on-going research in NTHU-CS.


Emerging 3D IC Technologies


Manufacturable Through Silicon Vias

Source: P. Franzon, NCSU, ‘05

The growing popularity of trough silicon vias (TSV) and on-chip spiral inductaors.


1D Thermal Modeling

Performed in NTHU-CS ‘06


2D Thermal Modeling


3D Thermal Modeling (1/2)

Heat sink (30oC) on top of the silicon chip while the CMOS pn junction is at 77oC.


3D Thermal Modeling (2/2)


Deterministic Eectrical 3-D Modeling

DRC-clean nanometer circuit layouts

Current pseudo 3D layout parameter extraction (LPE)

SPICE decks

Timing simulations and clock speed comparisons (We suggest that the new 3D LPE should be adopted if the compared difference is > 10%.)

New 3D layout parameter extraction (LPE)

SPICE decks


3D Capacitances by 3-D Tools

Figure 1.

Complex nanometer 3D profiles for parasitic capacitance models.


Nanometer Ring Oscillator

• Ring oscillator layout (left) uses Prof. His-Pin Ma’s design

• The corresponding schematic (right)


Detailed SPICE Simulations


Current EDA vs. 3D EDA Differences

Circuit Ring Oscillator 1 Ring Oscillator 2 Ring Oscillator 3Layout area 430.56 um^2 73.88 um^2 55.14 um^2

Speed with pseudo-3D EDA 0.694 GHz 2.54 GHz 6.99 GHz

Speed with 3D EDA 0.552 GHz 2.1 GHz 5.46 GHzRealistic degradation 20.39% 17.40% 21.86%

• The above circuit performance degradation data are real if the 3D models are accurate.

• The pseudo-3D EDA tools are implied to be too optimistic and should be replaced with the new 3D EDA tools.

• The 3D EDA tools (not yet validated) are more pessimistic and therefore are likely to be more realistic.


Applying and Validating 3D Models (1/4)

Source: UMC ‘03


Physical Views of Sub-100nm VLSI

2-D and 3-D views of sub-100nm physical structures (Courtesy: UMC, 2006)


Dimensions Affecting Capacitances


Varying Nanometer BEOL Profiles

Source: IWSOC ‘04


Material Properties as Profiles

Source: IEDM ‘06


Validating or Failure in Validating?

Sub-100nm BEOL

0.150.170.190.210.230.250.27

0.1 0.15 0.2C_normalized

R_

no

rma

lize

d

Silicon data

Model corners

Source: ASP-DAC ‘07


Gate Oxide On-Chip Variations

Source: IBM/UCLA ISPD’06 paper


Lithographic Imaging in Sub-100nm

Courtesy Porf. KY Tsai of NTUEE, 2006


Resolution Enhancement Tech (RET)

RET includes Optical Proximity Correction (OPC)


3-D Modeling and Predicting RET

Profiles through Resolution Enhancement Technology and Detailed Fourier Transform (not yet validated)


In a Nutshell

3-D electrical modeling for resistance, capacitance, thermal, inductance, and transmission lines of TFT-LCD and sub-90nm devices are performed but more are planned.

3-D lithographic modeling for sub-100nm with National Taiwan University and commercial companies is started.

3-D modeling of etching/CMP or reliability not started yet.

© 2007 National Tsing Hua University IC-DFN Workshop, Las Vegas, USA, 2007/02/10 Application and...

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