qst2up

20130327 IEICE D Hanada en Draft

A Detailed Router for Field-programmable Gate Arrays

A Novel Low-power FPGA Routing Switch

A Tileable Switch Module Architecture for Homogeneous 3D FPGAs

Algorithms for an FPGA Switch Module Routing Problem With Application to Global Routing

Call for Papers

Delay Optimal Low-power Circuit Clustering for FPGAs With Dual Supply Voltages

Designing a 3-D FPGA- Switch Box Architecture and Thermal Issues

Dynamic Voltage Scaling for Commercial FPGAs

Exploring Alternative 3d Fpga Architectures

General Models and a Reduction Design

General Switch Box Modeling and Optimization

GlitchLess - An Active Glitch Minimization Technique for FPGAs

glsvlsi09b

HARP Hard-wired Routing Pattern FPGAs

iCE FPGA

Low-Power and Reliable Clock Network Design for TSV Based 3D ICs

meijs_prorisc_90

3D FPGA Resource Management and Fragmentation Metric for Hardware Multitasking