razi
[Lchn] application for best o gip
[AIESEC Hanoi] EP Profile Winter 2014
2012 Report to Congress
Efficient parallel architecture for multi-level forward discrete wavelet transform processors
Reduced models of multi-stage cyclic structures using cyclic symmetry reduction and component mode synthesis
[IEEE 2014 IEEE Fifth International Conference on Communications and Electronics (ICCE) - Danang, Vietnam (2014.7.30-2014.8.1)] 2014 IEEE Fifth International Conference on Communications
97 08 07 Business Modeling
Chapter 1 - An Overview of Compiler - Sinh Vien