Comparison of VHDL Verilog and SystemVerilog

Impact User Guide

FPGA Disadvantages

VHDL Reference Guide From Xilinx

The Verilog Hardware Description Language 5E (Thomas & Moorby)

An Introduction to JTAG Boundary Scan From Sun Microelectronics

FPGA & CPLD Architectures, A Tutorial (Stephen Brown & Jonathan Rose)

HDL Chip Design Using VHDL or Verilog (Douglas J Smith) Part 1

HDL Chip Design Using VHDL or Verilog (Douglas J Smith) Part 2

HDL Chip Design Using VHDL or Verilog (Douglas J Smith) Part 3