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Zvi Kohavi and Niraj K. Jha

Multi-level Logic SynthesisMulti-level Logic Synthesis

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Logic SynthesisLogic Synthesis

Technology-independent: Optimize circuit for targeted design objective using laws of Boolean Algebra

• Example objective: minimize area under a delay constraint• Apply following logic transformations iteratively: preserves input/output behavior of

circuits– Factoring– Decomposition– Extraction– Substitution– Elimination

Technology-dependent: map resultant circuit to a library of gates available for the given semiconductor technology

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FactoringFactoringFactoring: converts a sum-of-products expression to an expression with multiple levels without introducing any subfunctions

Factored form: a recursive sum-of-products representation

Example: Factor f = uvxz + wxz + u’y’z + v’x’z’ + v’yz’

f = uvxz+wxz+u y z+v x z +v yzx

(a) Network graph for sum of products.zy

wvu

x

(b) Network graph for factored expression.zy

wvu

f = z(x(uv+w)+u y )+(x +y)v z

f

v

zy

v

w

u

y

v

z

z

x

zx

u

x

(c) Two-level circuit.

z

(d) Multi-level circuit.

f

uv

w x

uy

z

xy

vz

Literal-count of factored form: 11 (reduced from 16)

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DecompositionDecompositionDecomposition: replaces a factored switching expression with a set of new expressions

Example: Factored expression f = z(x(uv + w) + u’y’) + (x’ + y)v’z’ can be decomposed as

f1 = uv + w

f2 = x’ + y

f3 = v’z’

f4 = xf1 + u’y’

f = f2f3 + zf4 x

z

y

w

v

u f1 = uv+w

f2 = x +y

f3 = v z

f4 = xf1+u y

f = f2f3+zf4

Literal-count: 15

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ExtractionExtractionExtraction: extracts common subexpressions from two or more expressions in factored form

Example: Consider

f1 = (uv + w)x + u’y’

f2 = (uv + w)z

• After extraction:

f1 = f3x + u’y’

f2 = f3z

f3 = uv + w

Literal-count: reduces from 10 to 9

x

z

y

w

v

u

f1 = (uv+w)x+u y

(a) Network graph before extraction.

f2 = f3z f2 = (uv+w)zx

z

y

w

v

u

f3 = uv+w

(b) Network graph after extraction.

f1 = f3x+u y

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SubstitutionSubstitutionSubstitution: replaces a subexpression in expression f with a variable g corresponding to a node in the network graph

• g is substituted into f, or• f is expressed in terms of g

Example: Consider

f1 = uvx + wx + u’y’

f2 = uv + w

• After substitution:

f1 = f2x + u’y’

Literal-count: reduces from 10 to 7

x

y

w

v

u

f1 = uvx+wx+u y

(a) Network graph before substitution.

f2 = uv+w

(b) Network graph after substitution.

x

y

w

v

u

f1 = f2x+u y

f2 = uv+w

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EliminationElimination

Elimination: eliminates an internal node from the network graph

Example: Consider

f1 = x + f2

f2 = y + z

• After elimination: if f2 not needed elsewhere

f1 = x + y + z

Literal-count: reduces from 4 to 3

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Techniques for FactoringTechniques for FactoringAlgebraic expression: no implicant of the expression contains another implicant

Example: x + yz

Boolean expression: an expression that does not satisfy above condition

Example: x + xy

Operations on algebraic expressions simpler: can be treated similarly to multiplication and division of polynomials

• Disadvantage: prevents exploitation of all laws of Boolean Algebra– Idempotency, dual of distributivity [x + yz = (x + y)(x + z)], and absorption cannot be used as they do not

have an analog in conventional polynomial algebra– Complementation (x + x’ = 1 and xx’ = 0), involution and De Morgan’s theorem cannot be used since

complements are not defined in polynomial algebra– Complemented literals are deemed to be unrelated to uncomplemented literals

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Algebraic Factored FormAlgebraic Factored FormFactored form:

• Algebraic if multiplication of its terms yields an algebraic sum-of-products expression without the use of above-mentioned laws

• Boolean otherwise

Example: Factored form (w+x)(y+z) is algebraic since wy + wz + xy + xz is algebraic

Example: Factored form (w + yz)(x + yz) is not algebraic, but Boolean, because wx + wyz + xyz + yzyz is not algebraic

• yzyz cannot be simplified because idempotency cannot be used• This term is not allowed to absorb xyz since absorption law is not allowed

Example: (x + y)(x’ + z) is not algebraic since multiplying it out gives xx’ which cannot be simplified further

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Division OperationDivision OperationDivision operation: f = fdfq + fr

• fd: divisor

• fq: quotient

• fr: remainder

Algebraic division: if fd and fq have no variables in common

• Else, Boolean division

• fd: correspondingly an algebraic or Boolean divisor

• If fr = 0: fd correspondingly an algebraic or Boolean factor

Example: Let f1 = vx + vy + wx + wy + z = (v + w)(x + y) + z

• Algebraic divisor: (v + w)• Quotient: (x + y)• Remainder: z

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Division Operation (Contd.)Division Operation (Contd.)

Example: Let f2 = vx + vy + wx + wy = (v + w)(x + y)

• Algebraic factors: (v + w), (x + y)

Example: Let f3 = w + xy + z = (w + x)(w + y) + z

• Boolean divisors: (w + x), (w + y)

Example: Let f4 = w + xy = (w + x)(w + y)

• Boolean factors: (w + x), (w + y)

Example: Let f5 = xy + xz + yz

• Factored form 1: x(y + z) + yz• Factored form 2: (x + y)z + xy• Factored form 3: (x + z)y + xz

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Algebraic Kernels and Co-kernelsAlgebraic Kernels and Co-kernels

Cube-free expressions: one that cannot be factored by a cube

Example: wx + yz is cube-free

Example: xy + xz is not cube-free since it can be factored by x

Example: xyz is not cube-free since it can be factored by its literals

Kernel and co-kernel: if an expression divided by a cube results in a cube- free quotient, then the quotient is called a kernel and the cube the corresponding co-kernel

• Level-0 kernel: a kernel that has no kernel except itself• Level-n kernel: has at least one kernel of level n-1, but no kernel of level n or greater except itself• Co-kernel level: same as its kernel’s

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Kernels and Co-kernels (Contd.)Kernels and Co-kernels (Contd.)

Example: f = uwz + uxz + vwz + vxz + yz + uv

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Rectangle CoveringRectangle Covering

Consider a sum-of-products expression f with p cubes and q distinct literals

p x q cube-literal incidence matrix: element (i,j) = 1 if jth literal used in the ith cube, and 0 otherwise

Rectangle (r,c) of matrix: set of rows r and columns c in which all entries are 1• (r1,c1) contains (r2,c2) if r1 r2 and c1 c2

Prime rectangle: a rectangle not strictly contained in another rectangle

Co-rectangle of (r,c): (r,c) where c is the complement of column subset c

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Rectangle Covering (Contd.)Rectangle Covering (Contd.)

Example: Let f = uwz + uxz + yz + uv• It has four cubes and six distinct literals• Cube-literal incidence matrix:

• Prime rectangle: ({uwz,uxz}, {u,z})– Co-kernel: uz– Co-rectangle: ({uwz,uxz}, {v,w,x,y})

» Kernel: w + x, obtained by restricting uwz + uxz to literals in {v,w,x,y}• Other prime rectangles: ({uwz,uxz,uv}, {u}), ({uwz,uxz,yz}, {z})

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A Factoring ApproachA Factoring Approach

Start with a sum-of-products and derive a factored form to reduce literal-count:• Let f = fdfq + fr

• Recursively factor fd, fq, and fr into their factored forms until these forms cannot be factored any more

• Extract any common subexpressions from the quotient and part of the remainder

Example: Let f = uwz + uxz + vwz + vxz + yz + uv• Dividing by kernel (u + v): f = (u + v)(wz + xz) + yz + uv

– fd = (u + v), fq = wz + xz, and fr = yz + uv

• fd and fr cannot be factored any further, but fq can be:

– f = (u + v)(w + x)z + yz + uv• Further factoring by extracting z:

– f = ((u + v)(w + x) + y)z + uv• Literal-count: reduced from 16 to 8

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ExtractionExtractionFor two or more expressions with common divisors: divisors can be extracted using rectangle covering

• Cube extraction• Kernel extraction

Cube extraction: Form an auxiliary expression fa as the sum of all expressions in the logic network

• Obtain a cube-literal incidence matrix for fa

• Tag each cube of each expression with an identifier for that expression• Find a prime rectangle

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Extraction ExampleExtraction ExampleExample: Let f1 = uwz + uxz + yz + uv and f2 = vz + wyz

• fa = f1 + f2 = uwz + uxz + yz + uv + vz + wyz

• Cube-literal incidence matrix:

• Prime rectangle: ({yz, wyz}, {y,z}) with corresponding cube yz• Extract yz:

• Since literal-count remains at 15 after extraction: not an attractive step in this case

x

z

y

w

v

u

f1 = uwz+uxz+yz+uv

f2 = vz+wf3 f2 = vz+wyzx

z

y

w

v

u

f3 = yz

f1 = uwz+uxz+f3+uv

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Kernel ExtractionKernel ExtractionKernel extraction: Define a kernel-cube incidence matrix

• Represent each cube in a kernel with a new variable• Represent a kernel by a set of such variables

• Denote set of kernels for expression fi by K(fi)

Example: Let f1 = uwz + uxz + yz and f2 = vw + vx + vyz

• From their cube-literal incidence matrices:

– K(f1) = {(w + x), (uw + ux + y)}

– K(f2) = {(w + x + yz)}

• Let aw = w, ax = x, ay = y, auw = uw, aux = ux, ayz = yz

– Thus, K(f1) = {{aw, ax}, {auw, aux, ay}}

– K(f2) = {{aw, ax, ayz}}

• Next, form an auxiliary function fa

– fa = awax + auwauxay + awaxayz

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Kernel-cube Incidence MatrixKernel-cube Incidence MatrixKernel-cube incidence matrix: cubes represent kernels and columns denote new variables

• Element (i,j) is 1 if jth new variable is used in the ith cube, 0 otherwise• Prime rectangle corresponds to kernel intersection• If the rows of such a rectangle correspond to different expressions, the intersection corresponds

to the subexpression that can be extracted

Example: Again, let f1 = uwz + uxz + yz and f2 = vw + vx + vyz

• Prime rectangle: ({awax, awaxayz}, {aw, ax})

• Corresponds to kernel intersection (w + x), which can be extracted• Literal-count: reduces from 15 to 12

• f1 and f2 can be factored again to reduce literal-count to 10

f2 = vf3+vyz

x

z

y

w

v

u

f3 = w+x f1 = uzf3+yz

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Decomposition and SubstitutionDecomposition and SubstitutionDecomposition: helps reduce size of a complex expression to more manageable size implementable with standard logic cells

• Assume algebraic factoring: f = fdfq + fr

• Decomposition represents fd by a: reducing f to afq + fr and a = fd

• Then decomposition can be carried out recursively on the divisor, quotient and remainder

Example: Let f = xz + yz + wx + wy + vw and consider divisor x + y

f = aw + az + vw

a = x + y• Decomposing the

quotient next:

f = ab + vw

a = x + y

b = w + z

a = x+y x

z

y

w

v

f = xz+yz+wx+wy+vw f = aw+az+vw x

z

y

w

v

a = x+y x

z

y

w

v

b = w+z

f = ab+vw

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Decomposition and Substitution (Contd.)Decomposition and Substitution (Contd.)

End product of decomposition: depends on choice of divisor• Evaluate all kernels: choose the one that reduces literal-count the most• Faster alternative: consider level-0 kernels only

Substitution: Process of replacing the divisor by corresponding variable• Divisor x + y was replaced by variable a: this was substituted into f• Thus, decomposition and substitution go hand in hand• If a divisor of f is also a divisor of g: corresponding variable can be

substituted in both f and g

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Technology MappingTechnology Mapping

Technology mapping: mapping of circuit components after technology-independent logic synthesis to logic cells in a cell library

• Possible objectives: minimize area (delay) under delay (area) constraints

Example: Cell library: INV, NAND2, NAND3 with area costs of 1, 2, 3

(c) Technology mapping with area cost 9.

yf

z

x

vw

yf

z

x

vw

yf

z

x

vw

yf

z

x

vw

(b) NAND implementation.(a) Technology-independentnetwork.

(d) Technology mapping with area cost 7.

3-input NAND

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DefinitionsDefinitions

Network covering: process of replacing subnetworks with logic cells such that the whole network is covered and desired objective is met

Matching: a cell matches a subnetwork if they are functionally equivalent

Subject graph: logic network converted into a graph with nodes derived from a set of base functions, e.g., (inverter, two-input NAND)

Pattern graph: implementation of cell library with base functions

(a) INV. (b) NAND2. (c) NAND3.

(d) NAND4_1. (e) NAND4_2.

(g) AOI22.(f) AOI21.

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Area-delay Costs of Pattern GraphsArea-delay Costs of Pattern Graphs

Network cover: ensemble of pattern graphs with minimum cost that collectively matches every node in the subject graph

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Decomposing a Network into Base Decomposing a Network into Base FunctionsFunctions

For decomposition: base functions must obviously be functionally complete

and supported by the cell library• (INV, OR2, AND2)• (INV, NAND2)• (INV, NOR2)

Trivial network cover: map each node in the subject graph to the cell that implements that base function

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Partitioning a Network into Subject Partitioning a Network into Subject GraphsGraphs

Network decomposed into base functions: subsequent technology mapping cumbersome

• Partition network into a set of connected subject graphs– Use subnetworks called leaf-DAGs

» Leaf-DAG has no internal fanout» Thus, fanout points form the boundaries of a partition

• Subject each subject graph to matching and network covering

Example:

y f1

u

x

z f2

uv

w

(a) Technology-dependentnetwork.

y f1

u

x

z f2

uv

w

(b) Decomposed network and itssubject graphs.

s1

s3

s2

f3 f3

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Obtaining MatchesObtaining Matches

Obtain all possible ways in which pattern graphs match each node in the subject graph

• Tree matching: when all pattern graphs are trees (do not have fanout even at their primary inputs)

Example: Tree matching

(a) Subject graph.

wx

y

c3

z

c1c2

c4f

Node Match

fc1

c2

c3

c4

NAND2, NAND3INV, AOI21NAND2NAND2INV

(b) Matches.

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Obtaining the Network CoverObtaining the Network Cover

Choose one match at each node in the subject graph to obtain the network cover to minimize some cost

• Optimum method: dynamic programming• Traverse subject graph from primary inputs to output and choose the best

match for each node

Example: Optimum area cost

wx

y

c3

z

c1c2

c4f

AOI21

NAND2

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Obtaining the Network Cover (Contd.)Obtaining the Network Cover (Contd.)

Example: Optimum delay cost

wx

y

c3

z

c1c2

c4f

NAND3

NAND2

INV