Post on 26-Dec-2015
Work in Progress --- Not for Publication 1
Beyond CMOS – April 12, 2010ERD – Emerging Research
Architectures Paul Franzon, paulf@ncsu.edu
Chapter Sections:I. IntroductionII. Emerging Memory Devices in Conventional
ComputingII.1 Application Drivers
– Coordinating with System Drivers and DesignII.2 Emerging Memory Structures
III. Morphic Computing
Work in Progress --- Not for Publication 2
Beyond CMOS – April 12, 2010Application Drivers
Multi-Core Computing for Personal and Departmental Use
– Multi-threading; Power consumption; Instant-on computing
Database Computing in the Cloud
– Relational and Non-relational databases
– PB scales, massive concurrency, real time indexing; Power proportionality; Power; Storage Class Memory (SCM)
Exascale Computing
– Large scale supercomputing; XB scales
– Extreme power challenge in data motion; Emerging Programming Models
– Resiliency
Mobile Personal Computing
– Multi-core and random intensive applications do not favor a simple DRAM-flash hierarchy
Application-Specific Computing
– Persistent RAM; Associativity
Work in Progress --- Not for Publication 3
Beyond CMOS – April 12, 2010Memory Hierarchy
SRAM
DRAM
DiskSSD
CPU
CacheRefill
StreamingData
STTRAM
CPU
NVRAM(s)
DRAM
Disk
Storage Class Memory
Work in Progress --- Not for Publication 4
Beyond CMOS – April 12, 2010Memory Hierarchy
Issues:
•Multi-thread support
•Cost/bit
•Power vs. Persistence vs. Endurance
– Mix and match
•Access Patterns (standards)
•Indexing support
STTRAM
CPU
NVRAM(s)
DRAM
Disk
Work in Progress --- Not for Publication 5
Beyond CMOS – April 12, 2010Unconventional Logic Architectures
Research Direction
Approach Status
Nano-FPGA Implement LUTs and/or Switchboxes using nano devices (ReRAM, NEMS)
2-3x improvement in performance/power predicted by models; 3-5x in 3D implementation.
Nano-crossbar Build very dense nano PLAs using non-volatile nano memory devices
Would benefit from a scalable two-terminal device.
Reconfigurable Computing
Implement large LUTs in NV memory and switch between them
Modeled using STTRAM. Predict 45% improvement in Energy Delay Product
Table 2. Current Research Directions for Employing emerging research memory devices to enhance logic.
Work in Progress --- Not for Publication 6
Beyond CMOS – April 12, 2010Morphic Architectures
Leveraging ERD for:
•Neuromorphic Architectures– Synaptic; Inference; Neural Network, etc.– Stochastic architectures (noise assisted)
•Cellular Automata Architectures– E.g. Image processing
(Japan ERD – T. Asai leading)