Post on 03-Jan-2016
description
Virtual WalletStructure Proposal
To create a handheld device which will save money and time through budget assistance and improve the shopping experience.
• Gates Winkler • Jordan Samuel Fei• Yin Shen
• September 28, 2009
StatusFinished• Flow Chart• Behavioral Verilog• Transistor Estimate • Floor Plan• Structure Proposal
To Do • Schematic• Structural Verilog• Layout• Testing
An
Bn
Cn-1
Gn Pn
Sn
Cn
1
1
n n n
n n n
n n n
n n n n
P A B
G A B
S P C
C P C G
Adder
FA
A0 B0
S0
Co,0FA
A1 B1
S1
Co,1FA
A28 B28
S28
Co,28FA
A29 B29
S29
Co,29……
Ci,0
Subtractor
*1
* * *1 1
n n n n
n n n n n n n
D A B C
C A B A C B C
C*n-1
An
Bn
C*n
Dn
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
clock
input…Q9 Q8 Q1 Q0
Left shift
Multiply
clock
input … Q9Q8Q1Q0
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Right shift
Divide
D
CP
Q─ Q
D Flip-flop
Comparator
Relation Comparator
A BA B
A BA BA BA B
Z
ZC Z
C
C
C Z
+B29
A29
+B28
A28
+B1
A1
+B0
A0
… ZA=B
A≥B
A≤B
C
N
Initial
Connect to SecureOne
Select Account
Input FSM
Start Shopping
Don’t input budget
Set budget to max in account
Check account
Input Budget
Not enough in account
Display error
Enough in account
Budget stored in memory
S0
S1
S2 S3
0/0
1/0
1/10/0
1/1
0/0
1/1
0/1
Next State Output
0 1 0 1
S0 S0 S1 0 0
S1 S2 S3 0 1
S2 S0 S3 0 1
S3 S3 S3 1 1
Current StateInput xn
Next StateOutput
znAn Bn An+1 Bn+1
0 00 0 0 0
1 1 1 0
1 10 0 1 0
1 1 0 1
0 10 0 0 0
1 1 0 1
1 00 1 0 1
1 1 0 1
Q
QSET
CLR
D
Q
QSET
CLR
Dclock
B
A
output
input
n n n n nAD x A B x n n n n n n nBD A B x A B x n n n n nz B x A B
B
A
card(s0)
enough(s2)
bug_sel(s1)
(s3)input
Input FSM
S0
S1
S2
S3
00/0
10/001/1
11/000/0
01/1 01/1
10/0 10/0
11/0
Initial
Over
Remove item
Go over
Remove item
Remove item
Check SRAM
Make note in subtractor
Total not over budget
Budget FSM
Don’t go over
Added another item
Make note in subtractor
Total still over budget
CheckoutCheck SecureOne Database.
Pay
Next State Output
00 01 11 10 00 01 11 10
S0 S0 S2 S3 S1 0 1 0 0
S1 φ S2 S3 S1 φ 1 0 0
S2 φ S2 φ φ φ 1 φ φ
S3 S0 φ φ S1 φ φ φ 0
Current state Input xn Next StateOutput
znAn Bn x1n x0
n An+1 Bn+1
0 0
0 0 0 0 0
0 1 0 1 1
1 1 1 1 0
1 0 1 0 0
1 0
0 0 φ φ φ
0 1 1 0 1
1 1 1 1 0
1 0 1 0 0
Current state Input xn Next stateOutput
znAn Bn x1n x0
n An+1 Bn+1
0 1
0 0 φ φ φ
0 1 0 1 1
1 1 φ φ φ
1 0 φ φ φ
1 1
0 0 0 0 0
0 1 φ φ φ
1 1 φ φ φ
1 0 1 0 0
1n n n nAD x A B
0 1 0n n n n nBD A x x x
1 0n n nz x x
Q
QSET
CLR
D
Q
QSET
CLR
D
B
A
clock
outputinputx1
x0
over1(s0)
input(x1)
B
A
input(x0)
(s2)
remove1(s1)
judge1(s3)
over0(s0)
(s2)
remove0(s1)
judge0(s3)
Discount FSM
Initial
Check Database
Check SRAM
Get nothing
Scanned item
discountMake note in subtractor
No discount
S0
S1 S2
0/0
0/0
1/0 0/0
1/1
Next State Output
0 1 0 1
S0 S0 S1 0 0
S1 S0 S2 0 0
S2 S0 φ 1 φ
Current StateInput xn
Next StateOutput
znAn Bn An+1 Bn+1
0 00 0 0 0
1 0 1 0
0 10 0 0 0
1 1 1 0
1 10 0 0 1
φ φ φ φ
Q
QSET
CLR
D
Q
QSET
CLR
D
B
A
output
input
clock
n n nAD B xn nBD xn nz A
B
A
discount(s1)
(s2)
input
get(s0)
Discount FSM
Battery FSM
S0
S1 S2
0/1
0/0
1/0 1/1
1/0
0/0
Good Battery
Low Battery
Battery Good
Battery Low
Battery Low
Battery Charging
When Plugged in Battery Starts Charging and returns to the correct State when unplugged
Next State Output
0 1 0 1
S0 S0 S1 1 0
S1 S1 S2 0 0
S2 S2 S0 0 1
Current StateInput xn
Next StateOutput
znAn Bn An+1 Bn+1
0 00 0 0 1
1 0 1 0
0 10 0 1 0
1 1 1 0
1 10 1 1 0
1 0 0 1
Q
QSET
CLR
D
Q
QSET
CLR
D
B
A
clock
output
input
n n n n n nAD A x A B x n n n n nBD B x A x n n n n nz B x A x
B
A
charging(s1)
charged(s2)
input
low(s0)
Battery FSM
Controllerin_state Ain_state B
budg_state A
budg_state B
disc_state A
disc_state B
over warning
price
add_price sub_price
demux
Controller
Transistor Count (new)Block Transistor
SRAM 5000
Adder 720 (500)
Subtractor 780 (500)
Multiply 260 (500)
Divide 260 (500)
Comparator 900 (500)
Logic 600 (2000)
Budget Register 360 (120)
Total Register 360 (120)
Total 9240(9740)