Post on 08-May-2020
VHDL Review
Last updated 7/12/19
2 © tjEE 3921
Basic Logic
• Buffers
In OutIn Out
0 0
1 1
In Tri OUT
0 0 1
0 1 Z
1 0 0
1 1 Z
In Out
Tri
In OutIn Out
0 1
1 0
notA ~A A’
non-Inverting
Inverting
Tri-State
In Tri OUT
A 0 ~A
X 1 Z
3 © tjEE 3921
Basic Logic
• Simple Gates
A
BOut
A
BOut
A
BOut
A
BOut
A
BOut
A
BOut
AND/NAND
OR/NOR
XOR/XNOR
A B AND OUT
NAND OUT
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
A and B A nand BA ^ B (A ^ B)’A & B A & BAB A*B
A B OR OUT
NOR OUT
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0
A or B A nor BA v B (A v B)’A | B A | BA + B
A B XOROUT
XNOR OUT
0 0 0 1
0 1 1 0
1 0 1 0
1 1 0 1
A xor B A xnor BA ⊕ B (A ⊕ B)’
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Basic Logic
• Switches
A BSwitch
Ctl State
0 X
1 A = B
Ctl
A B
Ctl
Ctl
Switch
Ctl State
0 X
1 A = B
In Out
Tri
Tri
Tristate
In Tri Tribar
Out
A 0 0 U
A 0 1 A’
A 1 0 Z
A 1 1 U
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Basic Logic
• Coder / Decoder
4 to 2
b0
b1
b2
b3
out 12 to 4
b0
b1
b2
b3
in 1
out 0 in 0
b3 b2 b1 b0out
1out
0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
In 1
In 2
b3 b2 b1 b0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
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Basic Logic
• Multiplexer/ Demultiplexer
s1 s0
b0
b1
b2
b3
out
s1 s0
b0
b1
b2
b3
in
s1 S0 out
0 0 b0
0 1 b1
1 0 b2
1 1 b3
s1 s0 b3 b2 b1 b0
0 0 0 0 0 in
0 1 0 0 in 0
1 0 0 in 0 0
1 1 in 0 0 0
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Basic Logic
• Latches
R Q
QBS
R
S
Q
QB
SB
RB
Q
QB
SB Q
QBRB
S R Q QB
0 0 No change No change
0 1 0 1
1 0 1 0
1 1 0 0
SB RB Q QB
0 0 1 1
0 1 1 0
1 0 0 1
1 1 No change No change
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Basic Logic
• Flip-Flops
• Edge Triggered D Flip-Flop• Outputs depend on the state of the inputs at the rising clock edge
• Some have asynchronous set or reset inputs
SetResetBar
D Q QB
0 1 0 0 1
0 1 1 1 0
1 1 x 1 0
0 0 x 0 1
D Q
QB
RSTB
SET
D at the rising clock edge
9 © tjEE 3921
Basic Logic
• Flip-Flops
T Q QB
0 QOLD QBOLD
1 QBOLD QOLD
T Q
QBT at the rising clock edge
R S Q QB
0 0 QOLD QBOLD
0 1 1 0
1 0 0 1
1 1 N/A N/A
S,R at the rising clock edge
S Q
QB R
J K Q QB
0 0 QOLD QBOLD
0 1 0 1
1 0 1 0
1 1 QBOLD QOLD
J,K at the rising clock edge
J Q
QB K
10 © tjEE 3921
Basic Logic
• Delays• tpd = propagation delay• delay from input to valid output (max delay)
• tcd = contamination delay• delay from input to first movement on output (min delay)
A
Y
Time
A Y
tpd
tcd
src: Harris & Harris
11 © tjEE 3921
Basic Logic
• Physical world• Voltage levels• System/Circuit dependent
• Ideal:
3.3v System ‘1’ = 3.3v ‘0’ = 0.0v
1.8v System ‘1’ = 1.8v ‘0’ = 0.0v
1.2v System ‘1’ = 1.2v ‘0’ = 0.0v
• Real world:
3.3v System 3.3v
0.0v
2.4vVOH
0.5vVOL
0.8vVIL
2.0 vVIH
12 © tjEE 3921
Basic Logic
• Clock Systems
T (period) timeHigh Low
F (frequency) = 1/T Duty Cycle = High / T
50MHz <-> 20nS High = 10ns, Low = 10ns
25% duty cycle, 12.5Mhz
75% duty cycle, 12.5MHz
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VHDL Basics
• VHDL
• VHSIC Hardware Description Language
• Very High Speed Integrated Circuit
14 © tjEE 3921
VHDL Basics
• Concurrent vs Sequential Logic in HDL• Concurrent activities are happening all the time (in
parallel)• Assignment: <=
• with-select
• when-else
z <= (b or c) when (d = ‘0’) else (e and f); -- z can change if any value
-- changes, immediately
15 © tjEE 3921
VHDL Basics
• Concurrent vs Sequential Logic in HDL• Sequential activities only happen in certain situations• Rising edge of clock
• Sequential activities are identified by placing them in a “process” block
• Process blocks are only executed when a signal in the blocks “sensitivity list” changes
• The code in a process block is evaluated sequentially but signals are ONLY updated at the end of the process block
• Process blocks themselves are concurrent activities
16 © tjEE 3921
VHDL Basics
• Process block format
process (sensitivity list)begin
actionsend process;
label process (sensitivity list)begin
actionsend process;
17 © tjEE 3921
VHDL Basics
• Basic VHDL file
EntityDescription(External Signals)
------------------------------ basic_vhdl.vhdl-- Created: 7/16/18-- By: johnsontimoj-- For: EE3921--
-- File Overview ------- This file demonstrates basic VHDL file structure
-- File Details --------------------------------
-- Behavioral Architecture Definitionarchitecture behavioral of basic_vhdl is
signal e: std_logic;signal f: std_logic;signal g: std_logic;signal t: unsigned(N-1 downto 0);signal u: signed(N-1 downto 0);
Begin
e <= i_a and i_b;f <= i_c nor i_a;g <= e xor f;o_x <= g and not i_p(3);
t <= unsigned(i_p xor i_q);u <= signed("11" & i_a & t(4) & i_r(3 downto 2) & i_a & g);o_y <= (7 => '1' , 4 => u(5), 1 => i_a , 5 => t(4) , others => '1' ); -- array assignment
end architecture;
-- Library inclusionslibrary IEEE;use ieee.std_logic_1164.all;use ieee.numeric_std.all;
-- Entity definitionentity basic_vhdl is
generic( N: positive := 8);port( i_a: in std_logic;
i_b: in std_logic;i_c : in std_logic;i_p: in std_logic_vector(N-1 downto 0);i_q: in std_logic_vector(N-1 downto 0);i_r : in std_logic_vector(N-1 downto 0);o_x: out std_logic;o_y: out std_logic_vector(N-1 downto 0)
);end entity;
ArchitecturalDefinition
Internalsignals
HeaderInformation
LibraryInclusions
Entity
Architecture
Generic
Ports
18 © tjEE 3921
• Basic VHDL file
VHDL Basics
e <= i_a and i_b;f <= i_c nor i_a;g <= e xor f;o_x <= g and not i_p(3);
t <= unsigned(i_p xor i_q);u <= signed("11" & i_a & t(4) & i_r(3 downto 2) & i_a & g);o_y <= (7 => '1' , 4 => u(5), 1 => i_a , 5 => t(4) , others => '1' );
port( i_a: in std_logic;i_b: in std_logic;i_c: in std_logic;i_p: in std_logic_vector(N-1 downto 0);i_q: in std_logic_vector(N-1 downto 0);i_r : in std_logic_vector(N-1 downto 0);o_x: out std_logic;o_y: out std_logic_vector(N-1 downto 0)
);
19 © tjEE 3921
VHDL Basics
• Basic VHDL – Structural file
• Full Adder
------------------------------------- full_adder.vhdl---- by: johnsontimoj---- created: 7/5/2017---- version: 0.0-------------------------------------------------------------------------- 1 bit full adder---- inputs: a, b, cin---- outputs: s, cout------------------------------------
library IEEE; use ieee.std_logic_1164.all;
entity full_adder isport( i_a: in std_logic;
i_b: in std_logic;i_cin: in std_logic;o_s: out std_logic;o_cout: out std_logic
);end entity;
architecture behavioral of full_adder is
signal p: std_logic;signal g: std_logic;
begin
p <= i_a xor i_b;g <= i_a and i_b;
o_s <= p xor i_cin;o_cout <= g or (p and i_cin);
end;
20 © tjEE 3921
VHDL Basics
• Basic VHDL – Structural file
• Full Adder
21 © tjEE 3921
VHDL Basics
• Basic VHDL – Structural file------------------------------------- adder_4bit.vhdl---- by: tj---- created: 7/5/2017---- version: 0.0---------------------------------------- 4 bit adder to show cell instantiation---- inputs: - a, b, cin---- outputs: - sum, cout------------------------------------library IEEE;use ieee.std_logic_1164.all;
entity adder_4bit isport( i_A: in std_logic_vector(3 downto 0);
i_B: in std_logic_vector(3 downto 0);i_CIN: in std_logic;o_SUM: out std_logic_vector(3 downto 0);o_COUT: out std_logic
);end entity;
architecture structural of adder_4bit is
------------------------------------ 1 bit full adder prototype----------------------------------component full_adder is
port( i_a: in std_logic;i_b: in std_logic;i_cin: in std_logic;o_s: out std_logic;o_cout: out std_logic
);end component;------------------------------------- intermediate carrys mapped to co-- with 1st stage Cout mapped to co(0) and 4th stage cout mapped to co(3)-------------------------------------signal co: STD_LOGIC_VECTOR(3 downto 0); -- intermediate carrys
-- no vector interpretation
ComponentPrototype
begin
add_0: full_adder port map( i_a => i_A(0), i_b => i_B(0), i_cin => i_CIN, o_s => o_SUM(0), o_cout => co(0));
add_1: full_adder port map( i_a => i_A(1), i_b => i_B(1), i_cin => co(0), o_s => o_SUM(1), o_cout => co(1));
add_2: full_adder port map( i_a => i_A(2), i_b => i_B(2), i_cin => co(1), o_s => o_SUM(2), o_cout => co(2));
add_3: full_adder port map( i_a => i_A(3), i_b => i_B(3), i_cin => co(2), o_s => o_SUM(3), o_cout => co(3));
o_COUT <= co(3);
end architecture;
Instantiations
ExplicitMapping
Top LevelEntity
22 © tjEE 3921
VHDL Basics
• Basic VHDL – Structural file
23 © tjEE 3921
VHDL Basics
• VHDL – Selection• with-select• Choose a value when a certain situation exists
with decision_signal select result_signal <= -- exhaustive list
result_value when decision_value,
result_value when decision_value,
result_value when decision_value,
result_value when decision_value;
Limitation: Only one result signal
24 © tjEE 3921
VHDL Basics
• VHDL – Selection• with-select
with inA select outA <= “0100” when “01”,“0010” when “10”,“0001” when “11”,“1010” when “00”,“0000” when others;
Exhaustive List
with inA select outA <= “0100” when “01”,“0010” when “10”,“0000” when others;
Partial List
with inA select outA <= “0100” when “01”,“0010” when “10”,“0001” when (“11” or “00”),“0000” when others;
Partially Common Result
with (inA and inB) select outA <=“0100” when “01”,“0010” when “10”,“0001” when “00”,“0000” when others;
Complex Selection
25 © tjEE 3921
VHDL Basics
• VHDL – Selection• with-select
------------------------------------------ with_select.vhdl---- created 7/5/2018-- tj---- rev 0-------------------------------------------- with-select example---------------------------------------------- Inputs: C-- Outputs: V------------------------------------------library ieee;use ieee.std_logic_1164.all;
entity with_select isport (
i_C: in std_logic_vector(3 downto 0); o_V: out std_logic_vector(3 downto 0)
);end entity;
architecture behavioral of with_select is
begin --------------------------------------------- Code to show mux-------------------------------------------
with i_C select o_V <="0001" when "0000","0010" when "0001","0011" when "0010","0100" when "0011","0101" when "0100","0110" when "0101","0111" when "0110","1000" when "0111","1001" when "1000","0000" when others;
end behavioral;
26 © tjEE 3921
• VHDL – Selection• with-select
VHDL Basics
0000 0001 0101 01010000 0000 0110 01100000 0000 0111 10000000 0001 1000 0000
00
00
00
01
01
01
01
01
00
00
00
00
01
10
01
10
00
00
00
00
01
11
10
00
00
00
00
01
10
00
00
00
Mux3
Mux0
i_C = 0000
i_C = 1111
o_Vi_C = 0111
27 © tjEE 3921
VHDL Basics
• VHDL – Selection• when-else• Choose a value when a certain situation exists
result_signal <= result_value when decision_signal = decision_value else
result_value when decision_signal = decision_value else
result_value when decision_signal = decision_value else
result_value;
Limitation: Only one result signal
28 © tjEE 3921
VHDL Basics
• VHDL – Selection• when-else
outA <= “1000” when inA = “00” else“0100” when inA = “01” else“0010” when inA = “10” else“0010” when inA = “11” else“0001”;
Exhaustive List
outA <= “1000” when inA = “00” else“0100” when inA = “01” else“0001”;
Partial List
outA <= “1000” when inA = “00” else“0100” when inA = “01” else“0010” when inA = (“10” or “11”) else“0001”;
Partially Common Result
outA <= “1000” when (inA or inB) = “00” else“0100” when (inA or inB) = “01” else“0010” when (inA or inB) = “10” else“0001”;
Complex Selection
29 © tjEE 3921
VHDL Basics
• VHDL – Selection• when-else
------------------------------------------ when_else.vhdl---- created 7/5/2018-- tj---- rev 0-------------------------------------------- when-else example---------------------------------------------- Inputs: C-- Outputs: V------------------------------------------library ieee;use ieee.std_logic_1164.all;
entity when_else isport (
i_C: in std_logic_vector(3 downto 0); o_V: out std_logic_vector(3 downto 0)
);end entity;
architecture behavioral of when_else is
begin
o_V <= "0001" when i_C = "0000" else"0010" when i_C = "0001" else"0011" when i_C = "0010" else"0100" when i_C = "0011" else"0101" when i_C = "0100" else"0110" when i_C = "0101" else"0111" when i_C = "0110" else"1000" when i_C = "0111" else"1001" when i_C = "1000" else"0000";
end behavioral;
30 © tjEE 3921
VHDL Basics
• VHDL – Selection• when-else
31 © tjEE 3921
VHDL Basics
• VHDL – Selection• if-else• Choose a value when a certain situation exists
if (decision_signal = decision_value_X) thenresult_signal_1 <= result_value_1;
result_signal_2 <= result_value_2;
result_signal_3 <= result_value_3;elsif (decision_signal = decision_value_Y) then
result_signal_1 <= result_value_1a;
result_signal_2 <= result_value_2b;result_signal_3 <= result_value_3c;
else
result_signal_1 <= result_value_a;result_signal_2 <= result_value_b;
result_signal_3 <= result_value_c;
end if;
Limitation: Must be used in a process
Typically use the same decision signalException – creating registers (Flip-Flops)
32 © tjEE 3921
VHDL Basics
• VHDL – Selection• if-else
if(inA = "00") thenoutW <= "1000";
elsif(inA = "01") thenoutW <= "0100";
elsif(inA = "10") thenoutW <= "0010";
elsif(inA = "11") thenoutW <= "0011";
elseoutW <= "0000";
end if;
Exhaustive List Partial List Partially Common Result
Complex Selection
if(inA = "00") thenoutX <= "1000";
elsif(inA = "01") thenoutX <= "0100";
elseoutX <= "0000";
end if;
if(inA = "00") thenoutY <= "1000";
elsif(inA = "01") thenoutY <= "0100";
elsif((inA = "10") or (inA = "11")) thenoutY <= "0110";
elseoutX <= "0000";
end if;
if((inA or inB) = "00") thenoutZ <= "1000";
elsif((inA or inB) = "01") thenoutZ <= "0100";
elseoutZ <= "0000";
end if;
33 © tjEE 3921
VHDL Basics
• VHDL – Selection• if-else
------------------------------------------ if_else.vhdl---- created 7/5/2018-- tj---- rev 0-------------------------------------------- if-else example---------------------------------------------- Inputs: C-- Outputs: V------------------------------------------library ieee;use ieee.std_logic_1164.all;
entity if_else isport (
i_C: in std_logic_vector(3 downto 0); o_V: out std_logic_vector(3 downto 0)
);end entity;
architecture behavioral of if_else is
begin process(i_C)begin
if(i_C = "0000") theno_V <= "0001";
elsif(i_C = "0001") theno_V <= "0010";
elsif(i_C = "0010") theno_V <= "0011";
elsif(i_C = "0011") theno_V <= "0100";
elsif(i_C = "0100") theno_V <= "0101";
elsif(i_C = "0101") theno_V <= "0110";
elsif(i_C = "0110") theno_V <= "0111";
elsif(i_C = "0111") theno_V <= "1000";
elsif(i_C = "1000") theno_V <= "1001";
elseo_V <= "0000";
end if;end process;
end behavioral;
34 © tjEE 3921
VHDL Basics
• VHDL – Selection• if-else
35 © tjEE 3921
VHDL Basics
• VHDL – Selection• case• Choose a value when a certain situation exists
case decision_signal iswhen decision_value_X => result_signal_1 <= result_value_1;
result_signal_2 <= result_value_2;result_signal_3 <= result_value_3;
when decision_value_Y => result_signal_1 <= result_value_1a;result_signal_2 <= result_value_2b;result_signal_3 <= result_value_3c;
when others => result_signal_1 <= result_value_a;result_signal_2 <= result_value_b;result_signal_3 <= result_value_c;
end case;
Limitations: Must be used in a processOnly one decision signal
36 © tjEE 3921
VHDL Basics
• VHDL – Selection• case
case inA iswhen "00" => outW <= "1000";when "01" => outW <= "0100";when "10" => outW <= "0010";when "11" => outW <= "0011";when others => outW <= "0000";
end case;
Exhaustive List Partial List
Partially Common Result Complex Selection
case inA iswhen "00" => outY <= "1000";when "01" => outY <= "0100";when ("10“ or “11”) => outY <= "0010";when others => outY <= "0000";
end case;
case inA iswhen "00" => outX <= "1000";when "01" => outX <= "0100";when others => outX <= "0000";
end case;
case (inA or inB) iswhen "00" => outW <= "1000";when "01" => outW <= "0100";when "10" => outW <= "0010";when "11" => outW <= "0011";when others => outW <= "0000";
end case;
37 © tjEE 3921
VHDL Basics
• VHDL – Selection• case
------------------------------------------ case_ex.vhdl---- created 7/5/2018-- tj---- rev 0-------------------------------------------- case example---------------------------------------------- Inputs: C-- Outputs: V------------------------------------------library ieee;use ieee.std_logic_1164.all;
entity case_ex isport (
i_C: in std_logic_vector(3 downto 0); o_V: out std_logic_vector(3 downto 0)
);end entity;
architecture behavioral of case_ex is
begin process(all)begin
case i_C iswhen "0000" => o_V <= "0001";when "0001" => o_V <= "0010";when "0010" => o_V <= "0011";when "0011" => o_V <= "0100";when "0100" => o_V <= "0101";when "0101" => o_V <= "0110";when "0110" => o_V <= "0111";when "0111" => o_V <= "1000";when "1000" => o_V <= "1001";when others => o_V <= "0000";
end case;end process;
end behavioral;
38 © tjEE 3921
• VHDL – Selection• case
VHDL Basics
0000 0001 0101 01010000 0000 0110 01100000 0000 0111 10000000 0001 1000 0000
00
00
00
01
01
01
01
01
00
00
00
00
01
10
01
10
00
00
00
00
01
11
10
00
00
00
00
01
10
00
00
00
Mux3
Mux0
i_C = 0000
i_C = 1111
o_Vi_C = 0111
when "0110" => o_V <= "0111";when "0111" => o_V <= "1000";
39 © tjEE 3921
VHDL Basics
process (clk)begin
if(rising_edge(clk)) then q <= d;
end if;end process;
• Registers (Flip-Flops) are recognized by a pre-defined VHDL template
process (clk)begin
if(clk’event and clk = 1) then q <= d;
end if;end process;
2008 release
process (clock signal)begin
if(clock edge detection) then actions
end if;end process;
note:- here the else is not required
because the synthesizer recognizes the edge detection
- you can include an else for clarity
40 © tjEE 3921
VHDL Basics
library ieee;use ieee.std_logic_1164.all;
entity dff_a isport(
i_clk: in std_logic;i_rstb: in std_logic;i_D : in std_logic;
o_Q : out std_logic);
end entity;
architecture behavioral of dff_a isbegin
process (i_clk, i_rstb)begin
if (i_rstb = '0') theno_Q <= ‘0’;
elsif (rising_edge(i_clk)) theno_Q <= i_D;
end if;end process;
end architecture;
• D-FF w/ asynchronous rstb
Most of our designs will use DFFs with an asynchronous reset
Note addition of rstb to the sensitivity list
Data Path designs will use DFFs with no reset
41 © tjEE 3921
VHDL Basics
• N bit register entity reg_n_bit is
generic(N: integer := 8
);port (
i_D : in std_logic_vector((N - 1) downto 0); i_clk : in std_logic; i_rstb: in std_logic;
o_Q: out std_logic_vector((N - 1) downto 0));
end entity;
architecture behavioral of reg_n_bit isbegin
process(i_clk, i_rstb)begin
if (i_rstb = '0') theno_Q <= (others => '0');
elsif (rising_edge(i_clk)) theno_Q <= i_D;
end if;end process;
end behavioral;-----------------------------
42 © tjEE 3921
VHDL Basics
• Warning – Warning – Warning
• Most (maybe all) of the times you do not complete an
if-else with an else a latch will be created
• All cases must be covered
• We do not want latches - EVER