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Fall, 2010 RF CMOS Tranceiver Design 1/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
Tutorial-2 Low Noise Amplifier (LNA) Design
Written By: Rashad.M.Ramzan
rashad.ramzan@nu.edu.pk
Objective:
Low noise amplifiers are one of the basic building blocks of any communication system. The purpose of the LNA is to amplify the received signal to acceptable levels with minimum self generated additional noise. Gain, NF, non-linearity and impedance matching are four most important parameters in LNA design. The objective of this tutorial is to outline the basic tradeoffs between different amplifying topologies w.r.t gain, NF and impedance matching. After this comparison it is concluded that inductor degenerated common source topology gives the best performance to meet the gain, NF, and impedance matching goals with minimum power consumption in case of narrow band designs.
Goals:
After this tutorial, students should be able to
Calculate the gain, input impedance and NF of common gate, common source, and shunt feedback amplifiers.
Understand the basic equations and tradeoff between different LNA topologies.
Perform the calculation for inductor degenerated common source topology and understand the tradeoff between the gain, NF, and impedance matching.
A supplement tutorial LNA lab is also part of this course which takes the circuit from Problem-2.8 and guides through different analysis to design and practical LNA.
Fall, 2010 RF CMOS Tranceiver Design 2/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
gmVgs Cgs+Cgb
S
+ -
Vgs Iin
Io Iin G Cgd
D Io
Vgs + -
Problem-2.1(Tutorial) T is single figure of merit for high frequency transistors. This is defined as frequency at which current gain is extrapolated to fall to unity. Although the dc gate current of an MOS transistor is essentially zero, the high- frequency behavior of the transistor is controlled by the capacitive elements in the small- signal model, which cause the gate current to increase as frequency increases.
a) Derive the expression for T.
b) For RF design we always use minimum length transistors. Why?
Solution:
a).
Vsb = Vds = 0
So gmb, ro, Csb, Cdb have no effect on calculations. (This is drawback of t definition)
gsgdgbgsi VCCCji )(
gsmi Vgi
gdgbgs
m
in
o
CCCj
g
i
i
According to definition 1in
o
i
iat T
gdgbgs
mT
CCC
g
Cgb and Cgd are small compared to Cgs
So,
gs
m
gdgs
mT
C
g
CC
g
-----------------------(1)
b). 22
Tgsoxo
D VVL
WCI
Tgsoxo
gs
Dm VV
L
WC
V
Ig
-----------------------(2)
Fall, 2010 RF CMOS Tranceiver Design 3/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
And WLCC ogs -----------------------(3)
Put (2) & (3) in (1)
2... L
VV
LWCL
VVWC
C
g tgso
ox
tgsoxo
gs
mT
2L
VV tgso
T
This means that 2
1
LT so that’s why minimum L is preferred. But this approximation holds
for long channel devices for short channel L
T
1 instead of
2
1
L.
Problem-2.2(Tutorial)
NMOS transistor is racing horse in LNA design arena due to its higher mobility compared to PMOS transistors. Calculate the IP3 of NMOS CS amplifier shown below. Assume that NMOS transistor is in saturation.
a) Consider simplified square law model. (HW)
2( )2
nD GS T
KI V V
b) Consider the short channel effects as (Tutorial)
2
1
( )
2 1 ( )
,
0.2 0.1
n GS TD
GS T
GS T
K V VI
V V
Velocity Saturation Mobility Degradation
V V V and V
c) What conclusion can be drawn from part b) about the bias current and transconductance of transistor for higher IP3?
Solution:
Fall, 2010 RF CMOS Tranceiver Design 4/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
VDD
RL
VGS X(t) NMOS
DC-bias
a). Home work Ans: 3IP
b). From Razavi
)()()()( 33
221 txtxtxxy ---------------(1)
3
121
3
43coscos)(
IPtAtAtx
)(12
2
TGS
TGSnD
VV
VVKI
Here we assume that small signal x(t) over-rides (VGS – VT).
So,
))((1
)(
2
2
txVV
txVVKI
TGS
TGSnD
& VVV TGS --------------- Large signal
X(t) --------------- Small signal
1))((
)(
2
2
Vtx
VtxKI n
D
Vtx
VtxRKVRIV Ln
oLDo
)(1
)(
2
2
put K
RK Ln 2
1 So Vxx )( is also small 2
11
1 x
x
2
)(1
)(1
1 Vtx
Vtx
2
)(1)(
2 VtxVtxKVo
2
)()(32 K
VtxVtxKVo
)(2
)(2
3)(
2
32
232232 tx
KtxV
KKtxV
KVKV
KVKVo
---------------(2)
Small signal components
)(2
)(2
3)(
2
32 322 tx
KtxV
KKtxV
KVKVo
---------------(3)
Fall, 2010 RF CMOS Tranceiver Design 5/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
Comparing (1) & (3)
21
2
32 V
KVK
, V
KK
2
32
,
23
K
2
2
3
1 32
3
8
2
2
32
3
4
3
43 V
V
K
VKvKIP
VVIP
3
162
3
83
TGS VVVIP
3
16
3
163 ---------------(4)
Put VV 2.0 , 1.0
VoltsIP 27.31.0
2.0
3
163
dBmmWdBmIP 20150
1.
2
27.3log10)(3
2
VVVI
g
TGSD
m
22
m
D
g
IIP
3
323 Doxnm I
L
WCg
c).
- To increase IIP3 ID (high power) or gm (high noise)
- gm also depends upon ID, so when ID gm but at that rate DI
- When W increases gm for same ID (Power consumption) so this decreases IP3
- The above observations are for long-channel. But for short channel TGS VV4 then
ID any how.
Problem-2.3 (Tutorial)
It is preferred in current RF designs that the input of LNA be matched to 50 Ω (Razavi, Pg168). The easiest way is to shunt the gate with a resistor of 50 Ω.
a) Calculate the gain, input impedance and NF in absence of gate noise. Assume that Rsh=RL for NF derivation.
b) What are the disadvantage of shunt resistor with reference to gain and NF?
As 1 23 V can be ignored.
22
TGSoxo
D VVL
WCI
VVVI
g
VVL
WC
V
Ig
TGSD
m
TGSoxn
GS
Dm
22
This is just an approximation with ID & gm
Fall, 2010 RF CMOS Tranceiver Design 6/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
gmVgs
S
D Vout
RL di2
RL is noiseless
G
Rsh
RshnV ,2
RsnV ,2
Rs
VDD
RL
Rsh
Vin Vout
Zin
Rs
(Baising not shown)
Solution:
a). (Please read assumption in problem statement carefully)
sourceinputtoduenoiseOutput
powernoiseoutputTotalF
fKTRV sRsm 4,2
LmGateRgGain
fKTRV shRshm 4,2
shs
shLm
RR
RRgA for Rsh = Rs
fgKTi md 42
2L
m
RgA
Using superposition, considering one at a time and shorting / opening other sources.
2
22,
2,
2
shs
shLmRsnRson
RR
RRgVV
2
22,
2,
2
shs
sLmRshnRshon
RR
RRgVV
Fall, 2010 RF CMOS Tranceiver Design 7/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
Lddno RiV 22,
2
Rson
doRshon
Rson
dnoRshonRson
V
VV
V
VVVF
,2
,2
,2
,2
,2
,2
,2
1
2222
2
2
222
2
222
4
4
4
4
1
shs
sLm
S
Lm
shs
sLm
s
shs
shLm
sh
RR
RRgfKTR
RfgKT
RR
RRgfKTR
RR
RRgfKTR
F
In case of impedance match Rs = Rsh
smLm
s
mL
s
Lsm
s
mL
RgRgR
gR
R
RRgR
gRF
42
4
2
4
1122
2
2
222
2
b).
- Poor Noise Figure
- Input signal attenuated by voltage divider
- Rsh adds extra noise.
- At high frequency, shunt L is needed to tune out Cgs
- Reduced gain
Problem-2.4 (Tutorial)
Another approach to get 50 Ω input impedance match is shunt feedback amplifier shown below.
a) Calculate the gain, input impedance and NF in absence on gate noise. Neglect gate drain
and gate to bulk and gate to source capacitance.
b) What are the disadvantage of shunt feedback amplifier with reference to gain and NF?
Fall, 2010 RF CMOS Tranceiver Design 8/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
gmVgs
Vout
RL nDI 2
(Equivalent noise model ignoring gate noise), RL is noiseless
Rs
RsnV ,2
RFnV ,2
RF
VDD
RL
Vout
Zin
Rs
(Baising not shown)
RF
Vin
gmVgs
Vout
RL
Rs RF
Vgs
iin
Vin
RL
Vout
Iin Rs
RF
Iin
Solution:
fKTRVfgKTI SRSmnD 4,4 22
sourceinputtoduepowernoiseOutput
powernoiseinputTotal
VA
VNF
RStotv
outn
2,
2
,2
Here Av,tot = Gain from Vin to Vout
Again using superposition theorem
RStotv
outDnoutRFnoutRSn
RStotv
outn
VA
VVV
VA
VNF
2,
2
,2
,2
,2
2,
2
,2
Gain Calculation
outFSinin VRRiV
Lgsminout RVgiV
oFings VRiV
LSmLFS
LmL
in
outtotv
RRgRRR
RgR
V
VA
1,
If RF>>RS & gmRF>>1
Lm
F
SmL
F
S
Lmtotv Rg
R
RgR
R
R
RgA
11
,
Lmtotv RgA ,
Also
Lm
LFin
Rg
RRZ
1
By ignoring Cgs, we have considered real part only.
Fall, 2010 RF CMOS Tranceiver Design 9/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
gmVgs
outRFV ,2
RL
Rs RF
Vgs
i RFV 2
gmVgs
outnDV ,2
RL
Rs RF
Vgs
i
DnI ,2
For source resistance
nRStotvoutnRS VAV 2,
2,
2 ---------------(1)
For feedback resistance
outRFRFFSgs VViRiRV ,
gsmLoutRF VgiRV ,
Sm
F
LRF
smL
FSRFoutRF Rg
R
RV
RgR
RRVV
1
11
1,
2
,2
,,2 1
Sm
F
LRFnoutRFn Rg
R
RVV ---------------(2)
Similarly
0,,
FS
outnD
gsmnD
L
outnD
RR
VVgI
R
V
FS
outnD
SgsRR
VRV
,
LnD
FS
Sm
FSL
Dn
outnD RI
RR
Rg
RRR
IV
11
,
,
So,
22,
2LnDoutnD RIV ---------------(3)
Combaining (1) (2) & (3)
Fall, 2010 RF CMOS Tranceiver Design 10/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
RSntotv
LnD
RSntotv
Sm
F
LRFn
VA
RI
VA
RgR
RV
NF,
2,
2
22
,2
,2
2
,2 1
1
Lmtotv RgA , , fKTRV SRSn 4,2
, FRFM KTRV 4,2 & mnD gKTI 42
SmSmF
S
RgRgR
RNF
2
111
b).
NF gmRS & RF usually 50SR
- Better performance than CS amplifier
- RF induces noise
- At f need shunt inductor to tune out Cgs
- Broadband Amp @ Lower frequency
- To make NF RF > RS gmRS >> 1
Problem-2.5 (HW)
Common gate amplifier also offers 50 Ω input impedance match and solves the input matching problem.
c) Calculate the gain, input impedance and NF in absence on gate noise. Neglect gate drain
and gate to bulk and gate to source capacitance.
a) What are the disadvantage of common gate amplifier with reference to gain and NF?
Problem-2.6 (Tutorial)
The disadvantages of three types of amplifiers in Problem-3, 4 & 5 can be circumvented by using source degenerated LNA shown below.
Fall, 2010 RF CMOS Tranceiver Design 11/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
VDD
RL
VS Vout Rs
(Baising not shown)
Ls
Lg
VS Rs
Ls
Lg iin Vout io
gmVgs
Vin Vgs
Zin
a) Calculate the input impedance. This inductor source degenerated amplifier presents a
noiseless resistance for 50Ω for input power match. How we can cancel the imaginary part of complex input impedance so that the LNA presents 50Ω real input resistance at input port.
b) Calculate the NF in absence on gate noise. Neglect gate drain and gate to bulk and gate to source capacitance.
c) Cgd bridges the input and output ports. The reverse isolation of this LNA is very poor. Why reverse isolation is important? Suggest the modification to improve reverse isolation.
Solution:
a).
From model above we can write
soinsginin Ljicj
iLjLjiV
1 ---------------(1)
gs
inmgsmoCj
igVgi
1 ---------------(2)
Substituting (2) in (1)
gs
sm
gs
sgininC
Lg
CjLLjiV
1
Fall, 2010 RF CMOS Tranceiver Design 12/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
Vin
Rs Lg + Ls
gs
sm
C
Lg
Zin Vgs
Cgs
Reference: For series RLC Circuit R L
C VC Vin
RCR
L
C
L
RQ
o
os
11
And inSC VQV
For problem (1)
gs
mT
C
g Unity gain frequency
for current
gs
sm
gs
sg
in
inin
C
Lg
CjLLj
i
VZ
1
gs
sm
gs
sginC
Lg
CjLLjZ
1
For matching Lg + Ls are canceled out by Cgs. So at frequency of interest
gssg
o
gso
sgoCLLC
LL
11 2
And s
gs
mS L
C
gR 50
Notes:
a). Ls is typically small and may be realized by bond wire.
b). Lg can be implemented by spiral/external inductor.
b). From part a)
gs
sm
gs
sginC
Lg
CjLLjZ
1
We can draw this circuit as
Here
STS
sgo
gs
SmS
sgo
inLWR
LL
C
LgR
LLQ
gs
mT
C
g
gs
gs
SmSo
in
CC
LgR
Q
1 For match load
gs
SmS
C
LgR
Fall, 2010 RF CMOS Tranceiver Design 13/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
RL Vin
Vout
Rs
Ls
Lg
Zin Vgs
gsso
inCR
Q2
1
Gain
inings VQV
gs
outm
V
Vg
min
in
mgs
in
outm gQ
V
gV
V
VG
mm QgG
So, Lm RGGain or Lmin RgQ & minm gQG
Noise Figure:
sourceinputtodueoutputatpowernoise
outputatpowernoiseTotalNF
For this calculation we ignore channel noise.
OUTnRS
OUTnD
OUTnRS
OUTnDOUTnRS
V
V
V
VVF
,2
,2
,2
,2
,2
1
LDnOUTnD RiV 2,
2,
2 fgKTi mDn 4,2
LmRSnOUTnRS RGVV 22,
2,
2 fKTRV SRSn 4,2
& minm gQG
LminRSn
LDn
RgQV
RiF
222,
2
2,
2
1 mDn gKTi 4,2 , SRSn KTRV 4,
2
inSm QRgF
21
Notes:
- Very good NF value
- Narrow band matching
- NF with 2Q
- The Q is dependent upon Lg + Ls, Ls is small so Q depend upon Lg
Fall, 2010 RF CMOS Tranceiver Design 14/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
VDD
RL
VS Vout Rs
Ls
Lg
VDD
LD
VS Rs
Ls
Lg
CL RL generates noise so replace RL with LD so that’s
LD
oCL
1
Reverse Isolation
Vout
Lo
VDD
LD
Rs
Ls
Lg
CL
Vb
(Final Design)
Cgd
C). Draw Backs
i).
The CL can be the input capacitance of mixer or filter.
ii).
Reverse isolation depends upon Cgd to make it better cascade input device
Problem-2.7 (HW)
Fill-in the Table below, use the data from Problem-2.4, 2.5, 2.6 and 2.7
Type of LNA Zin Noise Factor Gain NF (dB)
Shunt Resistor Rsh 42
m Sg R
2m Lg R
Common Gate
Shunt Feedback
Source Degenerated
a) Calculate the NF for all above amplifiers. Assume γ=2, gm = 20mS, Rs = 50Ω, RF = 500Ω, and Qin = 2.
b) Which is best topology for Narrow Band LNA design at high frequency?
Fall, 2010 RF CMOS Tranceiver Design 15/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
VDD
LD RREF
Ls
Lg
M2
Vout
M1 CL = 10pF
M3
RBIAS
RS CB Vin
Problem-2.8 (Tutorial)
Real Design: We will design the inductor source degenerated LNA shown in Fig below to meet the specification outlined for IEEE802.11 (b) standard. The first cut approximate values are calculated as a starting point for simulation. In LAB3: Design of LNA you will take the same design and modify these component values to meet the specification.
LNA Specification:
NF < 2.5 db, Gain > 15dB, IP3 > -5dBm, Centre Frequency = 2.4 GHz
S11 < -20dB, S22 < -10dB, Load Capacitance = 1pF
Technology Parameters for 0.35um CMOS:
2 2 20.35 , 170 , 4.6 , 58 , 2eff n ox ox p oxL m C A V C mF m C A V
Solution:
Technology:
2
2
22
170,tan)(11.802
4.2,2,6.4,
35.0,58,170
VACdardSbIEE
GHzfmmFCCMOS
mVACVAC
oxo
oox
oxpoxo
Design Parameters
dBNFPFCVVR LDDS 5.2,10,3.3,50
Fall, 2010 RF CMOS Tranceiver Design 16/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
Component Description
Ls – Matches input impedance
Lg – Set the Resonant Frequency fO = 2.4 GHz
M3 – Biasing transistor which forms current mirror with M1
Ld – Tuned output increases the gain and also work as band pass filter with CL
M2 – Isolate tuned input and tuned output increases reverse isolation, also reduces the effect of Miller capacitance Cgd
CB – BC Blocking capacitor chosen to have negligible reactance at fO = 2.4 GHz
RBIAS – Large enough so that its equivalent current noise is small enough to be ignored. (Don’t consider it as voltage noise source. Why??)
Design Procedure
Size of M1:
We will not go for global minimum noise figure as given by two-point noise theory (See lecture on LNA Slide # 10)
50
11
5
2CCG gsopt
---------------(1)
!!44 1 mmWpFC Mgs (not possible)
Solution:
A & B are from Thomos. H. Lee book (LNA Chapter)
LNA NF will be optimized for given Power
* It will not be best NF globally.
Soxeffo
optRCL
W3
1
T
p
T
p FF
6.514.21 min,min, ---------------(A)
From (1) we can derive
TT
p CCF
3.211
5
21
2
min,
T
pF
3.21min, ---------------(B)
(a) is minimum NF for a given power consumption.
(b) is global minimum noise figure.
The difference is usually 0.5dB to 1dB (no big deal for Lower Power)
Fall, 2010 RF CMOS Tranceiver Design 17/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
Step - 1:
mAII 521 (Low Power consumption)
Step - 2:
Soxeff
MRCWL
W3
11
o
Mm
W
506.435.03
11
GHzff
mLVAC
mmFCR
ooo
effoxn
oxS
4.2,2
,35.0,170
,6.4,50 2
41 109.3 MW
mWM 390109.3 41
Step - 3:
oxeffMgs CLWC 113
2
pFmCgs 41.06.435.03903
21
1
1
1 2 DM
M
oxnm IL
WCg
VmAmgm 43535.0
39017021
SecradGpF
VmA
C
g
gs
mT 104
41.0
43
1
1
Assuming 2
Now
T
oF
6.51min
dBG
GF 55.2
104
4.226.51min
dBNF 55.2
It’s very close to what we derive, if the value is higher we can increase ID to increase T and
hence low NF on expense of power.
Fall, 2010 RF CMOS Tranceiver Design 18/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
Step - 4:
Source and gate inductance such that they cancel Cgs and set 50 input impedance
SecradGfoo 154.222
From previous problem
TS
gs
S
m
dTransformeS LC
LgRR
nHG
RL
T
SS 5.0
100
50
nHLS 5.0 can be implemented using Band wire.
Now 1
2
1
gso
sgC
LL
nH
pFGLL sg 81.10
41.015
12
nHLg 10
Step - 5:
pFCC
L L
Lo
d 112
nH
pFGLd 4.4
115
12
nHLd 4.4
Step - 6:
Size of M3 is chosen to minimize power consumption
mAIKRmW REFM 6.02,70 33
KRBIAS 2 (Large enough so that it’s equivalent current noise can be neglected)
pFCB 10 ( 6.6CX so good value @ 2.4G 6.62
1
Bo
BCf
X
)
Step - 7:
Size M2 = M3
So that they can have shared Drain Area..
(Note: We will simulate same design in LAB # 2)
Fall, 2010 RF CMOS Tranceiver Design 19/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
Problem-2.9 (Point to Ponder):
Connecting two Inductor source degenerated LNA as shown in Figure make the differential LNA. Differential LNA has many advantages: higher common mode rejection ratio, less sensitivity to the ground inductance variation Ls compared to single ended counterpart..
a) Compare intuitively the NF of single ended and differential if both have same power
consumption.
b) If low power is not parameter on interest, which LNA has lower NF?
Instructions:
For hand calculation of NF you can ignore the gate noise of the device and noise generated by the load resistance RL.
Acknowledgement: The major part of this tutorial was developed, while author was employed by Linkoping University, Sweden.