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FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Topics
Basic fabrication steps. Transistor structures. Basic transistor behavior. Latch up.
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Fabrication processes
IC built on silicon substrate:– some structures diffused into substrate;
– other structures built on top of substrate.
Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped)
Wires made of polycrystalline silicon (poly), multiple layers of aluminum/copper (metal).
Silicon dioxide (SiO2) is insulator.
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Simple cross section
substraten+ n+p+
substrate
metal1
poly
SiO2
metal2
metal3
transistor via
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Photolithography
Mask patterns are put on wafer using photo-sensitive material:
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Process steps
First place tubs to provide properly-doped substrate for n-type, p-type transistors:
p-tub n-tub
substrate
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Process steps, cont’d.
Pattern polysilicon before diffusion regions:
p-tub n-tub
poly polygate oxide
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Process steps, cont’d
Add diffusions, performing self-masking:
p-tub n-tub
poly poly
n+n+ p+ p+
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Process steps, cont’d
Start adding metal layers:
p-tub n-tub
poly poly
n+n+ p+ p+
metal 1 metal 1
vias
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Level 2 metal
Polish SiO2 before adding metal 2:
p-tub p-tub
poly poly
n+n+ p+ p+
metal 1 metal 1
vias
metal 2
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Transistor structure
n-type transistor:
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Transistor layout
n-type (tubs may vary):
w
L
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Drain current characteristics
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Drain current
Linear region (Vds < Vgs - Vt):
– Id = k’ (W/L)(Vgs - Vt)(Vds - 0.5 Vds2)
Saturation region (Vds >= Vgs - Vt):
– Id = 0.5k’ (W/L)(Vgs - Vt) 2
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
90 nm transconductances
Typical parameters: n-type:
– kn’ = 13 A/V2
– Vtn = 0.14 V
p-type:– kp’ = 7 A/V2
– Vtp = -0.21 V
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Current through a transistor
Use 90 nm parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions.
Vgs = 0.25V:
Id = 0.5k’(W/L)(Vgs-Vt)2= 0.12 A
Vgs = 1V:
Id = 7.2 A
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Basic transistor parasitics
Gate to substrate, also gate to source/drain. Source/drain capacitance, resistance.
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Basic transistor parasitics, cont’d
Gate capacitance Cg. Determined by active area.
Source/drain overlap capacitances Cgs, Cgd. Determined by source/gate and drain/gate overlaps. Independent of transistor L.– Cgs = Col W
Gate/bulk overlap capacitance.
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Latch-up
CMOS ICs have parastic silicon-controlled rectifiers (SCRs).
When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip.
Early CMOS problem. Can be solved with proper circuit/layout structures.
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Parasitic SCR
circuit I-V behavior
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Parasitic SCR structure
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Solution to latch-up
Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.
FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
CMOS Process Steps