Topic01B Introdiuction to Microprocessor and MicroControllers Part 2

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This topic covers the various components inside the Freescale MC9S12X

Transcript of Topic01B Introdiuction to Microprocessor and MicroControllers Part 2

Topic Video 01BIntroduction to Microprocessors

& Micro-controllers 1B

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A Typical Microprocessor• A microprocessor unit consists of a set of sequential and

combinatorial logic circuits.• The actions performed by these circuits is defined by the

stored program.• Unlike fixed logic circuits a microprocessor can perform

many tasks, driven purely by the software.• A microprocessor is generally implemented on a single

integrated circuit.• A processor requires: memory for storing data and

programs, support logic and I/O.

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A Typical Microprocessor Based System

Processor

MemoryMemory

MemoryMemory

I/O

I/O

Data Bus

Address Bus

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A Typical Microprocessor Based SystemProcessor Functions

• Processors are the main functional units of an embedded board and are primarily responsible for processing instructions and data.

• The basic microprocessor contains four basic sections:• The ALU (Arithmetic Logic Unit)‏• Interfacing• Control• Registers

• The microprocessor is capable of six simple functions:• Write data to system memory• Read data from system memory• Write data to an I/O device• Read data from an I/O device• Read an instruction from memory and execute it.• Manipulate data within the microprocessor.

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A Typical Microprocessor Based SystemProcessor Functions: ISA Architecture

• Features built into an architectures instruction set are commonly referred to as Instruction Set Architecture (ISA).• The ISA defines such features as – Operators / Instructions – The form of the operands (data)– Storage / addressing modes– Interrupt handling.

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A Typical Microprocessor Based SystemProcessor Functions: ISA Architecture

• Operations

• Instructions / Commands• Processor Specific

• Defined by ISA• Types of Operations

• computational‏• movement• branches‏• input/output operations• Context Switching

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A Typical Microprocessor Based SystemProcessor Functions: ISA Architecture

• Operation Format

Opcode Operand

– In the MC9S12XDP512 the opcodes are all 8 bits in length.

Eg.

LDAA #$32 => 86 32 => 10000110 00110010

OpCode Operand

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A Typical Microprocessor Based SystemProcessor Functions: ISA Architecture

• Operands– Operands are the data that instructions manipulate.

– In many architectures, ISA defines simple operand types of bytes (8bits), halfwords (16bits) and words (32bits).

– More complex data types such as integers, characters, or floating point are based on the simple types.

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• Storage– The address space can be characterized in one of two ways:• Linear

A linear address space is one in which specific memory locations are represented incrementally, typically starting at 0 through to 2N-1, where N is the address width in bits.

• SegmentedThe address space is split into segments where each segment is linear

and a specific segment can be selected via a register.

A Typical Microprocessor Based SystemProcessor Functions: ISA Architecture

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A Typical Microprocessor Based SystemProcessor Functions: ISA Architecture

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A Typical Microprocessor Based SystemAside: Memory

• Processors need memory.• Memory consists of three basic sections:

• RAM (Random Access Memory) (Read/Write)‏• ROM (Read Only Memory)‏• I/O (Memory Addressable I/O Registers)‏

• Data and instructions are stored in memory

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A Typical Microprocessor Based SystemProcessor Functions: ISA Architecture

• Register Set–Fast internal memory (inside CPU core)–Name memory spaces, not addressable.–General Purpose or fixed purpose.–A microprocessor can contain anywhere between a few to several hundred.

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MC9S12XDP512Registers: The Programmers Model (Register Set)‏

• The MC9S12XDP512 has a processing core called CPUS12.

• The register set of the CPUS12 consists of • a 16 bit Accumulator• Two index registers X and Y.• A 16 bit stack pointer• A 16 bit program counter • A 16 bit condition code

register.

X index register

Y index register

Program Counter register

Stack Pointer register

Condition Code Register (CCR)‏

Accumulator D

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MC9S12XDP512Registers: The Programmers Model (Register Set)

Accumulators

• General purpose registers• Commonly used registers• Able to perform mathematical and logic operations• The CPU12X contains a 16 bit accumulator that can be split to form

two 8 bit accumulators (A and B).• Accumulators A and B are interchangeable.

BA

D

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MC9S12XDP512Registers: The Programmers Model (Register Set)

Stack Pointer

• The stack pointer is a 16 bit register which points to the top of the stack.

• The stack is a LIFO buffer sitting in our memory space.• The stack is used for temporary storage during program execution.• As the stack is filled with elements it grows, and as the elements are

removed it shrinks.• The stack pointer is a 16 bit registers that points to the last memory

location filled by a stack operation (the top).

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How a Stack works...

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How a Stack works...

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How a Stack works...

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How a Stack works...

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How a Stack works...

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How a Stack works...

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How a Stack works...

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How a Stack works...

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How a Stack works...

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How a Stack works...

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How a Stack works...

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How a Stack works...

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How a Stack works...

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MC9S12XDP512Registers: The Programmers Model (Register Set)

Stack Pointer

C2

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C2

D2

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SP

A: D2 A: D2

SP

The affect of a PSHA operation on the stack and associated

Accumulator.

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MC9S12XDP512Registers: The Programmers Model (Register Set)

Stack Pointer

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C2

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C2

67

12

SP

A: D2 A: C2

SP

The affect of a PULA operation on the stack and associated

Accumulator.

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MC9S12XDP512Registers: The Programmers Model (Register Set)

Program Counter

• 16 bit register• Holds the memory location of the next instruction to be executed.• Its contents can only be modified by Jump or Branch instructions.

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MC9S12XDP512Registers: The Programmers Model (Register Set)

Condition Code Register

• The condition code register is an 16 bit register, which reflects the current state of the processor.

• The code condition register consists of five status indicators, two interrupt masking bits, and a STOP instruction control bit.

• The status bits reflect the the results of the CPU operation as it executes instructions. The five flags are:

• Half Carry (H)‏• Negative (N)‏• Zero (Z)‏• Overflow (V)‏• Carry/Borrow (C)‏

0 0 0 0 0 IPL[2:0] S X H I N Z V C

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MC9S12XDP512Registers: The Programmers Model (Register Set)

• The MSB of the condition code register contains only 3 active bits.• IPL [2:0]– The IPL bits allow nested interrupts to be used. –More than one interrupt can be running at a time– The value in IPL defines which interrupt is allowed to complete

first.– This is covered in the interrupt topic.

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MC9S12XDP512Registers: The Programmers Model (Register Set)

Condition Code Register

• S Control BitSetting the S bit disables the use of the stop

instruction. • X mask bit• Enables or disables the external XIRQ pin and the supporting interrupt subsystem.

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MC9S12XDP512Registers: The Programmers Model (Register Set)

Condition Code Register

• H status bitThe H bit indicates a half carry for Accumulator A or B.

• I mask bitThe I bit is used to enable or disable the maskable interrupt

subsystem.

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MC9S12XDP512Registers: The Programmers Model (Register Set)

Condition Code Register

• N status bitThe N status bit reflects the state of the MSB of the previous operation.

• Z status bitThe Z bit is set when the bits of a result are all “0”s.

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MC9S12XDP512Registers: The Programmers Model (Register Set)

Condition Code Register

• V status bitThe V status bit is set when the a two’s complement overflow occurs

as a result of an operation.

• C status bitThe C bit is set when a carry occurs during addition or a borrow

occurs during subtraction.

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MC9S12XDP512Registers: The Programmers Model (Register Set)

Index Register

• An index register is used mainly during indexed addressing.• They can also be used as 16 bit general purpose

registers.• An index register can also be used as a 16 bit counter.• The MC9S12XDP512 contains two index register

namely X and Y.

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A Typical Microprocessor Based SystemProcessor Functions: ISA Architecture

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Instruction Queue

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Instruction Queue

Example:Given the following section of code, outline the contents of the

instruction queue at each instruction cycle. Memory Machine OpCode Operand

Address code 0D00 B6 12 34 LDAA $1234 0D03 43 DECA 0D04 47 ASRA 0D05 BB 12 35 ADDA $1235 0D08 XX YY

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Normal Flow (1)‏

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Normal Flow (2)‏

• Queue Advances

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Normal Flow (3)‏

• Queue Advances

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Normal Flow (4)‏

• Queue does not advance• Next Instruction

Latched

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Normal Flow (5)‏

• Queue Advances• Buffer Latched into

Stage 2

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Instruction QueueChanges in Execution Flow

• During normal execution the queue proceeds as a continuous sequence of queue movement cycles.• However situations arise that interrupt the smooth flow

of the queue.• Such situations are categorized as:

• Resets,• Interrupts,• Subroutine Calls,• Conditional Branches• And Jumps.

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Arithmetic and Logic Unit

• The brain of the processor is the ALU. IT performs all the mathematical and logic operations.

Accumulator Buffer

Control

lines

Result = Accumulator opr Buffer

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Arithmetic and Logic Unit The Arithmetic Section

• The arithmetic section of the ALU contains logic to implement binary arithmetic, such as:•Addition•Subtraction•Multiplication•Division

• The most simplest of these operations being Addition.

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Arithmetic and Logic UnitThe Half-Adder

• Before looking at the Adder it is worthwhile to first look at a device commonly know as the half-adder.

• The goal of a half-adder is to add two binary digits, based on the assumption that there is no carry input.

• The truth table of such a device would be:

0000

1011

0101

1

R

010

CBA

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R=A⊕BC=A.B

Arithmetic and Logic UnitThe Half-Adder

• From the truth table it can be clearly seen that the output R is simply the XOR of both A and B, and the carry output is simply A AND B .• The logical implementation of the half adder

would be:

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Arithmetic and Logic UnitThe Full-Adder

• The full adder is designed to take into account the carry from the lesser significant bits.• The full-adder has three inputs:

• A and B

• Cin

• And produces two outputs:• S (the full sum) ‏• And Cout the outputted Carry.

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Arithmetic and Logic UnitThe Full-Adder

• The truth table and logical implementation of the full-adder is shown.

1

0

0

1

0

1

1

0

S

1010111

1101011

1101101

0000001

0

0

0

0

Cp

1

0

0

0

Cout

10110

01010

01100

00000

CRBACin

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Arithmetic and Logic UnitThe Full-Adder

• The Full Adder can be represented by the following logic symbol.

• And in gate form as...

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Arithmetic and Logic UnitThe Full-Adder

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Arithmetic and Logic UnitThe Functions of the ALU

• As mentioned previously the ALU performs arithmetic operations on binary data and can also simply act as a data path way.

• The ALU can also perform binary logical operation such as logical shifts, logical AND, OR and XOR.

• The function of the ALU is defined by a series of control lines that feed into it.

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Arithmetic and Logic UnitThe Functions of the ALU

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Arithmetic and Logic UnitThe Functions of the ALU

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MC9S12XDP512The ALU

• The ALU inside the CPU12X core is in fact a 20 bit ALU, capable of performing one large operation or two smaller operations during a single instruction cycle (a single 16 bit operation or two 8 bit operations).

• The functions performed by the ALU are controlled by the Instruction Queue via the µP control section.

• The CPU12X core boasts the fastest ALU ever implemented on a Motorola general-purpose MCU.

• Operations undertaken in the ALU directly effect the status of the CCR.• The CPU12X ALU is capable of performing the following functions:

• 8 bit and 16 bit subtraction and addition.• BCD addition• 8 bit and 16 bit multiplication and division• Bit tests and manipulation (CMP, BCLR, BSET, AND, OR, XOR)‏• Two complement addition and subtraction.

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A Typical Microprocessor Based SystemFunction of the External Buses

• A bus is considered as a group of related signals, that provide information transfer inside a computer in a parallel fashion.

• The width of a bus depends on the number of signal lines.• Address Bus – usually 16 or 32 bits wide• Data Bus – 8, 16, 32 or even 64 bits wide.• Control Bus – Consists of various control signals such as:

» Read/Write» Clock» Interrupt

Address

Data

Control

ExternalDevice

Processor

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Processor in Review• An instruction is fetched from memory.• It is then loaded into the instruction decoder.• The instruction decoder then executes the

instruction.• The instruction may take many clock cycles

depending what it must do.• The instruction may require the use a register, the

ALU or memory in order to complete properly.• For example, if the instruction was

LDAA PortAThis would require the processor to fetch an 8 bit value

out of memory in the location referred to by the variable PortA and put that value in Accumulator A.

The steps involved in completing this instruction successfully would be

Give the Memory Interface the

address of Port A(from Instruction)‏

Echo the address of Port A onto the Address Bus and

set the read line high

Read the value from theAddress of Port A via the Data Bus into a temporary register

Move the value read from Port A into Accumulator A

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MC9S12XDP512The Overall System

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Need Further Assistance?

• Ask your Demonstrator,

• Post a question on the Forum,

• Email the Convener, or

• Make an appointment.

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