Post on 18-Jul-2020
TinyPowerTM A/D Flash MCU with LCD & EEPROM
HT67F488HT67F489
Revision: V1.60 Date: �ove��e� ��� �016�ove��e� ��� �016
Rev. 1.60 � �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Table of Contents
Features ............................................................................................................ 6CPU Featu�es ......................................................................................................................... 6Pe�iphe�al Featu�es ................................................................................................................. 6
General Description ......................................................................................... 7Selection Table ................................................................................................. 8Block Diagram .................................................................................................. 8Pin Assignment ................................................................................................ 9Pin Description .............................................................................................. 10Absolute Maximum Ratings .......................................................................... 13D.C. Characteristics ....................................................................................... 13A.C. Characteristics ....................................................................................... 15A/D Converter Electrical Characteristics ..................................................... 16LVD & LVR Electrical Characteristics .......................................................... 16Power on Reset Characteristics ................................................................... 17System Architecture ...................................................................................... 18
Clocking and Pipelining ......................................................................................................... 18P�og�a� Counte� ................................................................................................................... 19Stack ..................................................................................................................................... �0A�ith�etic and Logic Unit – ALU ........................................................................................... �0
Flash Program Memory ................................................................................. 21St�uctu�e ................................................................................................................................ �1Special Vecto�s ..................................................................................................................... �1Look-up Ta�le ........................................................................................................................ ��Ta�le P�og�a� Exa�ple ........................................................................................................ ��In Ci�cuit P�og�a��ing – ICP ............................................................................................... �3On-Chip De�ug Suppo�t – OCDS ......................................................................................... �4
RAM Data Memory ......................................................................................... 25St�uctu�e ................................................................................................................................ �5Data Me�o�y Add�essing ...................................................................................................... �6Gene�al Pu�pose Data Me�o�y ........................................................................................... �6Special Pu�pose Data Me�o�y ............................................................................................ �6
Special Function Register Description ........................................................ 28Indi�ect Add�essing Registe� – IAR0� IAR1� IAR� ................................................................. �8Me�o�y Pointe�s – MP0� MP1L� MP1H� MP�L� MP�H ......................................................... �8Accu�ulato� – ACC ............................................................................................................... 30P�og�a� Counte� Low Registe� – PCL ................................................................................. 30Look-up Ta�le Registe�s – TBLP� TBHP� TBLH .................................................................... 31Status Registe� – STATUS ................................................................................................... 31
Rev. 1.60 3 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
EEPROM Data Memory .................................................................................. 33EEPROM Data Me�o�y St�uctu�e ........................................................................................ 33EEPROM Registe�s .............................................................................................................. 33Reading Data f�o� the EEPROM ......................................................................................... 35W�iting Data to the EEPROM ................................................................................................ 35W�ite P�otection ..................................................................................................................... 35EEPROM Inte��upt ................................................................................................................ 35P�og�a��ing Conside�ations ................................................................................................ 36P�og�a��ing Exa�ples ........................................................................................................ 36
Oscillators ...................................................................................................... 37Oscillato� Ove�view .............................................................................................................. 37System Clock Configurations ............................................................................................... 37Exte�nal C�ystal/Ce�a�ic Oscillato� – HXT ........................................................................... 38Inte�nal RC Oscillato� – HIRC .............................................................................................. 38Exte�nal 3�.768kHz C�ystal Oscillato� – LXT ........................................................................ 39LXT Oscillato� Low Powe� Function ..................................................................................... 40Inte�nal 3�kHz Oscillato� – LIRC .......................................................................................... 40
Operating Modes and System Clocks ........................................................ 41Syste� Clocks ..................................................................................................................... 41Syste� Ope�ation Modes ..................................................................................................... 4�Cont�ol Registe� .................................................................................................................... 43Ope�ating Mode Switching ................................................................................................... 45Stand�y Cu��ent Conside�ations .......................................................................................... 49Wake-up ............................................................................................................................... 49
Watchdog Timer ............................................................................................. 50Watchdog Ti�e� Clock Sou�ce .............................................................................................. 50Watchdog Ti�e� Cont�ol Registe� ......................................................................................... 50Watchdog Ti�e� Ope�ation ................................................................................................... 51
Reset and Initialisation .................................................................................. 52Reset Functions ................................................................................................................... 5�Reset Initial Conditions ........................................................................................................ 55
Input/Output Ports ........................................................................................ 58Pull-high Resisto�s ................................................................................................................ 59Po�t A Wake-up ..................................................................................................................... 59I/O Po�t Cont�ol Registe�s ..................................................................................................... 59Pin-sha�ed Functions ............................................................................................................ 59I/O Pin St�uctu�es .................................................................................................................. 60P�og�a��ing Conside�ations ............................................................................................... 61
Timer Modules – TM ...................................................................................... 62Int�oduction ........................................................................................................................... 6�TM Ope�ation ........................................................................................................................ 6�TM Clock Sou�ce ................................................................................................................... 63TM Inte��upts ......................................................................................................................... 63
Rev. 1.60 4 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
TM Exte�nal Pins .................................................................................................................. 63TM Input/Output Pin Cont�ol Registe�s ................................................................................. 63P�og�a��ing Conside�ations ................................................................................................ 65
Periodic Type TM – PTM ................................................................................ 66Pe�iodic TM Ope�ation .......................................................................................................... 66Pe�iodic Type TM Registe� Desc�iption ................................................................................. 67Pe�iodic Type TM Ope�ating Modes ...................................................................................... 7�
Compact Type TM – CTM .............................................................................. 81Co�pact TM Ope�ation ........................................................................................................ 81Co�pact Type TM Registe� Desc�iption................................................................................ 8�Co�pact Type TM Ope�ating Modes .................................................................................... 86
Analog to Digital Converter – ADC ............................................................... 92A/D Ove�view ........................................................................................................................ 9�A/D Conve�te� Registe� Desc�iption ...................................................................................... 9�A/D Conve�te� Data Registe�s – ADRL� ADRH ..................................................................... 93A/D Conve�te� Cont�ol Registe�s – ADCR0� ADCR1� ACERL� ACERH ................................ 93A/D Ope�ation ...................................................................................................................... 97A/D Input Pins ....................................................................................................................... 98Su��a�y of A/D Conve�sion Steps ...................................................................................... 99P�og�a��ing Conside�ations .............................................................................................. 100A/D T�ansfe� Function ......................................................................................................... 100A/D P�og�a��ing Exa�ple ................................................................................................. 101
LCD Display Memory ................................................................................... 103LCD D�ive� Output ............................................................................................................... 103LCD Cont�ol Registe� .......................................................................................................... 104LCD Wavefo�� .................................................................................................................... 108
LED Driver .....................................................................................................111LED D�ive� Ope�ation ...........................................................................................................111LED D�ive� Registe� .............................................................................................................111
UART Interface ..............................................................................................112UART Exte�nal Pin Inte�facing .............................................................................................113UART Data T�ansfe� Sche�e...............................................................................................113UART Status and Cont�ol Registe�s.....................................................................................113Baud Rate Gene�ato� ...........................................................................................................119UART Setup and Cont�ol..................................................................................................... 1�0UART T�ans�itte�................................................................................................................ 1��UART Receive� ................................................................................................................... 1�3Managing Receive� E��o�s .................................................................................................. 1�5UART Module Inte��upt St�uctu�e ........................................................................................ 1�6Add�ess Detect Mode .......................................................................................................... 1�7UART Module Powe� Down and Wake-up .......................................................................... 1�7
Rev. 1.60 5 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Interrupts ...................................................................................................... 129Inte��upt Registe�s ............................................................................................................... 1�9Inte��upt Ope�ation .............................................................................................................. 137Exte�nal Inte��upt ................................................................................................................. 139Multi-function Inte��upt ........................................................................................................ 139A/D Conve�te� Inte��upt ....................................................................................................... 139UART Inte��upt .................................................................................................................... 140Ti�e Base Inte��upt ............................................................................................................. 140EEPROM Inte��upt .............................................................................................................. 141LVD Inte��upt ....................................................................................................................... 14�TM Inte��upts ...................................................................................................................... 14�Inte��upt Wake-up Function ................................................................................................. 14�P�og�a��ing Conside�ations .............................................................................................. 143
Low Voltage Detector – LVD ....................................................................... 144LVD Registe� ....................................................................................................................... 144LVD Ope�ation ..................................................................................................................... 145
Configuration Options ................................................................................. 146Application Circuits ..................................................................................... 146Instruction Set .............................................................................................. 147
Int�oduction ......................................................................................................................... 147Inst�uction Ti�ing ................................................................................................................ 147Moving and T�ansfe��ing Data ............................................................................................. 147A�ith�etic Ope�ations .......................................................................................................... 147Logical and Rotate Ope�ation ............................................................................................. 148B�anches and Cont�ol T�ansfe� ........................................................................................... 148Bit Ope�ations ..................................................................................................................... 148Ta�le Read Ope�ations ....................................................................................................... 148Othe� Ope�ations ................................................................................................................. 148
Instruction Set Summary ............................................................................ 149Ta�le Conventions ............................................................................................................... 149Extended Inst�uction Set ..................................................................................................... 151
Instruction Definition ................................................................................... 153Extended Instruction Definition ........................................................................................... 16�
Package Information ................................................................................... 16944-pin LQFP (10��×10��) (FP�.0��) Outline Di�ensions ........................................... 170
Rev. 1.60 6 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Features
CPU Features• OperatingVoltage
♦ fSYS=4MHz:2.2V~5.5V♦ fSYS=8MHz:2.2V~5.5V♦ fSYS=12MHz:2.7V~5.5V♦ fSYS=16MHz:4.5V~5.5V
• Powerdownandwake-upfunctionstoreducepowerconsumption
• Oscillators♦ InternalRC–HIRC♦ ExternalCrystal-HXT♦ Internal32kHzRC–LIRC♦ External32.768kHzCrystal–LXT
• Fullyintegratedinternal8MHzoscillatorrequiresnoexternalcomponents
• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP
• Allinstructionsexecutedin1~3instructioncycles
• Bitmanipulationinstruction
• 16-bitTableReadFunction
• 115powerfulinstructions
• SupportdualwordsinstructionsforRAMaccess
• 8-levelsubroutinenesting
Peripheral Features• FlashProgramMemory:4K×16~8K×16
• RAMDataMemory:256×8
• TrueEEPROMMemory:64×8(onlyforHT67F489)
• WatchdogTimerfunction
• 42bidirectionalI/Olines♦ InlcudeLCD/LEDdrivingoutput
• 4pin-sharedexternalinterrupts
• MultipleTimerModulesfortimemeasure,inputcapture,comparematchoutput,PWMoutputorsinglepulseoutputfunctions
• DualTime-Basefunctionsforgenerationoffixedtimeinterruptsignals
• 10-channel12-bitresolutionA/Dconverter
• LCDdisplay♦ 20SEG×4COM&20SEG×8COM♦ 1/3or1/4bias
• LEDdisplay:8SEG×8COM
• Fully-duplexUniversalAsynchronousReceiverandTransmitterInterface--UART
• LowVoltageResetfunction
• LowVoltageDetectfunction
• Packagetype:44-pinLQFP
Rev. 1.60 7 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
General DescriptionTheHT67F488/HT67F489seriesofdevicesareFlashMemoryA/Dtype8-bithighperformanceRISCarchitecturemicrocontrollers,designedespeciallyforapplicationsthat interfacedirectlytoanalogsignals,suchasthosefromsensors.OfferinguserstheconvenienceofFlashMemorymulti-programmingfeatures, thesedevicesalso includeawiderangeoffunctionsandfeatures.OthermemoryincludesanareaofRAMDataMemoryaswellasanareaoftrueEEPROMmemory(onlyforHT67F489)forstorageofnon-volatiledatasuchasserialnumbers,calibrationdataetc.
Analogfeatures includeamulti-channel12-bitA/Dconverterfunction.MultipleandextremelyflexibleTimerModulesprovidetiming,pulsegenerationandPWMgenerationfunctions.ProtectivefeaturessuchasaninternalWatchdogTimer,LowVoltageResetandLowVoltageDetectorcoupledwithexcellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.
AfullchoiceofHIRC,HXT,LXTandLIRCoscillatorfunctionsareprovidedincludingafullyintegratedsystemoscillatorwhichrequiresnoexternalcomponents for its implementation.Theability tooperateandswitchdynamicallybetweena rangeofoperatingmodesusingdifferentclocksourcesgivesusers theability tooptimisemicrocontrolleroperationandminimizepowerconsumption.
TheUARTmodule iscontained in thesedevices. Itcansupport theapplicationssuchasdatacommunicationnetworksbetweenmicrocontrollers,low-costdatalinksbetweenPCsandperipheraldevices,portableandbatteryoperateddevicecommunication,etc.
TheinclusionofbothLCDandLEDdriverfunctionsallowsforeasyandcosteffectivesolutionsinapplicationsthatrequireinterfacetothesedisplaytypes.
TheinclusionofflexibleI/Oprogrammingfeatures,Time-BasefunctionsalongwithmanyotherfeaturesenhancetheversatilityofthesedevicestosuitawiderangeofA/Dapplicationpossibilitiessuchassensorsignalprocessing,chargers,motordriving, industrialcontrol,consumerproducts,subsystemcontrollers,etc.
Rev. 1.60 8 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Selection TableMostfeaturesarecommontoalldevices,themainfeaturedistinguishingthemareMemorycapacityandwhetherEEPROMornot.Thefollowingtablesummarisesthemainfeaturesofeachdevice.
Part No. Program Memory
Data Memory
DataEEPROM I/O Ext.
Interrupt A/D LCD Driver
HT67F488 4K×16 �56×8 — 4� 4 1�-�it×10 �0×4� �0×8
HT67F489 8K×16 �56×8 64×8 4� 4 1�-�it×10 �0×4� �0×8
Part No. LED Driver Timer Module Time Base UART Stack Package
HT67F488 8x8 10-�it CTM×310-�it PTM×1 � √ 8 44LQFP
HT67F489 8x8 10-�it CTM×310-�it PTM×1 � √ 8 44LQFP
Block Diagram
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Rev. 1.60 9 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Pin Assignment
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Rev. 1.60 10 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Pin Description
Pin Name Function OPT I/T O/T Description
PA0/I�T�/TCK0/OCDSDA/ICPDA
PA0 PAPUPAWU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high and
wake-up.
I�T� — ST — Exte�nal Inte��upt �
TCK0 — ST — TM0 input
OCDSDA — ST CMOS OCDS Add�ess/Data� fo� EV chip only.
ICPDA — ST CMOS ICP Add�ess/Data
PA1/OSC�PA3/OSC1PA6� PA7
PA1� PA3�PA6� PA7
PAPUPAWU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high and
wake-up.
OSC1 OSC HXT — High f�equency c�ystal pin
OSC� OSC HXT — High f�equency c�ystal pin
PA�/I�T3/TP0_0/OCDSCK/ICPCK
PA� PAPUPAWU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high and
wake-up.
I�T3 — ST — Exte�nal Inte��upt 3
TP0_0 TMPC ST CMOS TM0 I/O
OCDSCK — ST — OCDS Clock pin� fo� EV chip only.
ICPCK — ST — ICP Clock pin
PA4/XT1PA4 PAPU
PAWU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high and wake-up.
XT1 FSUBC LXT — Low f�equency c�ystal pin
PA5/XT�PA5 PAPU
PAWU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high and wake-up.
XT� FSUBC — LXT Low f�equency c�ystal pin
PB0/A�0/TCK3
PB0 PBPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
A�0 ACERL A� — A/D channel 0
TCK3 — ST — TM3 input
PB1/A�1/TP3
PB1 PBPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
A�1 ACERL A� — A/D channel 1
TP3 TMPC ST CMOS TM3 I/O
PB�/A��/TP�
PB� PBPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
A�� ACERL A� — A/D channel �
TP� TMPC ST CMOS TM� I/O
PB3/A�3/TP1
PB3 PBPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
A�3 ACERL A� — A/D channel 3
TP1 TMPC ST CMOS TM1 I/O
PB4/A�7/VREF
PB4 PBPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
A�7 ACERL A� — A/D channel 7
VREF ADCR1 A� — ADC �efe�ence voltage input pin
PB5/A�9PB5 PBPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
A�9 ACERH A� — A/D channel 9
PC0/SEG8PC0 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG8 SEGCR1 — CMOS LCD seg�ent output
PC1/SEG9PC1 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG9 SEGCR1 — CMOS LCD seg�ent output
Rev. 1.60 11 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Pin Name Function OPT I/T O/T Description
PC�/SEG10PC� PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG10 SEGCR1 — CMOS LCD seg�ent output
PC3/SEG11PC3 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG11 SEGCR1 — CMOS LCD seg�ent output
PC4/SEG1�PC4 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG1� SEGCR1 — CMOS LCD seg�ent output
PC5/SEG13PC5 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG13 SEGCR1 — CMOS LCD seg�ent output
PC6/SEG14PC6 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG14 SEGCR1 — CMOS LCD seg�ent output
PC7/SEG15PC7 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG15 SEGCR1 — CMOS LCD seg�ent output
PD0/SEG0PD0 PDPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG0 SEGCR0 — CMOS LCD seg�ent output
PD1/SEG1PD1 PDPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG1 SEGCR0 — CMOS LCD seg�ent output
PD�/SEG�PD� PDPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG� SEGCR0 — CMOS LCD seg�ent output
PD3/SEG3PD3 PDPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG3 SEGCR0 — CMOS LCD seg�ent output
PD4/SEG4PD4 PDPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG4 SEGCR0 — CMOS LCD seg�ent output
PD5/SEG5PD5 PDPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG5 SEGCR0 — CMOS LCD seg�ent output
PD6/SEG6PD6 PDPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG6 SEGCR0 — CMOS LCD seg�ent output
PD7/SEG7PD7 PDPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG7 SEGCR0 — CMOS LCD seg�ent output
PE0/COM0PE0 PEPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
COM0 LCDC0 — CMOS LCD co��on output
PE1/COM1PE1 PEPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
COM1 LCDC0 — CMOS LCD co��on output
PE�/COM�PE� PEPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
COM� LCDC0 — CMOS LCD co��on output
PE3/COM3PE3 PEPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
COM3 LCDC0 — CMOS LCD co��on output
PE4/A�4/COM4/TCK1
PE4 PEPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
A�4 ACERL A� — A/D channel 4
COM4 LCDC0 — CMOS LCD co��on output
TCK1 — ST — TM1 input
Rev. 1.60 1� �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Pin Name Function OPT I/T O/T Description
PE5/A�5/COM5/TCK�
PE5 PEPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
A�5 ACERL A� — A/D channel 5
COM5 LCDC0 — CMOS LCD co��on output
TCK� — ST — TM� input
PE6/A�6/COM6
PE6 PEPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
A�6 ACERL A� — A/D channel 6
COM6 LCDC0 — CMOS LCD co��on output
PE7/A�8/COM7
PE7 PEPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
A�8 ACERH A� — A/D channel 8
COM7 LCDC0 — CMOS LCD co��on output
PF4/SEG16/RX
PF4 PFPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG16 SEGCR� — CMOS LCD seg�ent output
RX — ST — Exte�nal UART RX se�ial data input pin
PF5/SEG17/TX
PF5 PFPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG17 SEGCR� — CMOS LCD seg�ent output
TX — — CMOS Exte�nal UART TX se�ial data output pin
PF6/SEG18/I�T0
PF6 PFPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG18 SEGCR� — CMOS LCD seg�ent output
I�T0 — ST — Exte�nal Inte��upt 0
PF7/SEG19/I�T1/TP0_1
PF7 PFPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-high.
SEG19 SEGCR� — CMOS LCD seg�ent output
I�T1 — ST — Exte�nal Inte��upt 1
TP0_1 TMPC ST CMOS TM0 I/O
AVDD AVDD — PWR — ADC Powe� Supply
VDD VDD — PWR — Powe� Supply
AVSS AVSS — PWR — ADC G�ound
VSS VSS — PWR — G�ound
Note:I/T:Inputtype; O/T:OutputtypeOPT:OptionalbyregisteroptionPWR:Power; ST:SchmittTriggerinputCMOS:CMOSoutput; AN:AnalogSignalLXT:Lowfrequencycrystaloscillator
Rev. 1.60 13 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-40˚Cto85˚CIOHTotal....................................................................................................................................-80mAIOLTotal..................................................................................................................................... 80mATotalPowerDissipation........................................................................................................ 500mW
Note:Thesearestressratingsonly.Stressesexceeding therangespecifiedunder"AbsoluteMaximumRatings"maycausesubstantialdamagetothesedevices.Functionaloperationofthesedevicesatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.
D.C. CharacteristicsTa=�5°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VDD Ope�ating Voltage (HXT) —
fSYS=4MHz �.� — 5.5 VfSYS=8MHz �.� — 5.5 VfSYS=1�MHz �.7 — 5.5 VfSYS=16MHz 4.5 — 5.5 V
IDD
Ope�ating Cu��ent��o��al Mode� fSYS=fH�fSUB=fLXT o� fLIRC
3V �o load� fH=8MHz� ADC off� WDT ena�le
— 1.6 �.4 �A
5V — 3.3 5.0 �A
Ope�ating Cu��ent��o��al Mode� fH=8MHz
3V �o load� fSYS=fH/�� ADC off� WDT ena�le
— 0.9 1.5 �A5V — �.5 3.75 �A3V �o load� fSYS=fH/4�
ADC off� WDT ena�le— 0.7 1.0 �A
5V — �.0 3.0 �A3V �o load� fSYS=fH/8�
ADC off� WDT ena�le— 0.6 0.9 �A
5V — 1.6 �.4 �A3V �o load� fSYS=fH/16�
ADC off� WDT ena�le— 0.5 0.75 �A
5V — 1.5 �.�5 �A3V �o load� fSYS=fH/3��
ADC off� WDT ena�le— 0.49 0.74 �A
5V — 1.45 �.18 �A3V �o load� fSYS=fH/64�
ADC off� WDT ena�le— 0.47 0.71 �A
5V — 1.4 �.1 �A
Ope�ating Cu��ent� Slow Mode� fSYS= fSUB
(LXT� LIRC)
3V �o load� fSYS=LXT�ADC off� WDT ena�le� LXTLP=0� LVR ena�le
— 45 75 μA
5V — 90 140 μA
3V �o load� fSYS=LXT�ADC off� WDT ena�le� LXTLP=1� LVR ena�le
— 40 70 μA
5V — 85 135 μA
3V �o load� fSYS=LIRC� ADC off� WDT ena�le� LVR ena�le
— 40 65 μA5V — 80 130 μA
Rev. 1.60 14 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
IIDLE01IDLE0 Mode Stan�y Cu��ent(LXT On)
3V �o load� ADC off� WDT ena�le� LXTLP=0
— � 4 μA5V — 4 8 μA3V �o load� ADC off� WDT ena�le�
LXTLP=1— 1.5 3.0 μA
5V — 3.0 6.0 μA
IIDLE0�IDLE0 Mode Stan�y Cu��ent(LIRC On)
3V�o load� ADC off� WDT ena�le
— 1.5 3.0 μA5V — 3.0 6.0 μA
IIDLE03IDLE0 Mode Stan�y Cu��ent(LXT On)
3V �o load� ADC off� WDT ena�le�LXTLP=1� LCD ena�le(RT=1170kΩ without quick cha�ge� VLCD=VDD)
— 3 6 μA
5V — 6 1� μA
IIDLE04IDLE0 Mode Stan�y Cu��ent(LXT On)
3V �o load� ADC off� WDT ena�le�LXTLP=1� LCD ena�le(RT=225kΩ without quick cha�ge� VLCD=VDD)
— 14 �8 μA
5V — �4 48 μA
IIDLE05IDLE0 Mode Stan�y Cu��ent(LXT On)
3V �o load� ADC off� WDT ena�le�LXTLP=1� LCD ena�le(RT=1170kΩ with quick charge,QCT[�:0]=0� VLCD=VDD)
— 5 10 μA
5V — 9 18 μA
IIDLE06IDLE0 Mode Stan�y Cu��ent(LXT On)
3V �o load� ADC off� WDT ena�le�LXTLP=1� LCD ena�le(RT=1170kΩ with quick charge,QCT[�:0]=7� VLCD=VDD)
— 11 �� μA
5V — 18 36 μA
IIDLE1IDLE1 Mode Stan�y Cu��ent(LIRC On)
3V �o load� ADC off� WDT ena�le�fSYS=8MHz on
— 0.5 3.0 �A5V — 1.0 6.0 �A
ISLEEP0SLEEP0 Mode Stan�y Cu��ent(LXT o� LIRC Off)
3V �o load� ADC off� WDT disa�le
— 0.� 1 μA5V — 0.4 � μA
ISLEEP1SLEEP1 Mode Stan�y Cu��ent(LXT o� LIRC On)
3V �o load� ADC off� WDT ena�le
— 1.5 3.0 μA5V — �.5 5.0 μA
VILInput Low Voltage fo� I/O Po�ts o� Input Pins — — 0 — 0.3VDD V
VIHInput High Voltage fo� I/O Po�tso� Input Pins — — 0.7VDD — VDD V
GPIO (except for PD0~PD7 & PE0~PE7)
IOL I/O Po�t Sink Cu��ent3V VOL=0.1VDD 4 8 — �A5V VOL=0.1VDD 10 �0 — �A
IOH I/O Po�t Sou�ce Cu��ent3V VOH=0.9VDD -� -4 — �A5V VOH=0.9VDD -5 -10 — �A
High Sink I/O for LED driver (PE0~PE7)
IOL I/O Po�t Sink Cu��ent3V VOL=0.1VDD 8 16 — �A5V VOL=0.1VDD �0 40 — �A
IOH I/O Po�t Sou�ce Cu��ent3V VOH=0.9VDD -� -4 — �A5V VOH=0.9VDD -5 -10 — �A
Adjustable source I/O for LED driver (PD0~PD7)
IOL I/O Po�t Sink Cu��ent3V VOL=0.1VDD 4 8 — �A5V VOL=0.1VDD 10 �0 — �A
Rev. 1.60 15 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
IOH I/O Po�t Sou�ce Cu��ent
3V
VOH= 0.9VDD
(IOHSn[1:0]=00B� n=0~7) -� -4 — �A
VOH= 0.9VDD
(IOHSn[1:0]=01B� n=0~7) -0.67 -1.33 — �A
VOH= 0.9VDD
(IOHSn[1:0]=10B� n=0~7) -0.5 -1 — �A
VOH= 0.9VDD
(IOHSn[1:0]=11B� n=0~7) -0.33 -0.66 — �A
5V
VOH= 0.9VDD
(IOHSn[1:0]=00B� n=0~7) -5 -10 — �A
VOH= 0.9VDD
(IOHSn[1:0]=01B� n=0~7) -1.67 -3.33 — �A
VOH= 0.9VDD
(IOHSn[1:0]=10B� n=0~7) -1.�5 -�.5 — �A
VOH= 0.9VDD
(IOHSn[1:0]=11B� n=0~7) -0.83 -1.67 — �A
RPH Pull-high Resistance fo� I/O Po�ts3V — �0 60 100 kΩ5V — 10 30 50 kΩ
RT LCD total �ias �esiste� 3V/5V — -30 RT +30 %ITOL Total I/O Po�t Sink Cu��ent 5V — 80 — — �AITOH Total I/O Po�t Sou�ce Cu��ent 5V — -80 — — �A
A.C. CharacteristicsTa=�5°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
fCPU Ope�ating Clock —
�.�~5.5 DC ─ 4 MHz�.�~5.5V DC ─ 8 MHz�.7~5.5V DC ─ 1� MHz4.5~5.5V DC ─ 16 MHz
fSYS Syste� Clock (HIRC) �.�V~5.5V — — 8 — MHzfHIRC Syste� Clock (HIRC) 4.5V~5.5V Ta=0°C to 70°C -�% 8 +�% MHzfLIRC Syste� Clock (LIRC) 5V Ta=�5°C -10% 3� +10% kHztTIMER TCKn Input Pulse Width — — 0.3 — — μstI�T Inte��upt Pulse Width — — 10 — — μstEERD EEPROM Read Ti�e 5V — — � 4 tSYS
tEEWR EEPROM W�ite Ti�e 5V — — � 4 �s
tRSTD
Syste� Reset Delay Ti�e(Powe� On Reset� LVR Reset�WDTC/LVRC S/W Reset)
— — �5 50 100 �s
Syste� Reset Delay Ti�e(WDT Ti�e-out Reset) — — 8.3 16.7 33.3 �s
tSSTSyste� Sta�t-up Ti�e� Pe�iod(Wake-up f�o� HALT)
— fSYS=LXT/HXT — 10�4 —tSYS— fSYS=HIRC — 16 —
— fSYS=LIRC — � —tSRESET Softwa�e Reset Width to Reset — — 45 90 1�0 μs
Note:tSYS=1/fSYS
Rev. 1.60 16 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
A/D Converter Electrical CharacteristicsTa=�5°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
AVDD A/D Conve�te� Ope�ating Voltage — — �.7 — 5.5 VVADI A/D Conve�te� Input Voltage — — 0 — AVDD/VREF VVREF A/D Conve�te� Refe�ence Voltage — — � — AVDD VVBG Refe�ence with �uffe� voltage — — -3% 1.09 +3% V
D�L Diffe�ential �on-linea�ity 5V VREF=AVDD=VDD
tADCK=0.5μs -4 — +4 LSB
I�L Integ�al �on-linea�ity 5V VREF=AVDD=VDD
tADCK=0.5μs -7 — +7 LSB
IADCAdditional Powe� Consu�ption ifA/D Conve�te� is used
3V �o load (tADCK=0.5μs) — 0.9 1.35 �A5V �o load (tADCK=0.5μs) — 1.� 1.8 �A
IBGAdditional Powe� Consu�ption if VBG Refe�ence with Buffe� is Used — — — �00 300 μA
tADCK A/D Conve�te� Clock Pe�iod — — 0.5 — 10 μs
tADCA/D Conve�sion Ti�e(Include Sa�ple and Hold Ti�e) — 1�-�it ADC — 16 — tADCK
tADS A/D Conve�te� Sa�pling Ti�e — — — 4 — tADCK
tO��ST A/D Conve�te� On-to-Sta�t Ti�e — — � — — μstBGS VBG Tu�n on Sta�le Ti�e — — — — �00 μs
LVD & LVR Electrical CharacteristicsTa=�5°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VLVR Low Voltage Reset Voltage —
LVR Ena�le� �.10V option -5% �.10 +5% V
LVR Ena�le� �.55V option -5% �.55 +5% V
LVR Ena�le� 3.15V option -5% 3.15 +5% V
LVR Ena�le� 3.80V option -5% 3.80 +5% V
VLVD Low Voltage Detecto� Voltage —
LVDE�=1� VLVD=�.0V -5% �.0 +5% V
LVDE�=1� VLVD=�.�V -5% �.� +5% V
LVDE�=1� VLVD=�.4V -5% �.4 +5% V
LVDE�=1� VLVD=�.7V -5% �.7 +5% V
LVDE�=1� VLVD=3.0V -5% 3.0 +5% V
LVDE�=1� VLVD=3.3V -5% 3.3 +5% V
LVDE�=1� VLVD=3.6V -5% 3.6 +5% V
LVDE�=1� VLVD=4.0V -5% 4.0 +5% V
ILVDAdditional Powe� Consu�ption if LVD is used
3V LVD disable → LVD enable(LVR ena�le)
— 30 45 μA
5V — 60 90 μA
tLVR Low Voltage Width to Reset — — 1�0 �40 480 μs
tLVD Low Voltage Width to Inte��upt — — �0 45 90 μs
tLVDS LVDO sta�le ti�e — For LVR enable, LVD off→on — — 15 μs
Rev. 1.60 17 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Power on Reset CharacteristicsTa=�5°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VPOR VDD Sta�t Voltage to Ensu�e Powe�-on Reset — — — — 100 �V
RRVDD VDD Raising Rate to Ensu�e Powe�-on Reset — — 0.035 — — V/�s
tPORMini�u� Ti�e fo� VDD Stays at VPOR to Ensu�e Powe�-on Reset — — 1 — — �s
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Rev. 1.60 18 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.TherangeofdevicestakeadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.Thepipeliningscheme is implemented insuchaway that instruction fetchingand instructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinoneortwocyclesformostof thestandardorextended instructions respectively.Theexceptions to thisarebranchorcallinstructionswhichneedonemorecycle.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitectural featuresensure thataminimumofexternalcomponents is required toprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakes thedevicessuitableforlow-cost,high-volumeproductionforcontrollerapplications.
Clocking and PipeliningThemainsystemclock,derivedfromeitheraHIRC,HXT,LXTorLIRCoscillatorissubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedat thebeginningof theT1clockduringwhichtimeanewinstruction isfetched.TheremainingT2~T4clockscarryout thedecodingandexecution functions. In thisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutive instructioncycles, thepipeliningstructureof themicrocontrollerensures thatinstructionsareeffectivelyexecutedinoneinstructioncycle.TheexceptiontothisareinstructionswherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.
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System Clocking and Pipelining
Rev. 1.60 19 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.
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Instruction Fetching
Program CounterDuringprogramexecution, theProgramCounterisusedtokeeptrackof theaddressof thenextinstructiontobeexecuted.It isautomatically incrementedbyoneeachtimeaninstructionisex-ecutedexceptforinstructions,suchas“JMP”or“CALL”thatdemandsajumptoanon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.
Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.
DeviceProgram Counter
Program Counter High Byte PCL RegisterHT67F488 PC11~PC8 PCL7~PCL0HT67F489 PC1�~PC8 PCL7~PCL0
Program Counter
Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly.However,asonlythis lowbyteisavailableformanipulation, the jumpsare limited to thepresentpageofmemory, that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.
Rev. 1.60 �0 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackisorganizedinto8levelsandneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.Theactivatedlevel is indexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.
Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresultinastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.
Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.
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Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:
• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA,LADD,LADDM,LADC,LADCM,LSUB,LSUBM,LSBC,LSBCM,LDAA
• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA,LAND,LANDM,LOR,LORM,LXOR,LXORM,LCPL,LCPLA
• Rotation,RRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC,LRR,LRRA,LRRCA,LRRC,LRLA,LRLCA,LRLC
• IncrementandDecrement,INCA,INC,DECA,DEC,LINCA,LINC,LDECA,LDEC
• Branchdecision,JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI,LSNZ,LSZ,LSZA,LSIZ,LSDZ,LSIZA,LSDZA
Rev. 1.60 �1 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthisdeviceseriestheProgramMemoryisFlashtype,whichmeansitcanbeprogrammedandre-programmedalargenumberoftimes,allowingtheusertheconvenienceofcodemodificationonthesamedevice.Byusingtheappropriateprogrammingtools,theFlashdevicesofferuserstheflexibilitytoconvenientlydebuganddevelop their applicationswhilealsoofferingameansof fieldprogrammingandupdating.
StructureTheProgramMemoryhasacapacityof4K×16bits to8K×16bits.TheProgramMemory isaddressedbytheProgramCounterandalsocontainsdata, tableinformationandinterruptentries.Tabledata,whichcanbesetup inany locationwithin theProgramMemory, isaddressedbyaseparatetablepointerregister.
Device CapacityHT67F488 4K×16HT67F489 8K×16
Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000His reserved foruseby thedevice reset forprograminitialisation.Afteradevice reset isinitiated,theprogramwilljumptothislocationandbeginexecution.
0000H
0004H
002CH
FFFH
Reset
Interrupt Vector
16 bits
Reset
Interrupt Vector
16 bits
1FFFH
HT67F488 HT67F489
1000H
Program Memory Structure
Rev. 1.60 �� �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressof thelookupdatatoberetrievedinthetablepointerregister,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.
Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe“TABRD[m]”or“TABRDL[m]”instructionsrespectivelywhenthememory[m]islocatedincurrentpage.Ifthememory[m]islocatedinotherpages,thetabledatacanberetrievedfromtheProgramMemoryusingthe“LTABRD[m]”or“LTABRDL[m]”instructionsrespectively.Whentheinstructionisexecuted,thelowerordertablebytefromtheProgramMemorywillbetransferredtotheuserdefinedDataMemoryregister[m]asspecifiedintheinstruction.ThehigherordertabledatabytefromtheProgramMemorywillbetransferredtotheTBLHspecialregister.Anyunusedbitsinthistransferredhigherorderbytewillbereadas0.
Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.
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Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis“F00H”whichreferstothestartaddressofthelastpagewithinthe4KProgramMemoryoftheHT67F488device.Thetablepointerissetupheretohaveaninitialvalueof“06H”.ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress“F06H”or6locationsafterthestartofthelastpage.Notethatthevalueforthetablepointerisreferencedtothefirstaddressofthepresentpageifthe“TABRD[m]”or“LTABRD[m]”instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe“TABRD[m]”or“LTABRD[m]”instructionisexecuted.
Because theTBLHregister isa read/write registerandcanbe restored,care shouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Table Read Program Exampletempreg1 db ? ; temporary register #1 in current pagetempreg2 db ? ; temporary register #2 in current page::mov a,06h ; initialise low table pointer - note that this address is ; referenced to the last page or present pagemov tblp,a::tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempreg1 ; Data at program memory address “F06H” transferred to tempreg1 ; and TBLHdec tblp ; reduce value of table pointer by onetabrdl tempreg2 ; transfers value in table referenced by table pointer to tempreg2 ; Data at program memory address “F05H” transferred to tempreg2 ; and TBLH ; in this example the data “1AH” is transferred to tempreg1 and ; data “0FH” to register tempreg2 while the value “00H” will be ; transferred the high byte register TBLH::org 0F00h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh::
In Circuit Programming – ICPTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogramata laterstage.Thisenablesproductmanufacturers toeasilykeep theirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.
TheHoltekFlashMCUtoWriterProgrammingPincorrespondencetableisasfollows:
Holtek Writer Pins MCU Programming Pins Pin DescriptionICPDA PA0 P�og�a��ing Se�ial Data/Add�essICPCK PA� P�og�a��ing ClockVDD VDD Powe� SupplyVSS VSS G�ound
TheProgramMemoryandEEPROMdataMemorycanbothbeprogrammedseriallyin-circuitusingthis4-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditionallinefor theclock.Twoadditional linesarerequiredfor thepowersupply.The technicaldetailsregardingthein-circuitprogrammingofthedevicesarebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.
Rev. 1.60 �4 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Duringtheprogrammingprocess, takingcontrolof thePA0andPA2I/Opinsfordataandclockprogrammingpurposes.Theusermusttheretakecaretoensurethatnootheroutputsareconnectedtothesetwopins.
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Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1korthecapacitanceof*mustbelessthan1nF.
On-Chip Debug Support – OCDSThereisanEVchipnamedHT67V489whichisusedtoemulatetheHT67F488/HT67F489seriesofdevices.TheHT67V489devicealsoprovides the“On-ChipDebug” function todebug theHT67F488/HT67F489seriesofdevicesduringdevelopmentprocess.Thedevices,HT67F488/HT67F489andHT67V489,arealmostfunctionalcompatibleexceptthe“On-ChipDebug”functionandpackage types.Userscanuse theHT67V489device toemulate theHT67F488/HT67F489seriesofdevicesbehaviorsbyconnecting theOCDSDAandOCDSCKpins to theHoltekHT-IDEdevelopmenttools.TheOCDSDApinis theOCDSData/Addressinput/outputpinwhiletheOCDSCKpinistheOCDSclockinputpin.WhenusersusetheHT67V489EVchipfordebugging,thecorrespondingpinfunctionssharedwiththeOCDSDAandOCDSCKpinsintheHT67F488/HT67F489seriesofdeviceswillhavenoeffect in theHT67V489EVchip.However, the twoOCDSpinswhicharepin-sharedwiththeICPprogrammingpinsarestillusedastheFlashMemoryprogrammingpins for ICP.FormoredetailedOCDS information, refer to thecorrespondingdocumentnamed“Holteke-Linkfor8-bitMCUOCDSUser’sGuide”.
Holtek e-Link Pins EV Chip Pins Pin DescriptionOCDSDA OCDSDA On-chip De�ug Suppo�t Data/Add�ess input/outputOCDSCK OCDSCK On-chip De�ug Suppo�t Clock input
VDD VDD Powe� SupplyVSS VSS G�ound
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
RAM Data MemoryTheDataMemoryisan8-bitwideRAMinternalmemoryandis the locationwhere temporaryinformationisstored.
Dividedintotwotypes,thefirstofDataMemoryisanareaofRAMwherespecialfunctionregistersare located.Theseregistershavefixed locationsandarenecessary forcorrectoperationof thedevice.Manyof theseregisterscanbereadfromandwritten todirectlyunderprogramcontrol,however, someremainprotected fromusermanipulation.ThesecondareaofDataMemory isreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.
StructureTheDataMemory isdivided intoseveral sectors,allofwhichare implemented in8-bitwideMemory.EachoftheDataMemorysectorsiscategorizedintotwotypes,theSpecialPurposeDataMemoryandtheGeneralPurposeDataMemory.
ThestartaddressoftheSpecialPurposeDataMemoryforalldevicesistheaddress00HwhilethestartaddressoftheGeneralPurposeDataMemoryistheaddress80H.TheSpecialPurposeDataMemoryregistersareaccessible inallsectors,withtheexceptionof theEECregisterataddress40H,whichisonlyaccessibleinSector1.
Device Capacity Sectors
HT67F488HT67F489 Gene�al Pu�pose: �56×8
0: 80H~FFH1: 80H~93H (Fo� LCD)�: 80H~FFH
00H
7FH80H
FFH
Special Pu�pose Data Me�o�y
Gene�al Pu�pose Data Me�o�y
Secto� 0
Secto� 1
Secto� 1LCD Data Me�o�y
Secto� �
93H
40H: EEC(Only availa�le in Secto� 1 fo�
HT67F489)
Data Memory Structure
Rev. 1.60 �6 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Data Memory AddressingForthedevicesthatsupporttheextendedinstructions,thereisnoBankPointerforDataMemoryaddressing.ForDataMemorythedesiredSectorispointedbytheMP1HorMP2HregisterandthecertainDataMemoryaddressintheselectedsectorisspecifiedbytheMP1LorMP2Lregisterwhenusingindirectaddressingaccess.
DirectAddressingcanbeusedinallsectorsusingthecorrespondinginstructionwhichcanaddressallavailabledatamemoryspace.Fortheaccesseddatamemorywhichislocatedinanydatamemorysectorsexceptsector0, theextendedinstructionscanbeusedtoaccess thedatamemoryinsteadofusing the indirectaddressingaccess.Themaindifferencebetweenstandard instructionsandextendedinstructionsisthatthedatamemoryaddress“m”intheextendedinstructionshas10validbits,thehighbyteindicatesasectorandthelowbyteindicatesaspecificaddress.
General Purpose Data Memory Thereare256bytesofgeneralpurposememorywhicharearranged in80H~FFHofSector0,Sector2separately.Andanother20bytesofLCDmemoryaremappedin80H~93HofSector1.Allmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.Thegeneralpurposedatamemoryisfullyaccessiblebytheuserprogramforbothreadandwritingoperations.Byusingthe"SET[m].i"and"CLR[m].i"instructionsindividualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.
Special Purpose Data Memory This area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller, are stored.Theyareoverlapped inanysector.Mostof the registersarebothreadableandwritablebutsomeareprotectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunusedbefore80H,anyreadinstructiontotheseaddresseswillreturnthevalue"00H".
Rev. 1.60 �7 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
00H IAR001H MP00�H IAR103H MP1L04H05H ACC06H PCL07H TBLP08H TBLH09H TBHP0AH STATUS0BH
TM1AL
0CH
EEA
0DH
TM1DH
0EH
EED
0FH
PE
10H
TM0DL
11H
TM0DH
1�H
19H
WDTC
18H
TBC
1BH1AH
1DH1CH
1FH
LVDC
1EH
13H14H
TM0RPL
15H
TM0RPH
16H17H
TM1C0
Sector 0, 1
FSUBCI�TEGI�TC0
I�TC�MFI0MFI1
MFI3PAWUPAPU
PA
PBPUPB
PBC
ACERHTM0C0TM0C1
�0H�1H��H
�9H�8H
�BH�AH
�DH�CH
�FH�EH
�3H�4H�5H�6H�7H
30H31H3�H
39H38H
3BH3AH
3DH3CH
3FH3EH
33H34H35H36H37H
40H EEC41H USR4�H UCR143H
TM3DH
47H
TM3AL
48H
TM�DL49H
TM3AH
4AH4BH4CH4DH
TM3C14EH
TM3DL4FH50H51H5�H
58H
53H54H55H56H57H
Sector 0 Sector 1
TM�C0TM�C1
TM�DHTM�ALTM�AHTM3C0
60H61H
MP1H
IAR�MP�LMP�H
TM0ALTM0AH
TM1C1TM1DL
TM1AH
44H45H46H
59H5AH5BH5CH5DH5EH5FH
LCDC0LCDC1
SEGCR0SEGCR1SEGCR�
PCPUPC
PCCPDPU
PDPDC
6�H63H64H65H66H67H68H69H
PEPU
PECPFPU
PFPFC
6AH6BH
6DH6CH
6EH6FH
TMPC
70H71H7�H73H74H75H76H77H78H79H7AH7BH
7DH7CH
7EH7FH
: Unused� �ead as 00H
SMOD
CTRL
I�TC1
MFI�
PAC
ACERL
UCR�BRG
TXR/RXR
LVRC
IOHR0IOHR1MFI4
ADCR1
ADRLADRHADCR0
Special Purpose Data Memory
Rev. 1.60 �8 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsections,howeverseveralregistersrequireaseparatedescriptioninthissection.
Indirect Addressing Register – IAR0, IAR1, IAR2TheIndirectAddressingRegisters,IAR0,IAR1andIAR2,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.Themethodof indirectaddressing forRAMdatamanipulationuses these IndirectAddressingRegistersandMemoryPointers, incontrast todirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0,IAR1andIAR2registerswillresult innoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0,MP1L/MP1HorMP2L/MP2H.Actingasapair, IAR0andMP0cantogetheraccessdataonlyfromSector0while theIAR1register togetherwithMP1L/MP1HregisterpairandIAR2registertogetherwithMP2L/MP2HregisterpaircanaccessdatafromanyDataMemorysector.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof“00H”andwritingtotheregistersindirectlywillresultinnooperation.
Memory Pointers – MP0, MP1L, MP1H, MP2L, MP2HFiveMemoryPointers,knownasMP0,MP1L,MP1H,MP2LandMP2H,areprovided.TheseMemoryPointersarephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedtoistheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister, IAR0,areused toaccessdata fromSector0,whileMP1L/MP1HtogetherwithIAR1andMP2L/MP2HtogetherwithIAR2areusedtoaccessdatafromalldatasectorsaccordingtothecorrespondingMP1HorMP2Hregister.DirectAddressingcanbeusedinalldatasectorsusingthecorrespondinginstructionwhichcanaddressallavailabledatamemoryspace.
ThefollowingexampleshowshowtoclearasectoroffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Indirect Addressing Program Example 1data .section ‘data’adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code .section at 0 codeorg 00hstart:mov a, 04h ; setup size of blockmov block, amov a,offsetadres1 ;AccumulatorloadedwithfirstRAMaddressmov mp0,a ;setupmemorypointerwithfirstRAMaddressloop: clr IAR0 ;clearthedataataddressdefinedbyMP0inc mp0 ; increment memory pointersdz block ; check if last memory location has been clearedjmp loopcontinue:
Indirect Addressing Program Example 2data .section ´data´adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code .section at 0 code´org 00hstart:mov a, 04h ; setup size of blockmov block, amov a, 01h ; setup the memory sectormov mp1h, amova,offsetadres1 ;AccumulatorloadedwithfirstRAMaddressmovmp1l,a ;setupmemorypointerwithfirstRAMaddressloop:clrIAR1 ;clearthedataataddressdefinedbyMP1Lincmp1l ;incrementmemorypointerMP1Lsdz block ; check if last memory location has been clearedjmp loopcontinue:
Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Direct Addressing Program Example using extended instructionsdata .section ´data´temp db ? code .section at 0 code´org 00hstart:lmov a, [m] ; move [m] data to acclsub a, [m+1] ; compare [m] and [m+1] datasnz c ; [m]>[m+1]?jmp continue ; nolmov a, [m] ; yes, exchange [m] and [m+1] datamov temp, almov a, [m+1]lmov [m], amov a, templmov [m+1], acontinue:
Note:Here“m” isadatamemoryaddress located inanydatamemorysectors.Forexample,m=1F0H,itindicatesaddress0F0HinSector1.
Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuserdefinedregisterandanother, it isnecessary todo thisbypassingthedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.
Program Counter Low Register – PCL Toprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.
Rev. 1.60 31 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Look-up Table Registers – TBLP, TBHP, TBLH Thesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointerandindicates thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe“INC”or“DEC”instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.
Status Register – STATUS This8-bitregistercontainstheSCflag,CZflag,zeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.
WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe“CLRWDT”or“HALT”instruction.ThePDFflagisaffectedonlybyexecutingthe“HALT”or“CLRWDT”instructionorduringasystempower-up.
TheZ,OV,AC,C,SCandCZflagsgenerallyreflectthestatusofthelatestoperations.
• SCistheresultofthe“XOR”operationwhichisperformedbytheOVflagandtheMSBofthecurrentinstructionoperationresult.
• CZistheoperationalresultofdifferentflagsfordifferentinstuctions.Refertoregisterdefinitionsformoredetails.
• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.
• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.
• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.
• OVisset ifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.
• PDFisclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetbyexecutingthe“HALT”instruction.
• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOissetbyaWDTtime-out.
Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.
Rev. 1.60 3� �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
STATUS Register
Bit 7 6 5 4 3 2 1 0�a�e SC CZ TO PDF OV Z AC CR/W R/W R/W R R R/W R/W R/W R/WPOR x x 0 0 x x x x
“x” unknownBit7 SC:Theresultofthe“XOR”operationwhichisperformedbytheOVflagandthe
MSBoftheinstructionoperationresult.Bit6 CZ:Thetheoperationalresultofdifferentflagsfordifferentinstructions.
ForSUB/SUBM/LSUB/LSUBMinstructions,theCZflagisequaltotheZflag.ForSBC/SBCM/LSBC/LSBCMinstructions, theCZflag is the“AND”operationresultwhichisperformedbythepreviousoperationCZflagandcurrentoperationzeroflag.Forotherinstructions,theCZflagwillnotbeaffected.
Bit5 TO:WatchdogTime-Outflag0:Afterpoweruporexecutingthe“CLRWDT”or“HALT”instruction1:Awatchdogtime-outoccurred.
Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe“CLRWDT”instruction1:Byexecutingthe“HALT”instruction
Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.
Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero
Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction
Bit0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation
Cisalsoaffectedbyarotatethroughcarryinstruction.
Rev. 1.60 33 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
EEPROM Data MemoryTheHT67F489devicecontainsanareaof internalEEPROMDataMemory.EEPROM,whichstandsforElectricallyErasableProgrammableReadOnlyMemory,isbyitsnatureanon-volatileformofre-programmablememory,withdataretentionevenwhenitspowersupply is removed.Byincorporatingthiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproductidentificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproductinformationtobestoreddirectlywithin theproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.
EEPROM Data Memory StructureTheEEPROMDataMemorycapacity is64×8bitsfor thedevice.Unlike theProgramMemoryandRAMDataMemory, theEEPROMDataMemoryisnotdirectlymappedintomemoryspaceandisthereforenotdirectlyaddressableinthesamewayastheothertypesofmemory.ReadandWriteoperationstotheEEPROMarecarriedoutinsinglebyteoperationsusinganaddressanddataregisterinSector0andasinglecontrolregisterinSector1.
EEPROM RegistersThreeregisterscontrol theoveralloperationof the internalEEPROMDataMemory.Thesearetheaddressregister,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEAandEEDregistersarelocatedinSector0, theycanbedirectlyaccessedinthesamewasasanyotherSpecialFunctionRegister.TheEECregisterhowever,beinglocatedinSector1,cannotbedirectlyaddresseddirectlyandcanonlybereadfromorwrittentoindirectlyusingtheMP1L/MP1HMemoryPointerandIndirectAddressingRegister,IAR1.BecausetheEECcontrolregisterislocatedataddress40HinSector1,theMP1LMemoryPointerlowbytemustfirstbesettothevalue40HandtheMP1HMemoryPointerhighbyteset tothevalue01HbeforeanyoperationsontheEECregisterareexecuted.
EEPROM Register List
NameBit
7 6 5 4 3 2 1 0EEA — — D5 D4 D3 D� D1 D0EED D7 D6 D5 D4 D3 D� D1 D0EEC — — — — WRE� WR RDE� RD
EEA Register
Bit 7 6 5 4 3 2 1 0�a�e — — D5 D4 D3 D� D1 D0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0
Bit7~6 Unimplemented,readas“0”Bit5~0 D5~D0:DataEEPROMaddress
DataEEPROMaddressbit5~bit0
Rev. 1.60 34 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
EED Register
Bit 7 6 5 4 3 2 1 0�a�e D7 D6 D5 D4 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~0 D7~D0:DataEEPROMdataDataEEPROMdatabit7~bit0
EEC Register
Bit 7 6 5 4 3 2 1 0�a�e — — — — WRE� WR RDE� RDR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0
Bit7~4 Unimplemented,readas“0”Bit3 WREN:DataEEPROMWriteEnable
0:Disable1:Enable
This is theDataEEPROMWriteEnableBitwhichmustbesethighbeforeDataEEPROMwriteoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMwriteoperations.
Bit2 WR:EEPROMWriteControl0:Writecyclehasfinished1:Activateawritecycle
This is theDataEEPROMWriteControlBitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENhasnotfirstbeensethigh.
Bit1 RDEN:DataEEPROMReadEnable0:Disable1:EnableThis is theDataEEPROMReadEnableBitwhichmustbesethighbeforeDataEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.
Bit0 RD:EEPROMReadControl0:Readcyclehasfinished1:Activateareadcycle
This is theDataEEPROMReadControlBitandwhensethighbytheapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENhasnotfirstbeensethigh.
Note:TheWREN,WR,RDENandRDcannotbesetto“1”atthesametimeinoneinstruction.TheWRandRDcannotbesetto“1”atthesametime.
Rev. 1.60 35 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Reading Data from the EEPROMToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationif theRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.Theapplicationprogramcanpoll theRDbit todeterminewhenthedataisvalidforreading.
Writing Data to the EEPROMTheEEPROMaddressofthedatatobewrittenmustfirstbeplacedintheEEAregisterandthedataplacedintheEEDregister.TowritedatatotheEEPROM,thewriteenablebit,WREN,intheEECregistermustfirstbesethightoenablethewritefunction.Afterthis,theWRbitintheEECregistermustbe immediatelysethighto initiateawritecycle.These twoinstructionsmustbeexecutedconsecutively.Theglobal interruptbitEMIshouldalsofirstbeclearedbefore implementinganywriteoperations,andthensetagainafterthewritecyclehasstarted.SettingtheWRbithighwillnotinitiateawritecycleiftheWRENbithasnotbeenset.AstheEEPROMwritecycleiscontrolledusinganinternaltimerwhoseoperationisasynchronoustomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates,theWRbitwillbeautomaticallyclearedtozerobythemicrocontroller,informingtheuserthatthedatahasbeenwrittentotheEEPROM.TheapplicationprogramcanthereforepolltheWRbittodeterminewhenthewritecyclehasended.
Write ProtectionProtectionagainst inadvertentwriteoperation isprovided inseveralways.After thedevice ispowered-on theWriteEnablebit in thecontrol registerwillbeclearedpreventinganywriteoperations.Alsoatpower-onMP1L/MP1HandMP2L/MP2Hwillbereset tozero,whichmeansthatDataMemorySector0willbeselected.AstheEEPROMcontrolregisterislocatedinSector1,thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.
EEPROM InterruptTheEEPROMwriteinterruptisgeneratedwhenanEEPROMwritecyclehasended.TheEEPROMinterruptmustfirstbeenabledbysettingtheDEEbitintherelevantinterruptregister.HoweverastheEEPROMiscontainedwithinaMulti-functionInterrupt,theassociatedmulti-functioninterruptenablebitmustalsobeset.WhenanEEPROMwritecycleends, theDEFrequest flagand itsassociatedmulti-functioninterruptrequestflagwillbothbeset.Iftheglobal,EEPROMandMulti-function interruptsareenabledandthestackisnotfull,a jumpto theassociatedMulti-functionInterruptvectorwilltakeplace.WhentheinterruptisservicedonlytheMulti-functioninterruptflagwillbeautomaticallyreset, theEEPROMinterruptflagmustbemanuallyresetbytheapplicationprogram.MoredetailscanbeobtainedintheInterruptsection.
Rev. 1.60 36 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Programming ConsiderationsCaremustbe taken thatdata isnot inadvertentlywritten to theEEPROM.Protectioncanbeenhancedbyensuring that theWriteEnablebit isnormallycleared tozerowhennotwriting.Also theMemoryPointerhighbyte,MP1HorMP2H,couldbenormallyclearedtozeroas thiswouldinhibitaccesstoSector1wheretheEEPROMcontrolregisterexist.Althoughcertainlynotnecessary,considerationmightbegivenintheapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.WhenwritingdatatheWRbitmustbesethighimmediatelyaftertheWRENbithasbeensethigh,toensurethewritecycleexecutescorrectly.TheglobalinterruptbitEMIshouldalsobeclearedbeforeawritecycleisexecutedandthenre-enabledafter thewritecyclestarts.Notethat thedeviceshouldnotenter theIDLEorSLEEPmodeuntiltheEEPROMreadorwriteoperationis totallycomplete.Otherwise, theEEPROMreadorwriteoperationwillfail.
Programming Examples
Reading data from the EEPROM - polling methodMOV A,EEPROM_ADRES ;userdefinedaddressMOV EEA,AMOV A,040H ;setupmemorypointerMP1LMOV MP1L,A ;MP1pointstoEECregisterMOV A,01H ;setupmemorypointerMP1HMOV MP1H,ASET IAR1.1 ;setRDENbit,enablereadoperationsSET IAR1.0 ;startReadCycle-setRDbitBACK:SZ IAR1.0 ;checkforreadcycleendJMP BACKCLR IAR1 ;disableEEPROMread/writeCLR MP1HMOV A,EED ;movereaddatatoregisterMOV READ_DATA,A
Writing Data to the EEPROM - polling methodMOV A,EEPROM_ADRES ;userdefinedaddressMOV EEA,AMOV A,EEPROM_DATA ;userdefineddataMOV EED,AMOV A,040H ;setupmemorypointerMP1LMOV MP1L,A ;MP1pointstoEECregisterMOV A,01H ;setupmemorypointerMP1HMOV MP1H,ACLR EMISET IAR1.3 ;setWRENbit,enablewriteoperationsSET IAR1.2 ;startWriteCycle-setWRbit–executedimmediatelyafterset WRENbitSET EMIBACK:SZ IAR1.2 ;checkforwritecycleendJMP BACKCLR IAR1 ;disableEEPROMread/writeCLR MP1H
Rev. 1.60 37 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
OscillatorsVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughregisters.
Oscillator Overview Inadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfor theWatchdogTimerandTimeBaseInterrupts.Externaloscillators requiringsomeexternalcomponentsaswellasfullyintegratedinternaloscillators,requiringnoexternalcomponents,areprovided to formawiderangeofboth fastandslowsystemoscillators.Thehigher frequencyoscillators providehigherperformancebut carrywith it thedisadvantageof higherpowerrequirements,while theopposite isofcourse truefor the lowerfrequencyoscillators.With thecapabilityofdynamically switchingbetween fast andslowsystemclock, thedevicehas theflexibilitytooptimizetheperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.
Type Name Freq. PinsInte�nal High Speed RC HIRC 8MHz —Exte�nal High speed C�ystal HXT 400kHz~16MHz OSC1/OSC�Inte�nal Low Speed RC LIRC 3�kHz —Exte�nal Low Speed C�ystal LXT 3�.768kHz XT1/XT�
Oscillator Types
System Clock Configurations Therearefourmethodsofgeneratingthesystemclock,twohighspeedoscillatorsandtwolowspeedoscillators.Thehighspeedoscillatoraretheinternal8MHzRCoscillator-HIRCandtheexternalcrystal/ceramicoscillator-HXT.Thetwolowspeedoscillatorsaretheinternal32kHzRCoscillator-LIRCandtheexternal32.768kHzcrystaloscillator-LXT.Selectingwhethertheloworhighspeedoscillator isusedasthesystemoscillator isimplementedusingtheHLCLKbitandCKS2~CKS0bits in theSMODregisterandas thesystemclockcanbedynamicallyselected.Note that twooscillatorselectionsmustbemadenamelyonehighspeedandonelowspeedsystemoscillators.Itisnotpossibletochooseano-oscillatorselectionforeitherthehighorlowspeedoscillator.
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System Clock Configurations
Rev. 1.60 38 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
External Crystal/Ceramic Oscillator – HXTTheExternalCrystal/CeramicSystemOscillator isoneof thehighfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Formostcrystaloscillatorconfigurations, thesimpleconnectionofacrystalacrossOSC1andOSC2willcreatethenecessaryphaseshiftandfeedbackforoscillation,withoutrequiringexternalcapacitors.However,forsomecrystaltypesandfrequencies,toensureoscillation, itmaybenecessarytoaddtwosmallvaluecapacitors,C1andC2.Usingaceramicresonatorwillusuallyrequiretwosmallvaluecapacitors,C1andC2,tobeconnectedasshownforoscillationtooccur.ThevaluesofC1andC2shouldbeselectedinconsultationwiththecrystalorresonatormanufacturer'sspecification.Anadditionalconfigurationoptionmustbesetuptoconfigurethedeviceaccordingtowhethertheoscillatorfrequencyishigh,definedasequaltoorabove1MHz,orlow,whichisdefinedasbelow1MHz.
Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk, it isimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwith interconnectinglinesarealllocatedasclosetotheMCUaspossible.
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Crystal/Resonator Oscillator – HXT
Crystal Oscillator C1 and C2 Values
Crystal Frequency C1 C21�MHz 0pF 0pF8MHz 0pF 0pF4MHz 0pF 0pF1MHz 100pF 100pF
455kHz (see �ote�) 100pF 100pF�ote: 1. C1 and C� values a�e fo� guidance only.
2. XTAL mode configuration option: 455kHz.
Crystal Recommended Capacitor Values
Internal RC Oscillator – HIRC TheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.The internalRCoscillator has a fixed frequency of 8MHz.Device trimming during themanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethat theinfluenceof thepowersupplyvoltage, temperatureandprocessvariationsontheoscillationfrequencyareminimised.Notethatifthisinternalsystemclockoptionisselected,asitrequiresnoexternalpinsforitsoperation,I/OpinsarefreeforuseasnormalI/Opins.
Rev. 1.60 39 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
External 32.768kHz Crystal Oscillator – LXTTheExternal32.768kHzCrystalSystemOscillatorisoneofthelowfrequencyoscillatorchoices,whichisselectedviatheFSUBCregister.Thisclocksourcehasafixedfrequencyof32.768kHzandrequiresa32.768kHzcrystaltobeconnectedbetweenpinsXT1andXT2.Theexternalresistorandcapacitorcomponentsconnectedtothe32.768kHzcrystalarenecessarytoprovideoscillation.Forapplicationswhereprecisefrequenciesareessential,thesecomponentsmayberequiredtoprovidefrequencycompensationduetodifferentcrystalmanufacturingtolerances.Duringpower-upthereisatimedelayassociatedwiththeLXToscillatorwaitingforittostart-up.
WhenthemicrocontrollerenterstheSLEEPorIDLEMode,thesystemclockisswitchedofftostopmicrocontrolleractivityand toconservepower.However, inmanymicrocontrollerapplicationsitmaybenecessary tokeep the internal timersoperationalevenwhenthemicrocontroller is intheSLEEPorIDLEMode.Todothis,anotherclock, independentof thesystemclock,mustbeprovided.
However,forsomecrystals,toensureoscillationandaccuratefrequencygeneration,itisnecessarytoadd twosmallvalueexternalcapacitors,C1andC2.TheexactvaluesofC1andC2shouldbeselectedinconsultationwiththecrystalorresonatormanufacturerspecification.Theexternalparallelfeedbackresistor,RP,isrequired.
TheFSUBCregisterdeterminesiftheXT1/XT2pinsareusedfortheLXToscillatororasI/Opins.
• IftheLXToscillatorisnotusedforanyclocksource,theXT1/XT2pinscanbeusedasnormalI/Opins.
• IftheLXToscillatorisusedforanyclocksource,the32.768kHzcrystalshouldbeconnectedtotheXT1/XT2pins.
Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk, it isimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwithinterconnectinglinesarealllocatedasclosetotheMCUaspossible.
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External LXT Oscillator
LXT Oscillator C1 and C2 Values
Crystal Frequency C1 C23�.768kHz 10pF 10pF
�ote: 1. C1 and C� values a�e fo� guidance only.�. RP=5M~10MΩ is recommended.
32.768kHz Crystal Recommended Capacitor Values
Rev. 1.60 40 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LXT Oscillator Low Power Function TheLXToscillatorcanfunctioninoneoftwomodes,theQuickStartModeandtheLowPowerMode.ThemodeselectionisexecutedusingtheLXTLPbitintheFSUBCregister.
FSUBC Register
Bit 7 6 5 4 3 2 1 0�a�e LXTLP FSUB6 FSUB5 FSUB4 FSUB3 FSUB� FSUB1 FSUB0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 1 0 1 0 1 0
Bit7 LXTLP:LXTLowPowerControl0:QuickStartMode1:LowPowerMode
Bit6~0 FSUB6~FSUB0:fSUBclocksourceselection0101010:LIRC1010101:LXTOthers:MCUreset
Afterpoweron,theLXTLPbitwillbeautomaticallyclearedtozeroensuringthattheLXToscillatoris in theQuickStartoperatingmode.IntheQuickStartModetheLXToscillatorwillpowerupandstabilisequickly.However,after theLXToscillatorhas fullypoweredup itcanbeplacedintotheLow-powermodebysettingtheLXTLPbithigh.Theoscillatorwillcontinuetorunbutwithreducedcurrentconsumption,asthehighercurrentconsumptionisonlyrequiredduringtheLXToscillatorstart-up.Inpowersensitiveapplications,suchasbatteryapplications,wherepowerconsumptionmustbekepttoaminimum,itisthereforerecommendedthattheapplicationprogramsetstheLXTLPbithighabout2secondsafterpower-on.
Itshouldbenotedthat,nomatterwhatconditiontheLXTLPbit issetto, theLXToscillatorwillalwaysfunctionnormally,theonlydifferenceisthatitwilltakemoretimetostartupifintheLow-powermode.
Internal 32kHz Oscillator – LIRC TheInternal32kHzSystemOscillator isoneof the lowfrequencyoscillatorchoices,which isselectedviatheFSUBCregister.It isafullyintegratedRCoscillatorwithatypicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor its implementation.Device trimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandatatemperatureof25°Cdegrees,thefixedoscillationfrequencyof32kHzwillhaveatolerancewithin10%.
Rev. 1.60 41 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Operating Modes and System Clocks Presentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcoursevice-versa, lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovidedthesedeviceswithbothhighandlowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically,theusercanoptimisetheoperationoftheirmicrocontrollertoachievethebestperformance/powerratio.
System Clocks ThedevicehasmanydifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byprovidingtheuserwithawiderangeofclockoptionsusingconfigurationoptionsandregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.
Themainsystemclock,cancomefromeitherahighfrequencyfHor lowfrequencyfSUBsource,andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.ThehighspeedsystemclockcanbesourcedfromtheHIRC/HXToscillator.ThelowspeedsystemclocksourcecanbesourcedfrominternalclockfSUB.IffSUBisselectedthenitcanbesourcedbyeithertheLXTorLIRCoscillator,selectedbytheFSUB6~FSUB0bitsintheFSUBCregister.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.
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System Clock Configuration
Note:When thesystemclocksourcefSYS isswitched to fSUB fromfH, thehighspeedoscillationwill stop toconservethepower.ThusthereisnofH~fH/64forperipheralcircuittouse.
Rev. 1.60 4� �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
System Operation Modes There are six differentmodesof operation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingfourmodes,theSLEEP0,SLEEP1, IDLE0andIDLE1Modeareusedwhen themicrocontrollerCPUisswitchedoff toconservepower.
Operating ModeDescription
CPU fSYS fSUB fTBC
�ORMAL Mode On fH~fH/64 On OnSLOW Mode On fSUB On OnIDLE0 Mode Off Off On OnIDLE1 Mode Off On On On
SLEEP0 Mode Off Off Off OffSLEEP1 Mode Off Off On Off
NORMAL Mode Asthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbyoneofthehighspeedoscillators.ThismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromthehighspeedoscillatorHIRC/HXT.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64, theactualratiobeingselectedbytheCKS2~CKS0andHLCLKbitsintheSMODregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.
SLOW Mode Thisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.Theclocksourceusedwillbefromoneofthelowspeedoscillators,eithertheLXTortheLIRC.Runningthemicrocontrollerinthismodeallowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode,thefHisoff.
SLEEP0 ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregister is low.IntheSLEEP0modetheCPUwillbestopped,andthefSUBclockwillbestoppedtoo,andtheWatchdogTimerfunctionisdisabled.Inthismode,theLVDENismustsetto“0”.IftheLVDENissetto“1”,itwon’tentertheSLEEP0Mode.
SLEEP1 ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterislow.IntheSLEEP1modetheCPUwillbestopped.HoweverthefSUBclockwillcontinuetooperateiftheLVDENis“1”ortheWatchdogTimerfunctionisenabled.
IDLE0 Mode TheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterislow.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPU,thesystemoscillatorwillbestopped,thelowfrequencyclockfSUBwillbeon.
Rev. 1.60 43 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
IDLE1 Mode TheIDLE1ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPU,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.IntheIDLE1ModethelowfrequencyclockfSUBwillbeon.
Note: IfLVDEN=1and theSLEEPor IDLEmode isentered, theLVDandbandgapfunctionswillnotbedisabled,andthefSUBclockwillbeforcedtobeenabled.Insleepmode,otherperipheralwilldisableexceptWDT,LVDifenableinSLEEP1.
Control RegisterAsingleregister,SMOD,isusedforoverallcontroloftheinternalclockswithinthedevice.
SMOD Register
Bit 7 6 5 4 3 2 1 0�a�e CKS� CKS1 CKS0 — LTO HTO IDLE� HLCLKR/W R/W R/W R/W — R R R/W R/WPOR 0 0 0 — 0 0 1 1
Bit7~5 CKS2~CKS0:ThesystemclockselectionwhenHLCLKis“0”000:fSUB(fLXTorfLIRC)001:fSUB(fLXTorfLIRC)010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2
Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.Inadditiontothesystemclocksource,whichcanbeeithertheLXTorLIRC,adividedversionof thehighspeedsystemoscillatorcanalsobechosenas thesystemclocksource.
Bit4 Unimplemented,readas“0”Bit3 LTO:Lowspeedsystemoscillatorreadyflag
0:Notready1:Ready
Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeedsystemoscillator isstableafterpoweronresetorawake-uphasoccurred.TheflagwillbelowwhenintheSLEEP0Modebutafterawake-uphasoccurred,theflagwillchangetoahighlevelafter1024clockcyclesif theLXToscillatorisusedand1~2clockcyclesiftheLIRCoscillatorisused.
Bit2 HTO:Highspeedsystemoscillatorreadyflag0:Notready1:Ready
Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstable.Thisflagisclearedto“0”byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas“1”bytheapplicationprogramafterdevicepower-on.TheflagwillbelowwhenintheSLEEPorIDLE0Modebutafterawake-uphasoccurred,theflagwillchangetoahighlevelafter15~16clockcyclesif theHIRC/HXToscillatorisused.
Rev. 1.60 44 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Bit1 IDLEN:IDLEModecontrol0:Disable1:Enable
This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthedevicewillenter theIDLEMode. In theIDLE1Mode theCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstopinIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALTinstructionisexecuted.
Bit0 HLCLK:Systemclockselection0:fH/2~fH/64orfSUB1:fH
Thisbit isused toselect if the fHclockor the fH/2~fH/64or fSUBclock isusedasthesystemclock.Whenthebit ishigh thefHclockwillbeselectedandif lowthefH/2~fH/64or fSUBclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefSUBclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.
CTRL Register
Bit 7 6 5 4 3 2 1 0�a�e FSYSO� — — — FSUBF LVRF LRF WRFR/W R/W — — — R/W R/W R/W R/WPOR 0 — — — 0 x 0 0
“x” unknownBit7 FSYSON:fSYSControlinIDLEMode
0:Disable1:Enable
Bit6~4 Unimplemented,readas“0”Bit3 FSUBF:FSUBCControlregistersoftwareresetflag
0:Notoccur1:Occurred
Thisbit isset to1 if theFSUB6~FSUB0bits in theFSUBCregistercontainsanyundefinedvalues.Thisbitcanonlybeclearedto0bytheapplicationprogram.
Bit2 LVRF:LVRfunctionresetflag0:Notoccur1:Occurred
Thisbitissetto1whenaspecificLowVoltageResetsituationconditionoccurs.Thisbitcanonlybeclearedto0bytheapplicationprogram.
Bit1 LRF:LVRControlregistersoftwareresetflag0:Notoccur1:Occurred
Thisbitissetto1iftheLVRCregistercontainsanynondefinedLVRvoltageregistervalues.Thisineffectactslikeasoftwareresetfunction.Thisbitcanonlybeclearedto0bytheapplicationprogram.
Bit0 WRF:WDTControlregistersoftwareresetflag0:Notoccur1:Occurred
Thisbit isset to1by theWDTControlregistersoftwareresetandclearedby theapplicationprogram.Note that thisbitcanonlybecleared to0by theapplicationprogram.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Operating Mode Switching Thedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.
Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionof theIDLENbit in theSMODregisterandFSYSONintheCTRLregister.
WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfSUB.IftheclockisfromthefSUB,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofotherinternalfunctionssuchastheTMs.Theaccompanyingflowchartshowswhathappenswhenthedevicemovesbetweenthevariousoperatingmodes.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
NORMAL Mode to SLOW Mode Switching WhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower,thesystemclockcanswitchtorunintheSLOWModebysettheHLCLKbitto“0”andsettheCKS2~CKS0bitsto“000”or“001”intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.
TheSLOWModeissourcedfromtheLXTor theLIRCoscillatorsandthereforerequires theseoscillatorstobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.
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SLOW Mode to NORMAL Mode Switching InSLOWModethesystemuseseither theLXTorLIRClowspeedsystemoscillator.ToswitchbacktotheNORMALMode,wherethehighspeedsystemoscillatorisused,theHLCLKbitshouldbeset to“1”orHLCLKbit is“0”,butCKS2~CKS0isset to“010”,“011”,“100”,“101”,“110”or“111”.Asacertainamountof timewillberequiredfor thehighfrequencyclocktostabilise,thestatusoftheHTObitischecked.Theamountoftimerequiredforhighspeedsystemoscillatorstabilizationdependsuponwhichhighspeedsystemoscillatortypeisused.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Entering the SLEEP0 Mode ThereisonlyonewayforthedevicetoentertheSLEEP0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDTandLVDbothoff.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• Thesystemclock,WDTclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.• TheWDTwillbeclearedandstopped.• TheI/Oportswillmaintaintheirpresentconditions.• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.
Entering the SLEEP1 Mode ThereisonlyonewayforthedevicetoentertheSLEEP1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDTorLVDon.When this instruction isexecutedunder theconditionsdescribedabove, thefollowingwilloccur:
• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction,buttheWDTorLVDwillremainwiththeclocksourcecomingfromthefSUBclock.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.• TheWDTwillbeclearedandresumecountingiftheWDTisenabled.• TheI/Oportswillmaintaintheirpresentconditions.• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.
Entering the IDLE0 Mode ThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinCTRLregisterequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• The systemclockwill be stoppedand the applicationprogramwill stopat the “HALT”instruction,buttheTimeBaseclockfTBCandfSUBclockwillbeon.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.• TheWDTwillbeclearedandresumecountingiftheWDTisenabled.• TheI/Oportswillmaintaintheirpresentconditions.• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.
Entering the IDLE1 Mode ThereisonlyonewayforthedevicetoentertheIDLE1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinCTRLregisterequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• Thesystemclock,TimeBaseclockfTBCandfSUBclockwillbeonandtheapplicationprogramwillstopatthe“HALT”instruction.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
• TheWDTwillbeclearedandresumecountingiftheWDTisenabled.• TheI/Oportswillmaintaintheirpresentconditions.• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.
Standby Current Considerations AsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicetoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerifthepowerconsumptionistobeminimised.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeunbonbedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.
Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuits thatdonotdrawcurrent,suchasotherCMOSinputs.Alsonote thatadditionalstandbycurrentwillalsoberequiredifenabledtheLXTorLIRCoscillator.
IntheIDLE1Modethesystemoscillatorison,ifthesystemoscillatorisfromthehighspeedsystemoscillator,theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.
Wake-up AfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:
• AnexternalfallingedgeonPortA
• Asysteminterrupt
• AWDToverflow
IfthedeviceiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiated.Althoughbothofthesewake-upmethodswillinitiatearesetoperation,theactualsourceofthewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflagisclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe“HALT”instruction.TheTOflagisset ifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.
EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.
Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheinternalclock,fSUB,thefSUBclockissourcedfromLIRCorLXToscillatorselectedbytheFSUBCregister.TheWatchdogTimersourceclockisthensubdividedbyaratioof28to218togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.TheLIRCinternaloscillatorhasanapproximateperiodof32kHzatasupplyvoltageof5V.However,itshouldbenotedthatthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.TheLXToscillatorissuppliedbyanexternal32.768kHzcrystal.
Watchdog Timer Control RegisterAsingle register,WDTC,controls the required timeoutperiodaswell as theenable/disableoperation.
WDTC Register
Bit 7 6 5 4 3 2 1 0�a�e WE4 WE3 WE� WE1 WE0 WS� WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1
Bit7~3 WE4~WE0:WDTfunctionsoftwarecontrol10101:Disable01010:EnableOthers:ResetMCU
Whenthesebitsarechangedbytheenvironmentalnoisetoresetthemicrocontroller,theresetoperationwillbeactivatedafteradelaytime,tSRESETandtheWRFbitintheCTRLregisterwillbesetto1.
Bit2~0 WS2~WS0:WDTtime-outperiodselection000:28/fSUB
001:210/fSUB
010:212/fSUB
011:214/fSUB
100:215/fSUB
101:216/fSUB
110:217/fSUB
111:218/fSUB
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
CTRL Register
Bit 7 6 5 4 3 2 1 0�a�e FSYSO� — — — FSUBF LVRF LRF WRFR/W R/W — — — R/W R/W R/W R/WPOR 0 — — — 0 x 0 0
“x” unknownBit7 FSYSON:fSYSControlinIDLEMode
Describedelsewhere.Bit6~4 Unimplemented,readas“0”Bit3 FSUBF:FSUBCControlregistersoftwareresetflag
Describedelsewhere.Bit2 LVRF:LVRfunctionresetflag
Describedelsewhere.Bit1 LRF:LVRControlregistersoftwareresetflag
Describedelsewhere.Bit0 WRF:WDTControlregistersoftwareresetflag
0:Notoccur1:Occurred
Thisbit isset to1by theWDTControl registersoftwareresetandclearedby theapplicationprogram.Note that thisbitcanonlybecleared to0by theapplicationprogram.
Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.WithregardtotheWatchdogTimerenable/disablefunction,therearealsofivebits,WE4~WE0,intheWDTCregister toofferadditionalenable/disableandresetcontrolof theWatchdogTimer.TheWDTfunctionwillbedisabledwhentheWE4~WE0bitsaresettoavalueof10101B.TheWDTfunctionwillbeenablediftheWE4~WE0bitsvalueisequalto01010B.IftheWE4~WE0bitsaresettoanyothervaluesbytheenvironmentalnoiseorsoftwaresetting,except01010Band10101B,itwillresetthedeviceafteradelaytime,tSRESET.Afterpoweronthesebitswillhavethevalueof01010B.
WE4 ~ WE0 Bits WDT Function10101B Disa�le01010B Ena�leAny othe� value Reset MCU
Watchdog Timer Enable/Disable Control
Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTreset,whichmeansacertainvalueexcept01010Band10101BwrittenintotheWE4~WE0bitfiled, thesecondisusingtheWatchdogTimersoftwareclear instructionsandthethirdisviaaHALTinstruction.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethesingle“CLRWDT”instructiontocleartheWDT.
Themaximumtimeoutperiod iswhenthe218divisionratio isselected.Asanexample,witha32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8secondforthe218divisionratio,andaminimumtimeoutof8msforthe28divisionration.
“CLR WDT”Instruction
8-stage Divider WDT Prescaler
WE4~WE0 bitsWDTC Register Reset MCU
LXT fSUB fSUB/28
8-to-1 MUX
CLR
WS2~WS0(fSUB/28 ~ fSUB/218)
WDT Time-out(28/fSUB ~ 218/fSUB)
LIRC
MUX
FSUBCFSUB6~FSUB0 bits
Watchdog Timer
Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.
AnothertypeofresetiswhentheWatchdogTimeroverflowsandresets.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullreset is implementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.
Reset Functions Therearefourwaysinwhicharesetcanoccur,througheventsoccurringinternally.
Power-on Reset Themostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/OportandportcontrolregisterswillpowerupinahighconditionensuringthatallI/Oportswillbefirstsettoinputs.
VDD
Powe�-on Reset
SST Ti�e-out
tRSTD
Note:tRSTDispower-ondelay,typicaltime=50msPower-On Reset Timing Chart
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Low Voltage Reset — LVR Themicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevice.TheLVRfunctionisalwaysenabledwithaspecificLVRvoltageVLVR.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyresetthedeviceinternallyandtheLVRFbitintheCTRLregisterwillalsobesetto1.ForavalidLVRsignal,alowsupplyvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexistfora timegreater thanthatspecifiedbytLVRintheLVD&LVRElectricalCharacteristics.Ifthelowsupplyvoltagestatedoesnotexceedthisvalue,theLVRwillignorethelowsupplyvoltageandwillnotperformaresetfunction.TheactualVLVRvaluecanbeselectedbytheLVSbitsintheLVRCregister.If theLVS7~LVS0bitsarechangedtosomecertainvaluesbytheenvironmentalnoiseorsoftwaresetting,theLVRwillresetthedeviceafteradelaytime,tSRESET.Whenthishappens,theLRFbitintheCTRLregisterwillbesetto1.Afterpowerontheregisterwillhavethevalueof01010101B.NotethattheLVRfunctionwillbeautomaticallydisabledwhenthedeviceentersthepowerdownmode.
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Note:tRSTDispower-ondelay,typicaltime=50msLow Voltage Reset Timing Chart
• LVRC Register
Bit 7 6 5 4 3 2 1 0�a�e LVS7 LVS6 LVS5 LVS4 LVS3 LVS� LVS1 LVS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 1 0 1
Bit7~0 LVS7~LVS0:LVRvoltageselect01010101:2.1V00110011:2.55V10011001:3.15V10101010:3.8VAnyothervalue:GeneratesMCUreset--LVRCregisterisresettoPORvalue
Whenanactuallowvoltageconditionoccurs,asspecifiedbyoneofthefourdefinedLVRvoltagevaluesabove,anMCUresetwillbegenerated.The resetoperationwillbeactivatedafterthelowvoltageconditionkeepsmorethanatLVRtime.Inthissituationtheregistercontentswillremainthesameaftersucharesetoccurs.Anyregistervalue,otherthanthefourdefinedLVRvaluesabove,willalsoresultinthegenerationofanMCUreset.Theresetoperationwillbeactivatedafteradelaytime,tSRESET.HoweverinthissituationtheregistercontentswillberesettothePORvalue.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
• CTRL Register
Bit 7 6 5 4 3 2 1 0�a�e FSYSO� — — — FSUBF LVRF LRF WRFR/W R/W — — — R/W R/W R/W R/WPOR 0 — — — 0 x 0 0
“x” unknownBit7 FSYSON:fSYSControlinIDLEMode
Describedelsewhere.Bit6~4 Unimplemented,readas“0”Bit3 FSUBF:FSUBCControlregistersoftwareresetflag
Describedelsewhere.Bit2 LVRF:LVRfunctionresetflag
0:Notoccur1:Occurred
Thisbitcanbeclearto“0”,butcannotsetto“1”.Bit1 LRF:LVRControlregistersoftwareresetflag
0:Notoccur1:Occurred
Thisbitissetto1iftheLVRCregistercontainsanynondefinedLVRvoltageregistervalues.Thisineffectactslikeasoftwareresetfunction.Thisbitcanonlybeclearedto0bytheapplicationprogram.
Bit0 WRF:WDTControlregistersoftwareresetflagDescribedelsewhere.
Watchdog Time-out Reset during Normal Operation TheWatchdogtime-outResetduringnormaloperationis thesameasLVRresetexcept that theWatchdogtime-outflagTOwillbesetto"1".
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Note:tRSTDispower-ondelay,typicaltime=16.7msWDT Time-out Reset during Normal Operation Timing Chart
Watchdog Time-out Reset during SLEEP or IDLE Mode TheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto“0”andtheTOflagwillbesetto“1”.RefertotheA.C.CharacteristicsfortSSTdetails.
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Note:ThetSSTis15~16clockcyclesifthesystemclocksourceisprovidedbyHIRC/HXT.ThetSSTis1024clockforLXT.ThetSSTis1~2clockforLIRC.
WDT Time-out Reset during Sleep or IDLE Timing Chart
Rev. 1.60 55 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Reset Initial Conditions Thedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:
TO PDF Reset Conditions0 0 Powe�-on �esetu u LVR �eset du�ing �o��al o� SLOW Mode ope�ation1 u WDT ti�e-out �eset du�ing �o��al o� SLOW Mode ope�ation1 1 WDT ti�e-out �eset du�ing IDLE o� SLEEP Mode ope�ation
�ote: “u” stands fo� unchangedThefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.
Item Condition after ResetP�og�a� Counte� Reset to ze�oInte��upts All inte��upts will �e disa�ledWDT Clea� afte� �eset� WDT �egins countingTi�e�/Event Counte� Ti�e� Counte� will �e tu�ned offInput/Output Po�ts I/O po�ts will �e setup as inputs and A�0~A�9 as A/D input pinsStack Pointe� Stack Pointe� will point to the top of the stack
Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachof themicrocontroller internalregisters.Note thatwheremorethanonepackagetypeexiststhetablewillreflectthesituationforthelargerpackagetype.
Register Power On Reset LVR Reset WDT Time-out(Normal Operation)
WDT Time-out(HALT)
IAR0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuuMP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuuIAR1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuuMP1L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuuMP1H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuuIAR� xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuuMP�L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuuMP�H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuuACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuuPCL 0000 0000 0000 0000 0000 0000 0000 0000TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuuTBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuuTBHP ---x xxxx ---u uuuu ---u uuuu ---u uuuuSTATUS xx00 xxxx uuuu uuuu uu1u uuuu uu11 uuuuSMOD 000- 0011 000- 0011 000- 0011 uuu- uuuuLVDC --00 -000 --00 -000 --00 -000 --uu -uuuLVRC 0101 0101 0101 0101 0101 0101 uuuu uuuuCTRL 0--- 0x00 0--- uuuu 0--- uuuu 0--- uuuuI�TEG 0000 0000 0000 0000 0000 0000 uuuu uuuu
Rev. 1.60 56 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Register Power On Reset LVR Reset WDT Time-out(Normal Operation)
WDT Time-out(HALT)
WDTC 0101 0011 0101 0011 0101 0011 uuuu uuuuTBC 0011 -111 0011 -111 0011 -111 uuuu -uuuI�TC0 -000 0000 -000 0000 -000 0000 -uuu uuuuI�TC1 0000 0000 0000 0000 0000 0000 uuuu uuuuI�TC� -000 -000 -000 -000 -000 -000 -uuu -uuuMFI0 --00 --00 --00 --00 --00 --00 --uu --uuMFI1 --00 --00 --00 --00 --00 --00 --uu --uuMFI� --00 --00 --00 --00 --00 --00 --uu --uuMFI3 --00 --00 --00 --00 --00 --00 --uu --uuPAWU 0000 0000 0000 0000 0000 0000 uuuu uuuuPAPU 0000 0000 0000 0000 0000 0000 uuuu uuuuPA 1111 1111 1111 1111 1111 1111 uuuu uuuuPAC 1111 1111 1111 1111 1111 1111 uuuu uuuuPBPU --00 0000 --00 0000 --00 0000 --uu uuuuPB --11 1111 --11 1111 --11 1111 --uu uuuuPBC --11 1111 --11 1111 --11 1111 --uu uuuuPCPU 0000 0000 0000 0000 0000 0000 uuuu uuuuPC 1111 1111 1111 1111 1111 1111 uuuu uuuuPCC 1111 1111 1111 1111 1111 1111 uuuu uuuuPDPU 0000 0000 0000 0000 0000 0000 uuuu uuuuPD 1111 1111 1111 1111 1111 1111 uuuu uuuuPDC 1111 1111 1111 1111 1111 1111 uuuu uuuuPEPU 0000 0000 0000 0000 0000 0000 uuuu uuuuPE 1111 1111 1111 1111 1111 1111 uuuu uuuuPEC 1111 1111 1111 1111 1111 1111 uuuu uuuuPFPU 0000 ---- 0000 ---- 0000 ---- uuuu ----PF 1111 ---- 1111 ---- 1111 ---- uuuu ----PFC 1111 ---- 1111 ---- 1111 ---- uuuu ----TMPC ---0 0000 ---0 0000 ---0 0000 ---u uuuuIOHR0 0000 0000 0000 0000 0000 0000 uuuu uuuuIOHR1 0000 0000 0000 0000 0000 0000 uuuu uuuuADRL (ADRFS=0) xxxx ---- xxxx ---- xxxx ---- uuuu ----ADRL (ADRFS=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuuADRH (ADRFS=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuuADRH (ADRFS=1) ---- xxxx ---- xxxx ---- xxxx ---- uuuuADCR0 0110 0000 0110 0000 0110 0000 uuuu uuuuADCR1 00-0 -000 00-0 -000 00-0 -000 uu-u -uuuACERL 1111 1111 1111 1111 1111 1111 uuuu uuuuACERH ---- --11 ---- --11 ---- --11 ---- --uu
Rev. 1.60 57 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Register Power On Reset LVR Reset WDT Time-out(Normal Operation)
WDT Time-out(HALT)
TM0C0 0000 0--- 0000 0--- 0000 0--- uuuu u---TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuuTM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuuTM0DH ---- --00 ---- --00 ---- --00 ---- --uuTM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuuTM0AH ---- --00 ---- --00 ---- --00 ---- --uuTM0RPL 0000 0000 0000 0000 0000 0000 uuuu uuuuTM0RPH ---- --00 ---- --00 ---- --00 ---- --uuTM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuuTM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuuTM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuuTM1DH ---- --00 ---- --00 ---- --00 ---- --uuTM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuuTM1AH ---- --00 ---- --00 ---- --00 ---- --uuTM�C0 0000 0000 0000 0000 0000 0000 uuuu uuuuTM�C1 0000 0000 0000 0000 0000 0000 uuuu uuuuTM�DL 0000 0000 0000 0000 0000 0000 uuuu uuuuTM�DH ---- --00 ---- --00 ---- --00 ---- --uuTM�AL 0000 0000 0000 0000 0000 0000 uuuu uuuuTM�AH ---- --00 ---- --00 ---- --00 ---- --uuTM3C0 0000 0000 0000 0000 0000 0000 uuuu uuuuTM3C1 0000 0000 0000 0000 0000 0000 uuuu uuuuTM3DL 0000 0000 0000 0000 0000 0000 uuuu uuuuTM3DH ---- --00 ---- --00 ---- --00 ---- --uuTM3AL 0000 0000 0000 0000 0000 0000 uuuu uuuuTM3AH ---- --00 ---- --00 ---- --00 ---- --uuFSUBC 0010 1010 0010 1010 0010 1010 uuuu uuuuLCDC0 0000 -000 0000 -000 0000 -000 uuuu -uuuLCDC1 000- 0000 000- 0000 000- 0000 uuu- uuuuSEGCR0 0000 0000 0000 0000 0000 0000 uuuu uuuuSEGCR1 0000 0000 0000 0000 0000 0000 uuuu uuuuSEGCR� ---- 0000 ---- 0000 ---- 0000 ---- uuuuEEA --00 0000 --00 0000 --00 0000 --uu uuuuEED 0000 0000 0000 0000 0000 0000 uuuu uuuuEEC ---- 0000 ---- 0000 ---- 0000 ---- uuuuUSR 0000 1011 0000 1011 0000 1011 uuuu uuuuUCR1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuuUCR� 0000 0000 0000 0000 0000 0000 uuuu uuuuBRG xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuuTXR/RXR xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
Note:“u”standsforunchanged“x”standsforunknown“-”standsforunimplemented
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Input/Output Ports HoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.
Thedeviceprovidesbidirectionalinput/outputlineslabeledwithportnamesPA~PF.TheseI/Oportsaremappedto theRAMDataMemorywithspecificaddressesasshownin theSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.
I/O Register List
Register Name
Bit
7 6 5 4 3 2 1 0PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU� PAWU1 PAWU0PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU� PAPU1 PAPU0
PA PA7 PA6 PA5 PA4 PA3 PA� PA1 PA0PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC� PAC1 PAC0
PBPU — — PBPU5 PBPU4 PBPU3 PBPU� PBPU1 PBPU0PB — — PB5 PB4 PB3 PB� PB1 PB0
PBC — — PBC5 PBC4 PBC3 PBC� PBC1 PBC0PCPU PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU� PCPU1 PCPU0
PC PC7 PC6 PC5 PC4 PC3 PC� PC1 PC0PCC PCC7 PCC6 PCC5 PCC4 PCC3 PCC� PCC1 PCC0
PDPU PDPU7 PDPU6 PDPU5 PDPU4 PDPU3 PDPU� PDPU1 PDPU0PD PD7 PD6 PD5 PD4 PD3 PD� PD1 PD0
PDC PDC7 PDC6 PDC5 PDC4 PDC3 PDC� PDC1 PDC0PEPU PEPU7 PEPU6 PEPU5 PEPU4 PEPU3 PEPU� PEPU1 PEPU0
PE PE7 PE6 PE5 PE4 PE3 PE� PE1 PE0PEC PEC7 PEC6 PEC5 PEC4 PEC3 PEC� PEC1 PEC0
PFPU PFPU7 PFPU6 PFPU5 PFPU4 — — — —PF PF7 PF6 PF5 PF4 — — — —
PFC PFC7 PFC6 PFC5 PFC4 — — — —
“—”:Unimplemented,readas“0”PAWUn:PAwake-upfunctioncontrol
0:Disable1:Enable
PAn/PBn/PCn/PDn/PEn/PFn:I/ODatabit0:Data01:Data1
PACn/PBCn/PCCn/PDCn/PECn/PFCn:I/Otypeselection0:Output1:Input
PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn:Pull-highfunctioncontrol0:Disable1:Enable
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregistersPAPU~PFPU,andare implementedusingweakPMOStransistors.
Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.
PAWU Register
Bit 7 6 5 4 3 2 1 0�a�e PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU� PAWU1 PAWU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~0 PAWU7~PAWU0:PortAbit7~bit0Wake-upControl0:Disable1:Enable
I/O Port Control RegistersEach I/Oport has itsowncontrol registerknownasPAC~PFC, to control the input/outputconfiguration.With this control register, eachCMOSoutput or input canbe reconfigureddynamicallyundersoftwarecontrol.Eachpinof theI/Oports isdirectlymappedtoabit in itsassociatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthecontrolregistermustbewrittenasa“1”.Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.
Pin-shared FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Forthesepins,thechosenfunctionofthemulti-functionI/Opinsisselectedbyaseriesofregistersviatheapplicationprogramcontrol.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
I/O Pin StructuresTheaccompanyingdiagrams illustrate the internalstructuresofsomegeneric I/Opin types.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.
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Generic Input/Output Structure
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A/D Input/Output Structure
Rev. 1.60 61 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Programming Considerations Withintheuserprogram,oneofthefirstthingstoconsiderisportinitialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate, thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregisters,PAC~PFC,arethenprogrammedtosetupsomepinsasoutputs,theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregisters,PA~PF,arefirstprogrammed.Selectingwhichpinsare inputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvaluesintotheappropriateportcontrolregisterorbyprogrammingindividualbits intheportcontrolregisterusingthe“SET[m].i”and“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.
PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.
Rev. 1.60 6� �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdeviceistheabilitytocontrolandmeasuretime.Toimplement timerelatedfunctionseachdeviceincludesseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeingthefunctionalunitforthegenerationofPWMsignals.EachoftheTMshastwoindividual interrupts.Theadditionof inputandoutputpins foreachTMensures thatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.
ThecommonfeaturesofthedifferentTMtypesaredescribedherewithmoredetailedinformationprovidedintheindividualCompactandPeriodicTMsections.
IntroductionThesedevicescontainfourTMshavinga referencenameofTM0,TM1,TM2andTM3.EachindividualTMcanbecategorisedasacertaintype,namelyCompactTypeTMorPeriodicTypeTM.Althoughsimilarinnature, thedifferentTMtypesvaryintheirfeaturecomplexity.Thecommonfeatures toallof theCompactandPeriodicTMswillbedescribed in thissection, thedetailedoperationregardingeachoftheTMtypeswillbedescribedinseparatesections.ThemainfeaturesanddifferencesbetweenthetwotypesofTMsaresummarisedintheaccompanyingtable.
Function CTM PTMTi�e�/Counte� √ √I/P Captu�e — √Co�pa�e Match Output √ √PWM Channels 1 1Single Pulse Output — 1PWM Align�ent Edge EdgePWM Adjust�ent Pe�iod & Duty Duty o� Pe�iod Duty o� Pe�iod
TM Function Summary
ThischipcontainsaspecificnumberofeitherCompactTypeandPeriodicTypeTMunitswhichareshowninthetabletogetherwiththeirindividualreferencenames,TM0~TM3.
TM0 TM1 TM2 TM310-�it PTM 10-�it CTM 10-�it CTM 10-�it CTM
TM Name/Type Reference
TM OperationThetwodifferent typesofTMofferadiverserangeoffunctions,fromsimpletimingoperationstoPWMsignalgeneration.ThekeytounderstandinghowtheTMoperatesistoseeitintermsofafreerunningcounterwhosevalueis thencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounter isdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.
Rev. 1.60 63 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
TM Clock SourceTheclocksourcewhichdrives themaincounter ineachTMcanoriginatefromvarioussources.TheselectionoftherequiredclocksourceisimplementedusingtheTnCK2~TnCK0bitsintheTMcontrolregisters.TheclocksourcecanbearatioofeitherthesystemclockfSYSortheinternalhighclockfH,thefTBCclocksourceortheexternalTCKnpin.TheTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.
TM InterruptsTheCompactTypeandPeriodicTypeTMseachhavetwointernalinterrupts,oneforeachoftheinternalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.WhenaTMinterruptisgenerateditcanbeusedtoclearthecounterandalsotochangethestateoftheTMoutputpin.
TM External Pins EachoftheTMs,irrespectiveofwhattype,hasoneTMinputpin,withthelabelTCKn.TheTMinputpinisessentiallyaclocksourcefortheTMandisselectedusingtheTnCK2~TnCK0bitsintheTMnC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.ThisexternalTMinputpinissharedwithotherfunctionsbutwillbeconnectedtotheinternalTMifselectedusingtheTnCK2~TnCK0bits.TheTMinputpincanbechosentohaveeitherarisingorfallingactiveedge.
TheTMseachhaveoneor twooutputpinswiththelabelTPn.WhentheTMis intheCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalTPnoutputpinisalsothepinwheretheTMgeneratesthePWMoutputwaveform.AstheTMoutputpinsarepin-sharedwithotherfunction,theTMoutput functionmust firstbesetupusingregisters.Asinglebit inoneof the registersdeterminesifitsassociatedpinistobeusedasanexternalTMoutputpinorifitistohaveanotherfunction.ThenumberofoutputpinsforeachTMtypeisdifferent, thedetailsareprovidedintheaccompanyingtable.
PeriodicTypeTMoutputpinnameshavea“_n”suffix.Pinnames that includea“_0”or“_1”suffixindicatethattheyarefromaTMwithmultipleoutputpins.ThisallowstheTMtogenerateacomplimentaryoutputpair,selectedusingtheI/Oregisterdatabits.
TM0 TM1 TM2 TM3TP0_0� TP0_1 TP1 TP� TP3
TM Output Pins
TM Input/Output Pin Control RegistersSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunctionsisimplementedusingoneregisterwithasinglebitineachregistercorrespondingtoaTMinput/outputpin.SettingthebithighwillsetupthecorrespondingpinasaTMinput/outputifresettozerothepinwillretainitsoriginalotherfunctions.
Rev. 1.60 64 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
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TM1 Function Pin Control Block Diagram
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TM2 Function Pin Control Block Diagram
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TM3 Function Pin Control Block Diagram
Rev. 1.60 65 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
TMPC Register
Bit 7 6 5 4 3 2 1 0�a�e — — — T3CP T�CP T1CP T0CP1 T0CP0R/W — — — R/W R/W R/W R/W R/WPOR — — — 0 0 0 0 0
Bit7~5 Unimplemented,readas“0”Bit4 T3CP:TP3pincontrol
0:Disable1:Enable
Bit3 T2CP:TP2pincontrol0:Disable1:Enable
Bit2 T1CP:TP1pincontrol0:Disable1:Enable
Bit1 T0CP1:TP0_1pincontrol0:Disable1:Enable
Bit0 T0CP0:TP0_0pincontrol0:Disable1:Enable
Programming ConsiderationsTheTMCounterRegistersandtheCapture/CompareCCRAandCCRPregisters,being10-bit,allhavealowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.AstheCCRAandCCRPregistersareimplementedinthewayshowninthefollowingdiagramandaccessingtheregister iscarriedout inaspecificwaydescribedabove, itisrecommendedtousethe“MOV”instructiontoaccesstheCCRAandCCRPlowbyteregisters,namedTMxALandTMxRPL,using the followingaccessprocedures.Accessing theCCRAorCCRPlowbyte registerwithout following theseaccessprocedureswill result inunpredictablevalues.
Data Bus
8-�it Buffe�
TMxDHTMxDL
TMxAHTMxAL
TM Counte� Registe� (Read only)
TM CCRA Registe� (Read/W�ite)
TMxRPHTMxRPL
TM CCRP Registe� (Read/W�ite)
Rev. 1.60 66 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Thefollowingstepsshowthereadandwriteprocedures:
• WritingDatatoCCRAorCCRP♦ Step1.WritedatatoLowByteTMxALorTMxRPL
– Notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighByteTMxAHorTMxRPH
– Heredataiswrittendirectlytothehighbyteregistersandsimultaneouslydatais latchedfromthe8-bitbuffertotheLowByteregisters.
• ReadingDatafromtheCounterRegistersandCCRAorCCRP♦ Step1.ReaddatafromtheHighByteTMxDH,TMxAHorTMxRPH
– HeredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.
♦ Step2.ReaddatafromtheLowByteTMxDL,TMxALorTMxRPL– Thisstepreadsdatafromthe8-bitbuffer.
Periodic Type TM – PTMThePeriodicTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.ThePeriodicTMcanbecontrolledwithanexternalinputpinandcandrivetwoexternaloutputpin.
Name TM No. TM Input Pin TM Output Pin10-�it PTM 0 TCK0 TP0_0� TP0_1
Periodic TM OperationAtitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearetwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwiththeCCRAandCCRPregisters.
Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theTnONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.ThePeriodicTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontroltheoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.
Rev. 1.60 67 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
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Periodic Type TM Block Diagram (n=0)
Periodic Type TM Register DescriptionOveralloperationofthePeriodicTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whiletworead/writeregisterpairsexisttostoretheinternal10-bitCCRAandCCRPvalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.
Register Name
Bit
7 6 5 4 3 2 1 0TMnC0 TnPAU TnCK� TnCK1 TnCK0 TnO� — — —TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnCAPTS TnCCLRTMnDL D7 D6 D5 D4 D3 D� D1 D0TMnDH — — — — — — D9 D8TMnAL D7 D6 D5 D4 D3 D� D1 D0TMnAH — — — — — — D9 D8TMnRPL D7 D6 D5 D4 D3 D� D1 D0TMnRPH — — — — — — D9 D8
10-bit Periodic TM Register List (n=0)
Rev. 1.60 68 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
TMnC0 Register
Bit 7 6 5 4 3 2 1 0
�a�e TnPAU TnCK� TnCK1 TnCK0 TnO� — — —
R/W R/W R/W R/W R/W R/W — — —
POR 0 0 0 0 0 — — —
Bit7 TnPAU:TMnCounterPauseControl0:Run1:Pause
Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.
Bit6~4 TnCK2~TnCK0:SelectTMnCounterclock000:fSYS/4001:fH010:fH/16011:fH/64100:fTBC101:fTBC110:TCKnrisingedgeclock111:TCKnfallingedgeclock
ThesethreebitsareusedtoselecttheclocksourcefortheTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.
Bit3 TnON:TMnCounterOn/OffControl0:Off1:On
Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheTMOutputcontrolbit,whenthebitchangesfromlowtohigh.
Bit2~0 Unimplemented,readas“0”
Rev. 1.60 69 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
TMnC1 Register
Bit 7 6 5 4 3 2 1 0�a�e TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnCAPTS TnCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~6 TnM1~TnM0:SelectTMnOperationMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMOutputModeorSinglePulseOutputMode11:Timer/CounterMode
ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetotheTnM1andTnM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.
Bit5~4 TnIO1~TnIO0:SelectTPn_0,TPn_1outputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput
PWMOutputMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput
CaptureInputMode00:InputcaptureatrisingedgeofTPn_0,TPn_1,TCKn01:InputcaptureatfallingedgeofTPn_0,TPn_1,TCKn10:Inputcaptureatfalling/risingedgeofTPn_0,TPn_1,TCKn11:Inputcapturedisabled
Timer/counterModeUnused
ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.IntheCompareMatchOutputMode,theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthesebitsarebothzero,thennochangewill takeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheTnOCbit.NotethattheoutputlevelrequestedbytheTnIO1andTnIO0bitsmustbedifferent fromthe initialvaluesetupusing theTnOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstate,itcanberesettoitsinitiallevelbychangingtheleveloftheTnONbitfromlowtohigh.InthePWMOutputMode,theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.It isnecessarytochangethevaluesoftheTnIO1andTnIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccurif theTnIO1andTnIO0bitsarechangedwhentheTMisrunning.
Rev. 1.60 70 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Bit3 TnOC:TPn_0,TPn_1OutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh
PWMOutputMode/SinglePulseOutputMode0:Activelow1:Activehigh
This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMOutputMode/SinglePulseOutputMode.Ithasnoeffectif theTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogiclevelof theTMoutputpinbeforeacomparematchoccurs.InthePWMOutputModeitdeterminesifthePWMsignalisactivehighoractivelow.
Bit2 TnPOL:TPn_0,TPn_1OutputpolarityControl0:Non-invert1:Invert
ThisbitcontrolsthepolarityoftheTPn_0,TPn_1outputpin.WhenthebitissethightheTMoutputpinwillbe invertedandnot invertedwhenthebit iszero.IthasnoeffectiftheTMisintheTimer/CounterMode.
Bit1 TnCAPTS:TMncapturetriggersourceselect0:FromTPn_0,TPn_1pin1:FromTCKnpin
Bit0 TnCCLR:SelectTMnCounterclearcondition0:TMnComparatrorPmatch1:TMnComparatrorAmatch
Thisbit isused toselect themethodwhichclears thecounter.Remember that thePeriodicTMcontains twocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheTnCCLRbitisnotusedinthePWM,SinglePulseorInputCaptureMode.
TMnDL Register
Bit 7 6 5 4 3 2 1 0�a�e D7 D6 D5 D4 D3 D� D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0
Bit7~0 TMnDL:TMnCounterLowByteRegisterbit7~bit0TMn10-bitCounterbit7~bit0
TMnDH Register
Bit 7 6 5 4 3 2 1 0�a�e — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0
Bit7~2 Unimplemented,readas“0”Bit1~0 TMnDH:TMnCounterHighByteRegisterbit1~bit0
TMn10-bitCounterbit9~bit8
Rev. 1.60 71 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
TMnAL Register
Bit 7 6 5 4 3 2 1 0�a�e D7 D6 D5 D4 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~0 TMnAL:TMnCCRALowByteRegisterbit7~bit0TMn10-bitCCRAbit7~bit0
TMnAH Register
Bit 7 6 5 4 3 2 1 0
�a�e — — — — — — D9 D8
R/W — — — — — — R/W R/W
POR — — — — — — 0 0
Bit7~2 Unimplemented,readas“0”Bit1~0 TMnAH:TMnCCRAHighByteRegisterbit1~bit0
TMn10-bitCCRAbit9~bit8
TMnRPL Register
Bit 7 6 5 4 3 2 1 0�a�e D7 D6 D5 D4 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~0 TMnRPL:TMnCCRPLowByteRegisterbit7~bit0TMn10-bitCCRPbit7~bit0
TMnRPH Register
Bit 7 6 5 4 3 2 1 0�a�e — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0
Bit7~2 Unimplemented,readas"0"Bit1~0 TMnRPH:TMnCCRPHighByteRegisterbit1~bit0
TMn10-bitCCRPbit9~bit8
Rev. 1.60 7� �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Periodic Type TM Operating ModesThePeriodicTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheTnM1andTnM0bitsintheTMnC1register.
Compare Match Output ModeToselect thismode,bitsTnM1andTnM0in theTMnC1register, shouldbeallcleared to00respectively. In thismodeonce thecounter isenabledand running itcanbeclearedby threemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchoccursfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HereboththeTnAFandTnPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.
IftheTnCCLRbitintheTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theTnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenTnCCLRishighnoTnPFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbesetto“0”.
Asthenameof themodesuggests,afteracomparisonismade, theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaTnAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheTnPFinterruptrequestflag,generatedfromacomparematchfromComparatorP,willhavenoeffectontheTMoutputpin.ThewayinwhichtheTMoutputpinchangesstatearedeterminedbytheconditionoftheTnIO1andTnIO0bitsintheTMnC1register.TheTMoutputpincanbeselectedusingtheTnIO1andTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.TheinitialconditionoftheTMoutputpin,whichissetupaftertheTnONbitchangesfromlowtohigh,issetupusingtheTnOCbit.NotethatiftheTnIO1,TnIO0bitsarezerothennopinchangewilltakeplace.
Rev. 1.60 73 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Counte� Value
0x3FF
CCRP
CCRA
TnO�
TnPAU
TnPOL
CCRP Int. Flag TnPF
CCRA Int. Flag TnAF
TM O/P Pin
Ti�e
CCRP=0
CCRP > 0
Counte� ove�flowCCRP > 0Counte� clea�ed �y CCRP value
Pause
Resu�e
Stop
Counte� Resta�t
TnCCLR = 0; TnM [1:0] = 00
Output pin set to initial Level Low if TnOC=0
Output Toggle with TnAF flag
�ote TnIO [1:0] = 10 Active High Output selectHe�e TnIO [1:0] = 11
Toggle Output select
Output not affected �y TnAF flag. Re�ains High until �eset �y TnO� �it
Output PinReset to Initial value
Output cont�olled �y othe� pin-sha�ed function
Output Inve�tswhen TnPOL is high
Compare Match Output Mode – TnCCLR = 0 (n=0)
Note:1.WithTnCCLR=0–aComparatorPmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoinitialstatebyaTnONbitrisingedge
Rev. 1.60 74 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Counte� Value
0x3FF
CCRP
CCRA
TnO�
TnPAU
TnPOL
CCRP Int. Flag TnPF
CCRA Int. Flag TnAF
TM O/P Pin
Ti�e
CCRA=0
CCRA = 0Counte� ove�flowCCRA > 0 Counte� clea�ed �y CCRA value
Pause
Resu�e
Stop Counte� Resta�t
TnCCLR = 1; TnM [1:0] = 00
Output pin set to initial Level Low if TnOC=0
Output Toggle with TnAF flag
�ote TnIO [1:0] = 10 Active High Output selectHe�e TnIO [1:0] = 11
Toggle Output select
Output not affected �y TnAF flag. Re�ains High until �eset �y TnO� �it
Output PinReset to Initial value
Output cont�olled �y othe� pin-sha�ed function
Output Inve�tswhen TnPOL is high
TnPF not gene�ated
�o TnAF flag gene�ated on CCRA ove�flow
Output does not change
Compare Match Output Mode – TnCCLR = 1 (n=0)
Note:1.WithTnCCLR=1–aComparatorAmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoinitialstatebyaTnONrisingedge4.TheTnPFflagisnotgeneratedwhenTnCCLR=1
Rev. 1.60 75 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Timer/Counter ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldallbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.
PWM Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto10respectivelyandalso theTnIO1andTnIO0bitsshouldbeset to10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.
AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMOutputMode, theTnCCLRbithasnoeffectas thePWMperiod.BothoftheCCRPandCCRAregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.
Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheTnOCbitintheTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoTnIO1andTnIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.
• 10-bit PTM, PWM Output Mode
CCRP 1~1023 0Pe�iod 1~10�3 10�4Duty CCRA
IffSYS=8MHz,TMclocksourceselectfSYS/4,CCRP=512andCCRA=128,
ThePTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=3.90625kHz,duty=128/512=25%.
IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.
Rev. 1.60 76 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Counte� Value
CCRP
CCRA
TnO�
TnPAU
TnPOL
CCRP Int. Flag TnPF
CCRA Int. Flag TnAF
TM O/P Pin(TnOC=1)
Ti�e
Counte� clea�ed �y CCRP
Pause Resu�e Counte� Stop if TnO� �it low
Counte� Reset when TnO� �etu�ns high
TnM [1:0] = 10
PWM Duty Cycle set �y CCRA
PWM �esu�es ope�ation
Output cont�olled �y othe� pin-sha�ed function Output Inve�ts
when TnPOL = 1PWM Pe�iod set �y CCRP
TM O/P Pin(TnOC=0)
PWM Output Mode (n=0)
Note:1.HereCounterclearedbyCCRP2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation
Rev. 1.60 77 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Single Pulse Output ModeToselectthismode,therequiredbitpairs,TnM1andTnM0shouldbesetto10respectivelyandalsothecorrespondingTnIO1andTnIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheTMoutputpin.
Thetriggerfor thepulseoutput leadingedgeisa lowtohightransitionof theTnONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseOutputMode,theTnONbitcanalsobemadetoautomaticallychangefromlowtohighusingtheexternalTCKnpin,whichwillinturninitiatetheSinglePulseoutput.WhentheTnONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.TheTnONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhentheTnONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.
HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheTnONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateTMinterrupts.ThecountercanonlyberesetbacktozerowhentheTnONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseOutputModeCCRPisnotused.TheTnCCLRbitisalsonotused.
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Single Pulse Generation (n=0)
Rev. 1.60 78 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Counte� Value
CCRP
CCRA
TnO�
TnPAU
TnPOL
CCRP Int. Flag TnPF
CCRA Int. Flag TnAF
TM O/P Pin(TnOC=1)
Ti�e
Counte� stopped �y CCRA
PauseResu�e Counte� Stops
�y softwa�e
Counte� Reset when TnO� �etu�ns high
TnM [1:0] = 10 ; TnIO [1:0] = 11
Pulse Width set �y CCRA
Output Inve�tswhen TnPOL = 1
�o CCRP Inte��upts gene�ated
TM O/P Pin(TnOC=0)
TCKn pin
Softwa�e T�igge�
Clea�ed �y CCRA �atch
TCKn pin T�igge�
Auto. set �y TCKn pin
Softwa�e T�igge�
Softwa�e Clea�
Softwa�e T�igge�Softwa�e
T�igge�
Single Pulse Output Mode (n=0)
Note:1.CounterstoppedbyCCRA2.CCRPisnotused3.ThepulseistriggeredbytheTCKnpinorbysettingtheTnONbithigh4.ATCKnpinactiveedgewillautomaticallysettheTnONbithigh5.IntheSinglePulseOutputMode,TnIO[1:0]mustbesetto“11”andcannotbechanged.
Rev. 1.60 79 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Capture Input ModeToselectthismodebitsTnM1andTnM0intheTMnC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedontheTPn_0,TPn_1orTCKnpin,selectedbytheTnCAPTSbitintheTMnC0register.Theinputpinactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingtheTnIO1andTnIO0bitsintheTMnC1register.Thecounter isstartedwhentheTnONbitchangesfromlowtohighwhichis initiatedusingtheapplicationprogram.
WhentherequirededgetransitionappearsontheTPn_0,TPn_1orTCKnpinthepresentvalueinthecounterwillbelatchedintotheCCRAregisterandaTMinterruptgenerated.IrrespectiveofwhateventsoccurontheTPn_0,TPn_1orTCKnpinthecounterwillcontinuetofreerununtiltheTnONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheTnIO1andTnIO0bitscanselect theactivetriggeredgeontheTPn_0,TPn_1orTCKnpintobearisingedge,fallingedgeorbothedgetypes.IftheTnIO1andTnIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheTPn_0,TPn_1orTCKnpin,howeveritmustbenotedthatthecounterwillcontinuetorun.
AstheTPn_0,TPn_1orTCKnpinispinsharedwithotherfunctions,caremustbetakeniftheTMnisintheCaptureInputMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.TheTnCCLR,TnOCandTnPOLbitsarenotusedinthisMode.
Rev. 1.60 80 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Counte� Value
YY
CCRP
TnO�
TnPAU
CCRP Int. Flag TnPF
CCRA Int. Flag TnAF
CCRA Value
Ti�e
Counte� clea�ed �y CCRP
PauseResu�e
Counte� Reset
TM captu�e pinTPn_x o� TCKn
XX
Counte� Stop
TnIO [1:0] Value
XX YY XX YY
Active edge Active edge Active edge
00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disa�le Captu�e
TnM [1:0] = 01
Capture Input Mode (n=0)
Note:1.TnM[1:0]=01andactiveedgesetbytheTnIO[1:0]bits2.ATMCaptureinputpinactiveedgetransferscountervaluetoCCRA3.TheTnCCLRbitisnotused4.Nooutputfunction–TnOCandTnPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero
Rev. 1.60 81 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Compact Type TM – CTMAlthough thesimplest formof the threeTMtypes, theCompactTMtypestill contains threeoperatingmodes,whichareCompareMatchOutput,Timer/EventCounterandPWMOutputmodes.TheCompactTMcanalsobecontrolledwithanexternalinputpinandcandriveoneexternaloutputpin.
Name TM No. TM Input Pin TM Output Pin10-�it CTM 1� �� 3 TCK1� TCK�� TCK3 TP1� TP�� TP3
Compact TM Operation Atitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealso twointernalcomparatorswith thenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPisthreebitswidewhosevalueiscomparedwiththehighestthreebitsinthecounterwhiletheCCRAisthetenbitsandthereforecompareswithallcounterbits.
Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theTnONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheCompactTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.
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Compact Type TM Block Digram (n=1~3)
Rev. 1.60 8� �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Compact Type TM Register DescriptionOveralloperationof theCompactTMiscontrolledusingsixregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whilearead/writeregisterpairexiststostoretheinternal10-bitCCRAvalue.Theremaining tworegistersarecontrol registerswhichsetup thedifferentoperatingandcontrolmodesaswellasthethreeCCRPbits.
Register Name
Bit
7 6 5 4 3 2 1 0TMnC0 TnPAU TnCK� TnCK1 TnCK0 TnO� TnRP� TnRP1 TnRP0TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLRTMnDL D7 D6 D5 D4 D3 D� D1 D0TMnDH — — — — — — D9 D8TMnAL D7 D6 D5 D4 D3 D� D1 D0TMnAH — — — — — — D9 D8
Compact TM Register List (n=1~3)
TMnC0 Register
Bit 7 6 5 4 3 2 1 0�a�e TnPAU TnCK� TnCK1 TnCK0 TnO� TnRP� TnRP1 TnRP0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7 TnPAU:TMnCounterPauseControl0:Run1:Pause
Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.
Bit6~4 TnCK2~TnCK0:SelectTMnCounterclock000:fSYS/4001:fH010:fH/16011:fH/64100:fTBC101:fTBC110:TCKnrisingedgeclock111:TCKnfallingedgeclock
ThesethreebitsareusedtoselecttheclocksourcefortheTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.
Bit3 TnON:TMnCounterOn/OffControl0:Off1:On
Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhen thebitchangesfromhigh to low, the internalcounterwillretainitsresidualvalue.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheTnOCbit,whentheTnONbitchangesfromlowtohigh.
Rev. 1.60 83 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Bit2~0 TnRP2~TnRP0:TMnCCRP3-bitregister,comparedwiththeTMnCounterbit9~bit7ComparatorPMatchPeriod000:1024TMnclocks001:128TMnclocks010:256TMnclocks011:384TMnclocks100:512TMnclocks101:640TMnclocks110:768TMnclocks111:896TMnclocks
ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter’shighest threebits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theTnCCLRbit isset tozero.SettingtheTnCCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.
TMnC1 Register
Bit 7 6 5 4 3 2 1 0�a�e TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~6 TnM1, TnM0:SelectTMnOperatingMode00:CompareMatchOutputMode01:Undefined10:PWMOutputMode11:Timer/CounterMode
ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetotheTnM1andTnM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.
Bit5~4 TnIO1, TnIO0:SelectTPnoutputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput
PWMOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Undefined
Timer/CounterModeUnused
ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.
Rev. 1.60 84 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
IntheCompareMatchOutputMode,theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowor totoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheTnOCbit intheTMnC1register.NotethattheoutputlevelrequestedbytheTnIO1andTnIO0bitsmustbedifferentfromtheinitialvaluesetupusingtheTnOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstate,itcanberesettoitsinitiallevelbychangingtheleveloftheTnONbitfromlowtohigh.InthePWMOutputMode,theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits. It isnecessarytoonlychangethevaluesof theTnIO1andTnIO0bitsonlyafter theTMnhasbeen switchedoff.UnpredictablePWMoutputswilloccuriftheTnIO1andTnIO0bitsarechangedwhentheTMisrunning.
Bit3 TnOC:TPnOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh
PWMOutputMode0:Activelow1:Activehigh
This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMOutputMode.IthasnoeffectiftheTMisintheTimer/CounterMode.IntheCompareMatchOutputMode itdetermines the logic levelof theTMoutputpinbeforeacomparematchoccurs.InthePWMOutputModeitdeterminesif thePWMsignal isactivehighoractivelow.
Bit2 TnPOL:TPnOutputpolarityControl0:Non-invert1:Invert
ThisbitcontrolsthepolarityoftheTPnoutputpin.WhenthebitissethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.
Bit1 TnDPX:TMnPWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period
Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.
Bit0 TnCCLR:SelectTMnCounterclearcondition0:TMnComparatrorPmatch1:TMnComparatrorAmatch
Thisbit isused toselect themethodwhichclears thecounter.Remember that theCompactTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheTnCCLRbitisnotusedinthePWMOutputMode.
Rev. 1.60 85 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
TMnDL Register
Bit 7 6 5 4 3 2 1 0�a�e D7 D6 D5 D4 D3 D� D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0
Bit7~0 D7~D0:TMnCounterLowByteRegisterbit7~bit0TMn10-bitCounterbit7~bit0
TMnDH Register
Bit 7 6 5 4 3 2 1 0�a�e — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0
Bit7~2 Unimplemented,readas“0”Bit1~0 D9~D8:TMnCounterHighByteRegisterbit1~bit0
TMn10-bitCounterbit9~bit8
TMnAL Register
Bit 7 6 5 4 3 2 1 0�a�e D7 D6 D5 D4 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~0 D7~D0:TMnCCRALowByteRegisterbit7~bit0TMn10-bitCCRAbit7~bit0
TMnAH Register
Bit 7 6 5 4 3 2 1 0�a�e — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0
Bit7~2 Unimplemented,readas“0”Bit1~0 D9~D8:TMnCCRAHighByteRegisterbit1~bit0
TMn10-bitCCRAbit9~bit8
Rev. 1.60 86 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Compact Type TM Operating ModesTheCompactTypeTMcanoperateinoneofthreeoperatingmodes,CompareMatchOutputMode,PWMOutputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheTnM1andTnM0bitsintheTMnC1register.
Compare Match Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1register,shouldbesetto00respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchoccursfromComparatorP, theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothTnAFandTnPFinterruptrequestflagsfortheComparatorAandComparatorPrespectively,willbothbegenerated.
IftheTnCCLRbitintheTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theTnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenTnCCLRishighnoTnPFinterruptrequestflagwillbegenerated.IftheCCRAbitsareallzero,thecounterwilloverflowwhenitsreachesitsmaximum10-bit,3FFHex,value,howeverheretheTnAFinterruptrequestflagwillnotbegenerated.
As thenameof themodesuggests,afteracomparison ismade, theTMoutputpinwillchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaTnAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheTnPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.Thewayinwhich theTMoutputpinchangesstatearedeterminedby theconditionof theTnIO1andTnIO0bitsintheTMnC1register.TheTMoutputpincanbeselectedusingtheTnIO1andTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof theTMoutputpin,which issetupafter theTnONbitchangesfromlowtohigh,issetupusingtheTnOCbit.NotethatiftheTnIO1andTnIO0bitsarezerothennopinchangewilltakeplace.
Rev. 1.60 87 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Counte� Value
0x3FF
CCRP
CCRA
TnO�
TnPAU
TnPOL
CCRP Int. Flag TnPF
CCRA Int. Flag TnAF
TM O/P Pin
Ti�e
CCRP=0
CCRP > 0
Counte� ove�flowCCRP > 0Counte� clea�ed �y CCRP value
Pause
Resu�e
Stop
Counte� Resta�t
TnCCLR = 0; TnM [1:0] = 00
Output pin set to initial Level Low if TnOC=0
Output Toggle with TnAF flag
�ote TnIO [1:0] = 10 Active High Output selectHe�e TnIO [1:0] = 11
Toggle Output select
Output not affected �y TnAF flag. Re�ains High until �eset �y TnO� �it
Output PinReset to Initial value
Output cont�olled �y othe� pin-sha�ed function
Output Inve�tswhen TnPOL is high
Compare Match Output Mode - TnCCLR = 0 (n=1~3)
Note:1.WithTnCCLR=0,aComparatorPmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge
Rev. 1.60 88 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Counte� Value
0x3FF
CCRP
CCRA
TnO�
TnPAU
TnPOL
CCRP Int. Flag TnPF
CCRA Int. Flag TnAF
TM O/P Pin
Ti�e
CCRA=0
CCRA = 0Counte� ove�flowCCRA > 0 Counte� clea�ed �y CCRA value
Pause
Resu�e
Stop Counte� Resta�t
TnCCLR = 1; TnM [1:0] = 00
Output pin set to initial Level Low if TnOC=0
Output Toggle with TnAF flag
�ote TnIO [1:0] = 10 Active High Output selectHe�e TnIO [1:0] = 11
Toggle Output select
Output not affected �y TnAF flag. Re�ains High until �eset �y TnO� �it
Output PinReset to Initial value
Output cont�olled �y othe� pin-sha�ed function
Output Inve�tswhen TnPOL is high
TnPF not gene�ated
�o TnAF flag gene�ated on CCRA ove�flow
Output does not change
Compare Match Output Mode - TnCCLR = 1 (n=1~3)
Note:1.WithTnCCLR=1,aComparatorAmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.TheTnPFflagisnotgeneratedwhenTnCCLR=1
Rev. 1.60 89 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Timer/Counter Mode Toselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.
PWM Output Mode Toselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol, illuminationcontroletc.Byprovidingasignalof fixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.
AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMOutputMode,theTnCCLRbithasnoeffectonthePWMoperation.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregister isusedtocleartheinternalcounterandthuscontrol thePWMwaveformfrequency,while theotherone isused tocontrol thedutycycle.Which register isused tocontroleitherfrequencyordutycycle isdeterminedusing theTnDPXbit in theTMnC1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevalues in theCCRAandCCRPregisters.
Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheTnOCbitintheTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoTnIO1andTnIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.
• CTM, PWM Output Mode, Edge-aligned Mode, TnDPX=0
CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod 1�8 �56 384 51� 640 768 896 10�4Duty CCRA
IffSYS=8MHz,TMclocksourceisfSYS/4,CCRP=100bandCCRA=128,
TheCTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=3.90625kHz,duty=128/512=25%.
IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.
• CTM, PWM Output Mode, Edge-aligned Mode, TnDPX=1
CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod CCRADuty 1�8 �56 384 51� 640 768 896 10�4
ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.
Rev. 1.60 90 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Counte� Value
CCRP
CCRA
TnO�
TnPAU
TnPOL
CCRP Int. Flag TnPF
CCRA Int. Flag TnAF
TM O/P Pin(TnOC=1)
Ti�e
Counte� clea�ed �y CCRP
Pause Resu�e Counte� Stop if TnO� �it low
Counte� Reset when TnO� �etu�ns high
TnDPX = 0; TnM [1:0] = 10
PWM Duty Cycle set �y CCRA
PWM �esu�es ope�ation
Output cont�olled �y othe� pin-sha�ed function Output Inve�ts
when TnPOL = 1PWM Pe�iod set �y CCRP
TM O/P Pin(TnOC=0)
PWM Output Mode - TnDPX = 0 (n=1~3)
Note:1.HereTnDPX=0–CounterclearedbyCCRP2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation
Rev. 1.60 91 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Counte� Value
CCRP
CCRA
TnO�
TnPAU
TnPOL
CCRP Int. Flag TnPF
CCRA Int. Flag TnAF
TM O/P Pin(TnOC=1)
Ti�e
Counte� clea�ed �y CCRA
Pause Resu�e Counte� Stop if TnO� �it low
Counte� Reset when TnO� �etu�ns high
TnDPX = 1; TnM [1:0] = 10
PWM Duty Cycle set �y CCRP
PWM �esu�es ope�ation
Output cont�olled �y othe� pin-sha�ed function Output Inve�ts
when TnPOL = 1PWM Pe�iod set �y CCRA
TM O/P Pin(TnOC=0)
PWM Output Mode - TnDPX = 1 (n=1~3)
Note:1.HereTnDPX=1–CounterclearedbyCCRA2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation
Rev. 1.60 9� �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Analog to Digital Converter – ADCTheneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.
A/D OverviewThedevicescontainamulti-channelanalog todigitalconverterwhichcandirectly interface toexternalanalogsignals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectlyintoeithera12-bitdigitalvalue.
Input Channels A/D Channel Select Bits Input Pins10 ACS4� ACS3~ACS0 A�0~A�9
TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregisters.
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A/D Converter Structure
A/D Converter Register DescriptionOveralloperationof theA/Dconverteriscontrolledusingsixregisters.AreadonlyregisterpairexiststostoretheADCdata12-bitvalue.TheremainingfourregistersarecontrolregisterswhichsetuptheoperatingandcontrolfunctionoftheA/Dconverter.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Register Name
Bit
7 6 5 4 3 2 1 0ADRL(ADRFS=0) D3 D� D1 D0 — — — —ADRL(ADRFS=1) D7 D6 D5 D4 D3 D� D1 D0ADRH(ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D4ADRH(ADRFS=1) — — — — D11 D10 D9 D8
ADCR0 START EOCB ADOFF ADRFS ACS3 ACS� ACS1 ACS0ADCR1 ACS4 VBGE� — VREFS — ADCK� ADCK1 ADCK0ACERL ACE7 ACE6 ACE5 ACE4 ACE3 ACE� ACE1 ACE0ACERH — — — — — — ACE9 ACE8
A/D Converter Register List
A/D Converter Data Registers – ADRL, ADRHThedevices,whichhaveaninternal12-bitA/Dconverter,requiretwodataregisters,ahighbyteregister,knownasADRH,andalowbyteregister,knownasADRL.Aftertheconversionprocesstakesplace, these registerscanbedirectly readby themicrocontroller toobtain thedigitisedconversionvalue.Asonly12bitsofthe16-bitregisterspaceisutilised,theformatinwhichthedataisstorediscontrolledbytheADRFSbitintheADCR0registerasshownintheaccompanyingtable.D0~D11aretheA/Dconversionresultdatabits.Anyunusedbitswillbereadaszero.
ADRFSADRH ADRL
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 00 D11 D10 D9 D8 D7 D6 D5 D4 D3 D� D1 D0 0 0 0 01 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D� D1 D0
A/D Data Registers
A/D Converter Control Registers – ADCR0, ADCR1, ACERL, ACERHTocontrol the functionandoperationof theA/Dconverter, fourcontrol registersknownasADCR0,ADCR1,ACERLandACERHareprovided.These8-bitregistersdefinefunctionssuchastheselectionofwhichanalogchannelisconnectedtotheinternalA/Dconverter, thedigitiseddataformat,theA/DclocksourceaswellascontrollingthestartfunctionandmonitoringtheA/Dconverterendofconversionstatus.TheACS3~ACS0bitsintheADCR0registerandtheACS4bitintheADCR1registerdefinetheADCinputchannelnumber.Asthedevicecontainsonlyoneactualanalogtodigitalconverterhardwarecircuit,eachoftheindividual8analoginputsmustberoutedtotheconverter.ItisthefunctionoftheACS4~ACS0bitstodeterminewhichanalogchannelinputpinorinternalVBGisactuallyconnectedtotheinternalA/Dconverter.
TheACERHandACERLcontrolregisterscontaintheACE9~ACE0bitswhichdeterminewhichpinsonPBandPEPortsareusedasanaloginputsfortheA/Dconverterinputandwhichpinsarenot tobeusedastheA/Dconverter input.Settingthecorrespondingbithighwillselect theA/Dinputfunction,clearingthebittozerowillselecteithertheI/Oorotherpin-sharedfunction.WhenthepinisselectedtobeanA/Dinput,itsoriginalfunctionwhetheritisanI/Oorotherpin-sharedfunctionwillberemoved.Inaddition,anyinternalpull-highresistorsconnectedtothesepinswillbeautomaticallyremovedifthepinisselectedtobeanA/Dinput.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
ADCR0 Register
Bit 7 6 5 4 3 2 1 0�a�e START EOCB ADOFF ADRFS ACS3 ACS� ACS1 ACS0R/W R/W R R/W R/W R/W R/W R/W R/WPOR 0 1 1 0 0 0 0 0
Bit7 START:StarttheA/Dconversion0→1→0:Start0→1:ResettheA/DconverterandsetEOCBto“1”
ThisbitisusedtoinitiateanA/Dconversionprocess.Thebitisnormallylowbutifsethighandthenclearedlowagain,theA/Dconverterwillinitiateaconversionprocess.WhenthebitissethightheA/Dconverterwillbereset.
Bit6 EOCB:EndofA/Dconversionflag0:A/Dconversionended1:A/Dconversioninprogress
ThisreadonlyflagisusedtoindicatewhenanA/Dconversionprocesshascompleted.Whentheconversionprocessisrunning,thebitwillbehigh.
Bit5 ADOFF:ADCmodulepoweron/offcontrolbit0:ADCmodulepoweron1:ADCmodulepoweroff
Thisbitcontrols thepowerto theA/Dinternalfunction.ThisbitshouldbeclearedtozerotoenabletheA/Dconverter.IfthebitissethighthentheA/Dconverterwillbeswitchedoffreducingthedevicepowerconsumption.AstheA/Dconverterwillconsumealimitedamountofpower,evenwhennotexecutingaconversion,thismaybeanimportantconsiderationinpowersensitivebatterypoweredapplications.Note:1.ItisrecommendedtosetADOFF=1beforeenteringIDLE/SLEEPModefor
savingpower.2.ADOFF=1willpowerdowntheADCmodule.
Bit4 ADRFS:A/Ddataformatcontrolbit0:ADCDataMSBisADRHbit7,LSBisADRLbit41:ADCDataMSBisADRHbit3,LSBisADRLbit0
Thisbitcontrols theformatof the12-bitconvertedA/Dvaluein thetwoA/Ddataregisters.DetailsareprovidedintheA/Ddataregistersection.
Bit3~0 ACS3~ACS0:SelectA/Dchannel(whenACS4is“0”)0000:AN00001:AN10010:AN20011:AN30100:AN40101:AN50110:AN60111:AN71000:AN81001~1111:AN9
ThesearetheA/Dchannelselectcontrolbits.AsthereisonlyoneinternalhardwareA/DconvertereachofthetenA/Dinputsmustberoutedtotheinternalconverterusingthesebits.IftheACS4bitissethigh,thentheinternalBandgapVBGwillberoutedtotheA/DConverter.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
ADCR1 Register
Bit 7 6 5 4 3 2 1 0�a�e ACS4 VBGE� — VREFS — ADCK� ADCK1 ADCK0R/W R/W R/W — R/W — R/W R/W R/WPOR 0 0 — 0 — 0 0 0
Bit7 ACS4:SelectinternalVBGasADCinputcontrol0:Disable1:Enable
ThisbitenablesVBG tobeconnected to theA/Dconverter.TheVBGENbitmustfirsthavebeenset toenablethebandgapcircuitVBGvoltagetobeusedbytheA/Dconverter.WhentheACS4bitissethigh,thebandgapVBGvoltagewillberoutedtotheA/DconverterandtheotherA/Dinputchannelsdisconnected.
Bit6 VBGEN:InternalVBGcontrol0:Disable1:Enable
Thisbitcontrols the internalBandgapcircuiton/offfunctionto theA/Dconverter.WhenthebitissethighthebandgapvoltageVBGcanbeusedbytheA/Dconverter.IfVBGisnotusedbytheA/DconverterandtheLVR/LVDfunctionisdisabledthenthebandgapreferencecircuitwillbeautomaticallyswitchedofftoconservepower.WhenVBGisswitchedonforusebytheA/Dconverter,atimetBGshouldbeallowedforthebandgapcircuittostabilisebeforeimplementinganA/Dconversion.
Bit5 Unimplemented,readas“0”Bit4 VREFS:SelecteADCreferencevoltage
0:InternalADCpower1:VREFpin
ThisbitisusedtoselectthereferencevoltagefortheA/Dconverter.Ifthebitishigh,thentheA/DconverterreferencevoltageissuppliedontheexternalVREFpin.Ifthepinislow,thentheinternalreferenceisusedwhichistakenfromthepowersupplypinVDD.WhentheA/DconverterreferencevoltageissuppliedontheexternalVREFpinwhichispin-sharedwithotherfunctions,allofthepin-sharedfunctionsexceptVREFonthispinaredisabled.
Bit3 Unimplemented,readas“0”Bit2~0 ADCK2~ADCK0:SelectADCclocksource
000:fSYS
001:fSYS/2010:fSYS/4011:fSYS/8100:fSYS/16101:fSYS/32110:fSYS/64111:Undefined
ThesethreebitsareusedtoselecttheclocksourcefortheA/Dconverter.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Bandgap reference voltage on/off true table:
ACS4 VBGEN LVR/LVD VBG Bandgap Reference Voltagex 0 Ena�le Off to G�D Onx 0 Disa�le Off to G�D Offx 1 x On On
x: Don’t ca�e
ACERL Register
Bit 7 6 5 4 3 2 1 0�a�e ACE7 ACE6 ACE5 ACE4 ACE3 ACE� ACE1 ACE0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1
Bit7 ACE7:DefinePB4isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN7
Bit6 ACE6:DefinePE6isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN6
Bit5 ACE5:DefinePE5isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN5
Bit4 ACE4:DefinePE4isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN4
Bit3 ACE3:DefinePB3isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN3
Bit2 ACE2:DefinePB2isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN2
Bit1 ACE1:DefinePB1isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN1
Bit0 ACE0:DefinePB0isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN0
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
ACERH Register
Bit 7 6 5 4 3 2 1 0�a�e — — — — — — ACE9 ACE8R/W — — — — — — R/W R/WPOR — — — — — — 1 1
Bit7~2 Unimplemented,readas“0”Bit1 ACE9:DefinePB5isA/Dinputornot
0:NotA/Dinput1:A/Dinput,AN9
Bit0 ACE8:DefinePE7isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN8
A/D Operation TheSTARTbit in theADCR0register isused tostartand reset theA/Dconverter.When themicrocontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbe initiated.WhentheSTARTbit isbroughtfromlowtohighbutnot lowagain, theEOCBbitintheADCR0registerwillbesethighandtheanalogtodigitalconverterwillbereset.ItistheSTARTbitthatisusedtocontroltheoverallstartoperationoftheinternalanalogtodigitalconverter.
TheEOCBbit in theADCR0register isused to indicatewhentheanalogtodigitalconversionprocess is complete.Thisbitwillbeautomatically set to “0”by themicrocontroller after aconversioncyclehasended.Inaddition, thecorrespondingA/Dinterruptrequestflagwillbesetintheinterruptcontrolregister,andif theinterruptsareenabled,anappropriateinternalinterruptsignalwillbegenerated.ThisA/Dinternal interruptsignalwilldirect theprogramflowto theassociatedA/Dinternal interruptaddressforprocessing.If theA/Dinternal interrupt isdisabled,themicrocontrollercanbeusedtopolltheEOCBbitintheADCR0registertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.
TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosentobeeither fSYSora subdividedversionof fSYSThedivision ratiovalue isdeterminedby theADCK2~ADCK0bitsintheADCR1register.
AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYS,andbybitsADCK2~ADCK0,thereare some limitationson theA/Dclocksource speed range thatcanbe selected.As therecommendedrangeofpermissibleA/Dclockperiod, tADCK, isfrom0.5μsto10μs,caremustbetakenforselectedsystemclockfrequencies.Forexample,ifthesystemclockoperatesatafrequencyof4MHz,theADCK2~ADCK0bitsshouldnotbeset to000Bor110B.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/DclockperiodorgreaterthanthemaximumA/DclockperiodwhichmayresultininaccurateA/Dconversionvalues.
Refer to thefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessthanthespecifiedminimumA/DClockPeriod.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
fSYS
A/D Clock Period (tADCK)ADCK2,ADCK1,ADCK0
=000(fSYS)
ADCK2,ADCK1,ADCK0
=001(fSYS/2)
ADCK2,ADCK1,ADCK0
=010(fSYS/4)
ADCK2,ADCK1,ADCK0
=011(fSYS/8)
ADCK2,ADCK1,ADCK0
=100(fSYS/16)
ADCK2,ADCK1,ADCK0
=101(fSYS/32)
ADCK2,ADCK1,ADCK0
=110(fSYS/64)
ADCK2,ADCK1,ADCK0
=111
1MHz 1μs 2μs 4μs 8μs 16μs* 32μs* 64μs* Undefined�MHz 500ns 1μs 2μs 4μs 8μs 16μs* 32μs* Undefined4MHz 250ns* 500ns 1μs 2μs 4μs 8μs 16μs* Undefined8MHz 125ns* 250ns* 500ns 1μs 2μs 4μs 8μs Undefined
A/D Clock Period Examples
Controlling thepoweron/off functionof theA/Dconvertercircuitry is implementedusing theADOFFbitintheADCR0register.ThisbitmustbezerotopowerontheA/Dconverter.WhentheADOFFbit isclearedtozerotopowerontheA/Dconverter internalcircuitryacertaindelay,asindicatedinthetimingdiagram,mustbeallowedbeforeanA/Dconversionisinitiated.EvenifnopinsareselectedforuseasA/DinputsbyclearingtheACE9~ACE0bitsintheACERHandACERLregisters, if theADOFFbit iszerothensomepowerwillstillbeconsumed.InpowerconsciousapplicationsitisthereforerecommendedthattheADOFFissethightoreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused.
ThereferencevoltagesupplytotheA/DConvertercanbesuppliedfromeitherthepositivepowersupplypin,VDD,orfromanexternalreferencesourcessuppliedonpinVREF.ThedesiredselectionismadeusingtheVREFSbit.AstheVREFpinispin-sharedwithotherfunctions,whentheVREFSbitissethigh,theVREFpinfunctionwillbeselectedandtheotherpinfunctionswillbedisabledautomatically.
A/D Input PinsAllof theA/Danalog inputpinsarepin-sharedwith thePBandPEI/Opinsaswellasotherfunctions.TheACE9~ACE0bits in theACERHandACERLregisters,determinewhether theinputpinsaresetupasA/Dconverteranaloginputsorwhether theyhaveotherfunctions.If theACE9~ACE0bitsfor itscorrespondingpin issethighthenthepinswillbesetuptobeanA/Dconverter inputand theoriginalpinfunctionsdisabled. In thisway,pinscanbechangedunderprogramcontrol tochangetheir functionbetweenA/Dinputsandotherfunctions.Allpull-highresistors,whicharesetupthroughregisterprogramming,willbeautomaticallydisconnectedif thepinsaresetupasA/Dinputs.NotethatitisnotnecessarytofirstsetuptheA/DpinasaninputinthePBCorPECportcontrolregistertoenabletheA/DinputaswhentheACE9~ACE0bitsenableanA/Dinput,thestatusoftheportcontrolregisterwillbeoverridden.
TheA/Dconverterhas itsownreferencevoltagepin,VREF,however thereferencevoltagecanalsobesuppliedfromthepowersupplypin,achoicewhichismadethroughtheVREFSbitintheADCR1register.TheanaloginputvaluesmustnotbeallowedtoexceedthevalueofVREF.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
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A/D Input Structure
Summary of A/D Conversion Steps ThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.
• Step1SelecttherequiredA/DconversionclockbycorrectlyprogrammingbitsADCK2~ADCK0intheADCR1register.
• Step2EnabletheA/DbyclearingtheADOFFbitintheADCR0registertozero.
• Step3SelectwhichchannelistobeconnectedtotheinternalA/DconverterbycorrectlyprogrammingtheACS4~ACS0bitswhicharealsocontainedintheADCR1andADCR0registers.
• Step4SelectwhichpinsaretobeusedasA/DinputsandconfigurethembycorrectlyprogrammingtheACE9~ACE0bitsintheACERHandACERLregisters.
• Step5If theinterruptsare tobeused, theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dconverterinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,andtheA/Dconverterinterruptbit,ADE,mustbothbesethightodothis.
• Step6Theanalog todigitalconversionprocesscannowbe initialisedbysetting theSTARTbit intheADCR0registerfromlowtohighandthenlowagain.Notethat thisbitshouldhavebeenoriginallyclearedtozero.
• Step7Tocheckwhentheanalogtodigitalconversionprocessiscomplete,theEOCBbitintheADCR0registercanbepolled.Theconversionprocessiscompletewhenthisbitgoeslow.WhenthisoccurstheA/DdataregistersADRLandADRHcanbereadtoobtaintheconversionvalue.Asanalternativemethod,iftheinterruptsareenabledandthestackisnotfull,theprogramcanwaitforanA/Dinterrupttooccur.
Note:Whencheckingfortheendoftheconversionprocess,ifthemethodofpollingtheEOCBbitintheADCR0registerisused,theinterruptenablestepabovecanbeomitted.
Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.AfteranA/Dconversionprocesshasbeeninitiatedby theapplicationprogram, themicrocontroller internalhardwarewillbegin tocarryout theconversion,duringwhichtimetheprogramcancontinuewithotherfunctions.ThetimetakenfortheA/Dconversionis16tADCKwheretADCKisequaltotheA/Dclockperiod.
Rev. 1.60 100 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
ADC �odule O�
START
EOCB
ACS4~ACS0
off on off ontO��ST
tADCS
A/D sa�pling ti�etADCS
A/D sa�pling ti�e
Reset A/D conve�sion
Sta�t of A/D conve�sion
tADC
A/D conve�sion ti�etADC
A/D conve�sion ti�e
00011B 00010B 00000B 00001B
ADOFF
End of A/D conve�sion
Reset A/D conve�sion
End of A/D conve�sion
Sta�t of A/D conve�sion
Reset A/D conve�sion
Powe�-on Reset
1. Define po�t configu�ation�. Select analog channel
Sta�t of A/D conve�sion
A/D Conversion Timing
Programming ConsiderationsDuringmicrocontrolleroperationswhere theA/Dconverter isnotbeingused, theA/Dinternalcircuitrycanbeswitchedoff to reducepowerconsumption,bysettingbitADOFFhigh in theADCR0register.Whenthishappens, theinternalA/Dconvertercircuitswillnotconsumepowerirrespectiveofwhatanalogvoltageisappliedtotheirinputlines.IftheA/DconverterinputlinesareusedasnormalI/Os,thencaremustbetakenasiftheinputvoltageisnotatavalidlogiclevel,thenthismayleadtosomeincreaseinpowerconsumption.
A/D Transfer FunctionAsthedevicescontaina12-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal toFFFH.Sincethefull-scaleanaloginputvalueisequaltotheVDDorVREFvoltage,thisgivesasinglebitanaloginputvalueofVDDorVREFdividedby4096.
1LSB=(VDDorVREF)÷4096
TheA/DConverterinputvoltagevaluecanbecalculatedusingthefollowingequation:
A/Dinputvoltage=A/Doutputdigitalvalue×(VDDorVREF)÷4096
Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefor theA/Dconverter.Exceptfor thedigitisedzerovalue, thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheVDDorVREFlevel.
Rev. 1.60 101 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
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Ideal A/D Transfer Function
A/D Programming ExampleThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheEOCBbit intheADCR0registerisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.
Example: using an EOCB polling method to detect the end of conversionclr ADE ; disable ADC interruptmov a, 03Hmov ADCR1,a ;selectfSYS/8asA/DclockandswitchoffVBGclr ADOFFmov a,0Fh ;setupACERLtoconfigurepinsAN0~AN3mov ACERL,amov a,00hmov ACERH,amov a, 00hmov ADCR0,a ;enableandconnectAN0channeltoA/Dconverter: Start_conversion:clr STARTset START ;resetA/Dclr START ;startA/DPolling_EOC:sz EOCB ;polltheADCR0registerEOCBbittodetectend ;ofA/Dconversionjmp polling_EOC ;continuepollingmov a,ADRL ;readlowbyteconversionresultvaluemov adrl_buffer,a ;saveresulttouserdefinedregistermov a,ADRH ;readhighbyteconversionresultvaluemov adrh_buffer,a ;saveresulttouserdefinedregister: jmp start_conversion ;startnextA/Dconversion
Rev. 1.60 10� �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Example: using the interrupt method to detect the end of conversionclr ADE ; disable ADC interruptmov a, 03Hmov ADCR1,a ;selectfSYS/8asA/DclockandswitchoffVBGclr ADOFFmov a,0Fh ;setupACERLtoconfigurepinsAN0~AN3mov ACERL,amov a,00hmov ACERH,amov a, 00hmov ADCR0,a ;enableandconnectAN0channeltoA/Dconverter: : Start_conversion:clr STARTset START ;resetA/Dclr START ;startA/Dclr ADF ;clearADCinterruptrequestflagset ADE ; enable ADC interrupt set EMI ;enableglobalinterrupt: : ; ADC interrupt service routine ADC_:mov acc_stack,a ;saveACCtouserdefinedmemorymov a,STATUSmov status_stack,a ;saveSTATUStouserdefinedmemory: : mov a,ADRL ;readlowbyteconversionresultvaluemov adrl_buffer,a ;saveresulttouserdefinedregistermov a,ADRH ;readhighbyteconversionresultvaluemov adrh_buffer,a ;saveresulttouserdefinedregister: : EXIT_ISR:mov a,status_stackmov STATUS,a ;restoreSTATUSfromuserdefinedmemorymov a,acc_stack ;restoreACCfromuserdefinedmemoryclr ADF ;clearADCinterruptflagreti
Rev. 1.60 103 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LCD Display MemoryThedevicesprovideanareaofembeddeddatamemoryforLCDdisplay.Thisareaislocatedfrom80Hto93HoftheRAMatSector1.TheMemoryPointerMP1HistheswitchbetweentheRAMandtheLCDdisplaymemory.WhentheMP1H=01H,datawritteninto80H~93HwillaffecttheLCDdisplay.WhentheMP1Hiswrittenotherthan01H,anydatawritteninto80H~93Hismeanttoaccessthegeneralpurposedatamemory.
TheLCDdisplaymemorycanbereadandwrittentoonlybyindirectaddressingmodeusingMP1LandMP1H.Whendata iswrittenintothedisplaydataarea, it isautomaticallyreadbytheLCDdriverwhichthengeneratesthecorrespondingLCDdrivingsignals.Toturnthedisplayonoroff,a“1”ora“0”iswrittentothecorrespondingbitof thedisplaymemory,respectively.ThefigureillustratesthemappingbetweenthedisplaymemoryandLCDpatternforthedevice.
�7 �6 �5 �4 �3 �� �1 �0
SEG0
SEG1
SEG�
180H
181H
SEG17
SEG18
SEG19
19�H
193H
COM7 COM6 COM5 COM4 COM3 COM� COM1 COM0
LCD Driver OutputTheoutputnumberofthedeviceLCDdrivercanbe20×4or20×8.TheLCDdriveris“R”typeonly.TheLCDclocksourceisfromfSUB,whichcanbeeithertheLXTorLIRCoscillator.
Rev. 1.60 104 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LCD Control Register
LCDC0 Register
Bit 7 6 5 4 3 2 1 0�a�e LCDE� TYPE DTYC BIAS — RSEL� RSEL1 RSEL0R/W R/W R/W R/W R/W — R/W R/W R/WPOR 0 0 0 0 — 0 0 0
Bit7 LCDEN:LCDenable/disablecontrol0:Disable1:Enable
Notethat theLCDdriverandA/DconvertershouldnotbeenabledsimultaneouslywhentheLCDoutputandA/Dchannelaresharedwiththesamepin.
Bit6 TYPE:LCDWaveformTypeselection0:TypeA1:TypeB
Bit5 DTYC:DefineLCDDuty0:1/4Duty(LCDCOM:COM0~COM3)1:1/8Duty(LCDCOM:COM0~COM7)
Note:IfDTYC=1,thenCOM4~COM7pinswillbeconfiguredasLCDCOM.IfDTYC=0,thenCOM4~COM7pinswillbeconfiguredasI/O.
Bit4 BIAS:DefineLCDBias0:1/3Bias1:1/4Bias
Bit3 Unimplemented,readas“0”Bit2~0 RSEL2~RSEL0:TotalBiasResistorRTselection
000:1170K001:225K010:60K011:QuickChargingMode,switchbetween60Kand1170K.1xx:QuickChargingMode,switchbetween60Kand225K.
Note:Thebiasresistorfor1/3biasisRT/3,1/4biasisRT/4.ThedevicesprovidelowpowerquickchargingmodeforLCDdisplay.Inquickchargingmode,theLCDwillprovideLCDbiascurrentbyRT=60K,atbeginningofLCDdisplayrefreshes(i.ethemomentonLCDCOMchanges).Afterquickchargingtime, thebiasresistorwillchangeto225K/1170K.
Rev. 1.60 105 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LCDC1 Register
Bit 7 6 5 4 3 2 1 0�a�e QCT� QCT1 QCT0 — VLCD3 VLCD� VLCD1 VLCD0R/W R/W R/W R/W — R/W R/W R/W R/WPOR 0 0 0 — 0 0 0 0
Bit7 QCT2~QCT0:Quickchargingtimeselection000:1×tSUB001:2×tSUB010:3×tSUB011:4×tSUB100:5×tSUB101:6×tSUB110:7×tSUB111:8×tSUB
tSUB=1/fSUBBit6~4 Unimplemented,readas"0"Bit3~0 VLCD3~VLCD0:VLCDselection
0000:8/16×VDD
0001:9/16×VDD
0010:10/16×VDD
0011:11/16×VDD
0100:12/16×VDD
0101:13/16×VDD
0110:14/16×VDD
0111:15/16×VDD
1000~1111:16/16×VDD
Rev. 1.60 106 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
SEGCR0 Register
Bit 7 6 5 4 3 2 1 0�a�e SEG7C SEG6C SEG5C SEG4C SEG3C SEG�C SEG1C SEG0CR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7 SEG7C:SelectSEG7orPD70:SEG71:PD7
Bit6 SEG6C:SelectSEG6orPD60:SEG61:PD6
Bit5 SEG5C:SelectSEG5orPD50:SEG51:PD5
Bit4 SEG4C:SelectSEG4orPD40:SEG41:PD4
Bit3 SEG3C:SelectSEG3orPD30:SEG31:PD3
Bit2 SEG2C:SelectSEG2orPD20:SEG21:PD2
Bit1 SEG1C:SelectSEG1orPD10:SEG11:PD1
Bit0 SEG0C:SelectSEG0orPD00:SEG01:PD0
Rev. 1.60 107 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
SEGCR1 Register
Bit 7 6 5 4 3 2 1 0�a�e SEG15C SEG14C SEG13C SEG1�C SEG11C SEG10C SEG9C SEG8CR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7 SEG15C:SelectSEG15orPC70:SEG151:PC7
Bit6 SEG14C:SelectSEG14orPC60:SEG141:PC6
Bit5 SEG13C:SelectSEG13orPC50:SEG131:PC5
Bit4 SEG12C:SelectSEG12orPC40:SEG121:PC4
Bit3 SEG11C:SelectSEG11orPC30:SEG111:PC3
Bit2 SEG10C:SelectSEG10orPC20:SEG101:PC2
Bit1 SEG9C:SelectSEG9orPC10:SEG91:PC1
Bit0 SEG8C:SelectSEG8orPC00:SEG81:PC0
SEGCR2 Register
Bit 7 6 5 4 3 2 1 0�a�e — — — — SEG19C SEG18C SEG17C SEG16CR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0
Bit7~4 Unimplemented,readas“0”Bit3 SEG19C:SelectSEG19orPF7
0:SEG191:PF7
Bit2 SEG18C:SelectSEG18orPF60:SEG181:PF6
Bit1 SEG17C:SelectSEG17orPF50:SEG171:PF5
Bit0 SEG16C:SelectSEG16orPF40:SEG161:PF4
Rev. 1.60 108 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LCD Waveform
LCD Display Off Mode
COM0 ~ COM3VA
All seng�ent outputs
Normal Operation Mode
COM0
COM1
COM�
COM3
All seg�ents a�e OFF
COM0 side seg�ents a�e O�
All seng�ents a�e O�
(othe� co��inations a�e o�itted)
VBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
1 F�a�e
COM1 side seg�ents a�e O�
COM� side seg�ents a�e O�
COM3 side seg�ents a�e O�
COM0�1 side seg�ents a�e O�
COM0�� side seg�ents a�e O�
COM0�3 side seg�ents a�e O�
LCD Driver Output – Type A - 1/4 Duty, 1/3 Bias
Note:VA=VLCD,VB=VLCD×2/3andVC=VLCD×1/3.
Rev. 1.60 109 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LCD Display Off Mode
COM0 ~ COM3VA
All seng�ent outputs
Normal Operation Mode
COM0
COM1
COM�
COM3
All seg�ents a�e OFF
COM0 side seg�ents a�e O�
All seng�ents a�e O�
(othe� co��inations a�e o�itted)
VBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
VAVBVCVSS
1 F�a�e
COM1 side seg�ents a�e O�
COM� side seg�ents a�e O�
COM3 side seg�ents a�e O�
COM0�1 side seg�ents a�e O�
COM0�� side seg�ents a�e O�
COM0�3 side seg�ents a�e O�
LCD Driver Output – Type B - 1/4 Duty, 1/3 Bias
Note:VA=VLCD,VB=VLCD×2/3andVC=VLCD×1/3.
Rev. 1.60 110 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
COM0COM0State1
(on)
State1(on)
State�(off)
State�(off)
LCD Seg�entLCD Seg�enttLCD
VLCDVLCD
VSSVSS
VLCD x 3/4VLCD x 3/4
VLCD x �/4VLCD x �/4
VLCD x 1/4VLCD x 1/4
COM1COM1
VLCDVLCD
VSSVSS
COM�COM�
VLCDVLCD
VSSVSS
COM3COM3
VLCDVLCD
VSSVSS
COM4COM4
VLCDVLCD
VSSVSS
COM5COM5
VLCDVLCD
VSSVSS
COM6COM6
VLCDVLCD
VSSVSS
COM7COM7
VLCDVLCD
VSSVSS
VLCDVLCD
VSSVSS
SEG nSEG n
VLCDVLCD
VSSVSS
SEG n+1SEG n+1
VSSVSS
SEG n+�SEG n+�
VLCDVLCD
VSSVSS
SEG n+3SEG n+3
VLCDVLCD
VLCD x 3/4VLCD x 3/4
VLCD x �/4VLCD x �/4
VLCD x 1/4VLCD x 1/4
VLCD x 3/4VLCD x 3/4
VLCD x �/4VLCD x �/4
VLCD x 1/4VLCD x 1/4
VLCD x 3/4VLCD x 3/4
VLCD x �/4VLCD x �/4
VLCD x 1/4VLCD x 1/4
VLCD x 3/4VLCD x 3/4
VLCD x �/4VLCD x �/4
VLCD x 1/4VLCD x 1/4
VLCD x 3/4VLCD x 3/4
VLCD x �/4VLCD x �/4
VLCD x 1/4VLCD x 1/4
VLCD x 3/4VLCD x 3/4
VLCD x �/4VLCD x �/4
VLCD x 1/4VLCD x 1/4
VLCD x 3/4VLCD x 3/4
VLCD x �/4VLCD x �/4
VLCD x 1/4VLCD x 1/4
VLCD x 3/4VLCD x 3/4
VLCD x �/4VLCD x �/4
VLCD x 1/4VLCD x 1/4
VLCD x 3/4VLCD x 3/4
VLCD x �/4VLCD x �/4
VLCD x 1/4VLCD x 1/4
VLCD x 3/4VLCD x 3/4
VLCD x �/4VLCD x �/4
VLCD x 1/4VLCD x 1/4
VLCD x 3/4VLCD x 3/4
VLCD x �/4VLCD x �/4
VLCD x 1/4VLCD x 1/4
LCD Driver Output – Type A - 1/8 Duty, 1/4 Bias
Rev. 1.60 111 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LED DriverThedevicescontainanLEDdriverfunctionofferinghighcurrentoutputdrivecapabilitywhichcanbeusedtodriveexternalLEDs.
LED Driver OperationThevariousI/OpinsofdeviceshaveacapabilityofprovidingLEDhighcurrentdriveoutputs,asshownintheaccompanyingtable.
Device LED Drive PinsHT67F488HT67F489
PD0~PD7 (high sou�ce cu��ent)PE0~PE7 (high sink cu��ent)
LED Driver Register
IOHR0 Register
Bit 7 6 5 4 3 2 1 0�a�e IOHS31 IOHS30 IOHS�1 IOHS�0 IOHS11 IOHS10 IOHS01 IOHS00R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
IOHR1 Register
Bit 7 6 5 4 3 2 1 0�a�e IOHS71 IOHS70 IOHS61 IOHS60 IOHS51 IOHS50 IOHS41 IOHS40R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
IOHSn[1:0]:IOHcapacityselectionforPDn(n=0~7)00:FulllysourcedrivingcapacityofGPIO01:1/3sourcedrivingcapacityofGPIO10:1/4sourcedrivingcapacityofGPIO11:1/6sourcedrivingcapacityofGPIO
Rev. 1.60 11� �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
UART InterfaceEachdevicecontainsanintegratedfull-duplexasynchronousserialcommunicationsUARTinterfacethatenablescommunicationwithexternaldevicesthatcontainaserialinterface.TheUARTfunctionhasmanyfeaturesandcantransmitandreceivedataseriallybytransferringaframeofdatawitheightorninedatabitsper transmissionaswellasbeingable todetecterrorswhen thedata isoverwrittenorincorrectlyframed.TheUARTfunctionpossessesitsowninternal interruptwhichcanbeusedtoindicatewhenareceptionoccursorwhenatransmissionterminates.
TheintegratedUARTfunctioncontainsthefollowingfeatures:
• Full-duplex,UniversalAsynchronousReceiverandTransmitter(UART)communication
• 8or9bitscharacterlength
• Even,oddornoparityoptions
• Oneortwostopbits
• Baudrategeneratorwith8-bitprescaler
• Parity,framing,noiseandoverrunerrordetection
• Supportforinterruptonaddressdetect(lastcharacterbit=1)
• Transmitterandreceiverenabledindependently
• 2-byteDeepFIFOReceiveDataBuffer
• TransmitandReceiveMultipleInterruptGenerationSources:♦ TransmitterEmpty♦ TransmitterIdle♦ ReceiverFull♦ ReceiverOverrun♦ AddressModeDetect♦ RXpinwake-upinterrupt
� � � � � � � � � � � � � � � � � � � � � � � �
� � � � � �
� � � � � � � � � � � � � � � � � � � � � � � � � � �
� � � � � � � � � � � �
� � � � � � � � � � � � � � � � � � � � � � �
� � � � � �
� � � � � � � �� � � � � � � � �
� � � � � �
� � �
� � � � � � � � � � �
UART Data Transfer Scheme
Rev. 1.60 113 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
UART External Pin InterfacingTocommunicatewithanexternalserialinterface,theinternalUARThastwoexternalpinsknownasTXandRX.TheTXpinistheUARTtransmitterpin,whichcanbeusedasageneralpurposeI/Oorotherpin-sharedfunctionalpin if thepin isnotconfiguredasaUARTtransmitter,whichoccurswhentheTXENbitintheUCR2controlregisterisequaltozero.Similarly,theRXpinistheUARTreceiverpin,whichcanalsobeusedasageneralpurposeI/Oorotherpin-sharedfunctionalpin,if thepinisnotconfiguredasareceiver,whichoccursiftheRXENbitintheUCR2registerisequaltozero.AlongwiththeUARTENbit,theTXENandRXENbits,ifset,willautomaticallysetup theseI/Oorotherpin-sharedfunctionalpins to their respectiveTXoutputandRXinputconditionsanddisableanypull-highresistoroptionwhichmayexistontheRXpin.IftheTXandRXpinsaresharedwiththeLCDoutputsandtheUARTinterfaceandLCDdriverbothareenabledsimultaneously,theLCDdriverhastheprioritytousethecorrespondingpinsasLCDoutputs.
UART Data Transfer SchemeTheblockdiagramshowstheoveralldatatransferstructurearrangementfortheUART.Theactualdata tobe transmittedfromtheMCUis first transferred to theTXRregisterby theapplicationprogram.Thedatawill thenbe transferredto theTransmitShiftRegisterfromwhere itwillbeshiftedout,LSBfirst,ontotheTXpinataratecontrolledbytheBaudRateGenerator.OnlytheTXRregisterismappedontotheMCUDataMemory,theTransmitShiftRegisterisnotmappedandisthereforeinaccessibletotheapplicationprogram.
DatatobereceivedbytheUARTisacceptedontheexternalRXpin,fromwhereit isshiftedin,LSBfirst, to theReceiverShiftRegisterataratecontrolledbytheBaudRateGenerator.Whentheshiftregisterisfull,thedatawillthenbetransferredfromtheshiftregistertotheinternalRXRregister,whereit isbufferedandcanbemanipulatedbytheapplicationprogram.OnlytheRXRregisterismappedontotheMCUDataMemory,theReceiverShiftRegisterisnotmappedandisthereforeinaccessibletotheapplicationprogram.
Itshouldbenotedthattheactualregisterfordatatransmissionandreception,althoughreferredtointhetext,andinapplicationprograms,asseparateTXRandRXRregisters,onlyexistsasasinglesharedregisterintheDataMemory.ThissharedregisterknownastheTXR/RXRregisterisusedforbothdatatransmissionanddatareception.
UART Status and Control RegistersTherearefivecontrolregistersassociatedwiththeUARTfunction.TheUSR,UCR1andUCR2registerscontroltheoverallfunctionoftheUART,whiletheBRGregistercontrolstheBaudrate.TheactualdatatobetransmittedandreceivedontheserialinterfaceismanagedthroughtheTXR/RXRdataregisters.
Register Name
Bit
7 6 5 4 3 2 1 0USR PERR �F FERR OERR RIDLE RXIF TIDLE TXIF
UCR1 UARTE� B�O PRE� PRT STOPS TXBRK RX8 TX8UCR� TXE� RXE� BRGH ADDE� WAKE RIE TIIE TEIE
TXR/RXR TXRX7 TXRX6 TXRX5 TXRX4 TXRX3 TXRX� TXRX1 TXRX0BRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG� BRG1 BRG0
UART Register List
Rev. 1.60 114 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
USR RegisterTheUSRregisteristhestatusregisterfortheUART,whichcanbereadbytheprogramtodeterminethepresentstatusoftheUART.AllflagswithintheUSRregisterarereadonly.Furtherexplanationoneachoftheflagsisgivenbelow:
Bit 7 6 5 4 3 2 1 0�a�e PERR �F FERR OERR RIDLE RXIF TIDLE TXIFR/W R R R R R R R RPOR 0 0 0 0 1 0 1 1
Bit7 PERR:Parityerrorflag0:Noparityerrorisdetected1:Parityerrorisdetected
ThePERRflagistheparityerrorflag.Whenthisreadonlyflagis“0”,itindicatesaparityerrorhasnotbeendetected.Whentheflagis“1”,itindicatesthattheparityofthereceivedwordisincorrect.ThiserrorflagisapplicableonlyifParitymode(oddoreven)isselected.TheflagcanalsobeclearedbyasoftwaresequencewhichinvolvesareadtothestatusregisterUSRfollowedbyanaccesstotheRXRdataregister.
Bit6 NF:Noiseflag0:Nonoiseisdetected1:Noiseisdetected
TheNFflagis thenoiseflag.Whenthisreadonlyflagis"0", it indicatesnonoisecondition.Whentheflagis"1",itindicatesthattheUARThasdetectednoiseonthereceiverinput.TheNFflagissetduringthesamecycleastheRXIFflagbutwillnotbesetinthecaseofasoverrun.TheNFflagcanbeclearedbyasoftwaresequencewhichwillinvolveareadtothestatusregisterUSRfollowedbyanaccesstotheRXRdataregister.
Bit5 FERR:Framingerrorflag0:Noframingerrorisdetected1:Framingerrorisdetected
TheFERRflagistheframingerrorflag.Whenthisreadonlyflagis“0”,itindicatesthat thereisnoframingerror.Whentheflagis“1”, it indicates thataframingerrorhasbeendetectedforthecurrentcharacter.TheflagcanalsobeclearedbyasoftwaresequencewhichwillinvolveareadtothestatusregisterUSRfollowedbyanaccesstotheRXRdataregister.
Bit4 OERR:Overrunerrorflag0:Nooverrunerrorisdetected1:Overrunerrorisdetected
TheOERRflagistheoverrunerrorflagwhichindicateswhenthereceiverbufferhasoverflowed.Whenthisreadonlyflagis“0”,itindicatesthatthereisnooverrunerror.Whentheflagis“1”,itindicatesthatanoverrunerroroccurswhichwillinhibitfurthertransferstotheRXRreceivedataregister.Theflagisclearedbyasoftwaresequence,which isa read to thestatusregisterUSRfollowedbyanaccess to theRXRdataregister.
Bit3 RIDLE:Receiverstatus0:Datareceptionisinprogress(databeingreceived)1:Nodatareceptionisinprogress(receiverisidle)
TheRIDLEflagisthereceiverstatusflag.Whenthisreadonlyflagis“0”,itindicatesthatthereceiverisbetweentheinitialdetectionofthestartbitandthecompletionofthestopbit.Whentheflagis“1”, it indicates that thereceiver is idle.Betweenthecompletionofthestopbitandthedetectionofthenextstartbit,theRIDLEbitis“1”indicatingthattheUARTreceiverisidleandtheRXpinstaysinlogichighcondition.
Rev. 1.60 115 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Bit2 RXIF:ReceiveRXRdataregisterstatus0:RXRdataregisterisempty1:RXRdataregisterhasavailabledata
TheRXIFflagisthereceivedataregisterstatusflag.Whenthisreadonlyflagis“0”,itindicatesthattheRXRreaddataregisterisempty.Whentheflagis“1”,itindicatesthat theRXRreaddataregistercontainsnewdata.When thecontentsof theshiftregisteraretransferredtotheRXRregister,aninterruptisgeneratedifRIE=1intheUCR2register.Ifoneormoreerrorsaredetectedinthereceivedword,theappropriatereceive-relatedflagsNF,FERR,and/orPERRaresetwithinthesameclockcycle.TheRXIFflagisclearedwhentheUSRregisterisreadwithRXIFset,followedbyareadfromtheRXRregister,andiftheRXRregisterhasnodataavailable.
Bit1 TIDLE:Transmissionidle0:Datatransmissionisinprogress(databeingtransmitted)1:Nodatatransmissionisinprogress(transmitterisidle)
TheTIDLEflag isknownas the transmissioncompleteflag.Whenthis readonlyflagis“0”,it indicatesthatatransmissionisinprogress.Thisflagwillbesetto“1”whentheTXIFflagis“1”andwhenthereisnotransmitdataorbreakcharacterbeingtransmitted.WhenTIDLEisequalto“1”,theTXpinbecomesidlewiththepinstateinlogichighcondition.TheTIDLEflagisclearedbyreadingtheUSRregisterwithTIDLEsetandthenwritingtotheTXRregister.Theflagisnotgeneratedwhenadatacharacterorabreakisqueuedandreadytobesent.
Bit0 TXIF:TransmitTXRdataregisterstatus0:Characterisnottransferredtothetransmitshiftregister1:Characterhastransferredtothetransmitshiftregister(TXRdataregisterisempty)
TheTXIFflagisthetransmitdataregisteremptyflag.Whenthisreadonlyflagis“0”,itindicatesthatthecharacterisnottransferredtothetransmittershiftregister.Whentheflagis“1”,it indicatesthatthetransmittershiftregisterhasreceivedacharacterfromtheTXRdataregister.TheTXIFflag isclearedbyreadingtheUARTstatusregister(USR)withTXIFsetandthenwriting to theTXRdataregister.Note thatwhentheTXENbit isset, theTXIFflagbitwillalsobesetsincethetransmitdataregisterisnotyetfull.
Rev. 1.60 116 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
UCR1 RegisterTheUCR1registertogetherwiththeUCR2registerarethetwoUARTcontrolregistersthatareusedtosetthevariousoptionsfortheUARTfunction,suchasoverallon/offcontrol,paritycontrol,datatransferbitlengthetc.Furtherexplanationoneachofthebitsisgivenbelow:
Bit 7 6 5 4 3 2 1 0�a�e UARTE� B�O PRE� PRT STOPS TXBRK RX8 TX8R/W R/W R/W R/W R/W R/W R/W R WPOR 0 0 0 0 0 0 x 0
“x” unknownBit7 UARTEN:UARTfunctionenablecontrol
0:DisableUART.TXandRXpinsareasI/Oorotherpin-sharedfunctionalpins1:EnableUART.TXandRXpinsfunctionasUARTpins
TheUARTENbitistheUARTenablebit.IftheTXandRXpinsaresharedwiththeLCDoutputsandtheUARTinterfaceandLCDdriverarebothenabledsimultaneously,theLCDdriverwillhavetheprioritytousethecorrespondingpinsasLCDoutputs.Whenthisbitisequalto“0”,theUARTwillbedisabledandtheRXpinaswellastheTXpinwillbeasGeneralPurposeI/Oorotherpin-sharedfunctionalpins.Whenthebitisequalto“1”,theUARTwillbeenabledandtheTXandRXpinswillfunctionasdefinedbytheTXENandRXENenablecontrolbits.WhentheUARTisdisabled, itwillemptythebuffersoanycharacterremaininginthebufferwillbediscarded.Inaddition, thevalueof thebaudratecounterwillbereset.IftheUARTisdisabled,allerrorandstatusflagswillbereset.AlsotheTXEN,RXEN,TXBRK,RXIF,OERR,FERR,PERRandNFbitswillbecleared,whiletheTIDLE,TXIFandRIDLEbitswillbeset.Othercontrolbits inUCR1,UCR2andBRGregisterswillremainunaffected.IftheUARTisactiveandtheUARTENbitiscleared,allpendingtransmissionsandreceptionswillbeterminatedandthemodulewillberesetasdefinedabove.WhentheUARTisre-enabled, itwill restart in thesameconfiguration.
Bit6 BNO:Numberofdatatransferbitsselection0:8-bitdatatransfer1:9-bitdatatransfer
Thisbit isusedtoselect thedata lengthformat,whichcanhaveachoiceofeither8-bitor9-bitformat.Whenthisbitisequalto“1”,a9-bitdatalengthformatwillbeselected.Ifthebitisequalto“0”,thenan8-bitdatalengthformatwillbeselected.If9-bitdatalengthformatisselected,thenbitsRX8andTX8willbeusedtostorethe9thbitofthereceivedandtransmitteddatarespectively.
Bit5 PREN:Parityfunctionenablecontrol0:Parityfunctionisdisabled1:Parityfunctionisenabled
Thisistheparityenablebit.Whenthisbitisequalto“1”,theparityfunctionwillbeenabled.Ifthebitisequalto“0”,thentheparityfunctionwillbedisabled.Replacethemostsignificantbitpositionwithaparitybit.
Bit4 PRT:Paritytypeselectionbit0:Evenparityforparitygenerator1:Oddparityforparitygenerator
Thisbitistheparitytypeselectionbit.Whenthisbitisequalto“1”,oddparitytypewillbeselected.Ifthebitisequalto“0”,thenevenparitytypewillbeselected.
Bit3 STOPS:NumberofStopbitsselection0:Onestopbitformatisused1:Twostopbitsformatisused
Thisbitdeterminesifoneortwostopbitsaretobeused.Whenthisbitisequalto“1”,twostopbitsareused.Ifthisbitisequalto“0”,thenonlyonestopbitisused.
Rev. 1.60 117 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Bit2 TXBRK:Transmitbreakcharacter0:Nobreakcharacteristransmitted1:Breakcharacterstransmit
TheTXBRKbit is theTransmitBreakCharacterbit.Whenthisbit is“0”, therearenobreakcharactersandtheTXpinoperatesnormally.Whenthebitis“1”,therearetransmitbreakcharactersandthetransmitterwillsendlogiczeros.Whenthisbit isequalto“1”,afterthebuffereddatahasbeentransmitted,thetransmitteroutputisheldlowforaminimumofa13-bitlengthanduntiltheTXBRKbitisreset.
Bit1 RX8:Receivedatabit8for9-bitdatatransferformat(readonly)Thisbitisonlyusedif9-bitdatatransfersareused,inwhichcasethisbitlocationwillstorethe9thbitofthereceiveddataknownasRX8.TheBNObitisusedtodeterminewhetherdatatransfersarein8-bitor9-bitformat.
Bit0 TX8:Transmitdatabit8for9-bitdatatransferformat(writeonly)Thisbit isonlyusedif9-bitdata transfersareused, inwhichcasethisbit locationwillstorethe9thbitofthetransmitteddataknownasTX8.TheBNObitisusedtodeterminewhetherdatatransfersarein8-bitor9-bitformat.
UCR2 RegisterTheUCR2registeristhesecondofthetwoUARTcontrolregistersandservesseveralpurposes.Oneofitsmainfunctionsistocontrolthebasicenable/disableoperationoftheUARTTransmitterandReceiveraswellasenablingthevariousUARTinterruptsources.Theregisteralsoservestocontrolthebaudratespeed,receiverwake-upenableandtheaddressdetectenable.Furtherexplanationoneachofthebitsisgivenbelow:
Bit 7 6 5 4 3 2 1 0�a�e TXE� RXE� BRGH ADDE� WAKE RIE TIIE TEIER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7 TXEN:UARTTransmitterenabledcontrol0:UARTtransmitterisdisabled1:UARTtransmitterisenabled
ThebitnamedTXENistheTransmitterEnableBit.Whenthisbitisequalto“0”,thetransmitterwillbedisabledwithanypendingdata transmissionsbeingaborted. Inadditionthebufferswillbereset.InthissituationtheTXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.If theTXENbit is equal to “1”and theUARTENbit is also equal to “1”, thetransmitterwillbeenabledandtheTXpinwillbecontrolledbytheUART.ClearingtheTXENbitduringatransmissionwillcausethedatatransmissiontobeabortedandwillresetthetransmitter.Ifthissituationoccurs,theTXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.
Bit6 RXEN:UARTReceiverenabledcontrol0:UARTreceiverisdisabled1:UARTreceiverisenabled
ThebitnamedRXENistheReceiverEnableBit.Whenthisbit isequalto“0”,thereceiverwillbedisabledwithanypendingdatareceptionsbeingaborted.Inadditionthereceivebufferswillbereset.InthissituationtheRXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.IftheRXENbitisequalto“1”andtheUARTENbitisalsoequalto“1”,thereceiverwillbeenabledandtheRXpinwillbecontrolledbytheUART.ClearingtheRXENbitduringareceptionwillcausethedatareceptiontobeabortedandwillresetthereceiver.Ifthissituationoccurs,theRXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.
Rev. 1.60 118 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Bit5 BRGH:BaudRatespeedselection0:Lowspeedbaudrate1:Highspeedbaudrate
ThebitnamedBRGHselectsthehighorlowspeedmodeoftheBaudRateGenerator.Thisbit, togetherwith thevalueplacedinthebaudrateregisterBRG,controls theBaudRateoftheUART.Ifthisbitisequalto“1”,thehighspeedmodeisselected.Ifthebitisequalto“0”,thelowspeedmodeisselected.
Bit4 ADDEN:Addressdetectfunctionenablecontrol0:Addressdetectfunctionisdisabled1:Addressdetectfunctionisenabled
ThebitnamedADDENistheaddressdetectfunctionenablecontrolbit.Whenthisbit isequalto“1”,theaddressdetectfunctionisenabled.Whenitoccurs,if the8thbit,whichcorrespondstoRX7ifBNO=0orthe9thbit,whichcorrespondstoRX8ifBNO=1,hasavalueof“1”,thenthereceivedwordwillbeidentifiedasanaddress,ratherthandata.Ifthecorrespondinginterruptisenabled,aninterruptrequestwillbegeneratedeachtimethereceivedwordhastheaddressbitset,whichisthe8thor9thbitdependingonthevalueofBNO.Iftheaddressbitknownasthe8thor9thbitofthereceivedwordis“0”withtheaddressdetectfunctionbeingenabled,aninterruptwillnotbegeneratedandthereceiveddatawillbediscarded.
Bit3 WAKE:RXpinfallingedgewake-upfunctionenablecontrol0:RXpinwake-upfunctionisdisabled1:RXpinwake-upfunctionisenabled
Thisbitenablesordisablesthereceiverwake-upfunction.Ifthisbit isequalto“1”andtheMCUisintheSLEEPmode,afallingedgeontheRXinputpinwillwake-up thedevice.Please reference theUARTRXpinwake-upfunctions indifferentoperatingmodeforthedetail.Ifthisbitisequalto“0”andtheMCUisintheSLEEPmode,anyedgetransitionsontheRXpinwillnotwake-upthedevice.
Bit2 RIE:Receiverinterruptenablecontrol0:Receiverrelatedinterruptisdisabled1:Receiverrelatedinterruptisenabled
Thisbitenablesordisablesthereceiverinterrupt.Ifthisbitisequalto“1”andwhenthereceiveroverrunflagOERRorreceivedataavailableflagRXIFisset,theUARTinterruptrequestflagwillbeset.Ifthisbitisequalto“0”,theUARTinterruptrequestflagwillnotbeinfluencedbytheconditionoftheOERRorRXIFflags.
Bit1 TIIE:TransmitterIdleinterruptenablecontrol0:Transmitteridleinterruptisdisabled1:Transmitteridleinterruptisenabled
Thisbitenablesordisablesthetransmitteridleinterrupt.Ifthisbitisequalto“1”andwhenthetransmitter idleflagTIDLEisset,duetoa transmitter idlecondition, theUARTinterruptrequestflagwillbeset.Ifthisbitisequalto“0”,theUARTinterruptrequestflagwillnotbeinfluencedbytheconditionoftheTIDLEflag.
Bit0 TEIE:TransmitterEmptyinterruptenablecontrol0:Transmitteremptyinterruptisdisabled1:Transmitteremptyinterruptisenabled
Thisbitenablesordisablesthetransmitteremptyinterrupt.Ifthisbitisequalto“1”andwhenthetransmitteremptyflagTXIFisset,duetoatransmitteremptycondition,theUARTinterrupt request flagwillbeset. If thisbit isequal to“0”, theUARTinterruptrequestflagwillnotbeinfluencedbytheconditionoftheTXIFflag.
Rev. 1.60 119 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
TXR/RXR Register
Bit 7 6 5 4 3 2 1 0�a�e TXRX7 TXRX6 TXRX5 TXRX4 TXRX3 TXRX� TXRX1 TXRX0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x
“x” unknownBit7~0 TXRX7~TXRX0:UARTTransmit/ReceiveDatabit7~bit0
BRG Register
Bit 7 6 5 4 3 2 1 0�a�e BRG7 BRG6 BRG5 BRG4 BRG3 BRG� BRG1 BRG0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x
“x” unknownBit7~0 BRG7~BRG0:BaudRatevalues
Byprogramming theBRGHbit inUCR2Registerwhichallowsselectionof therelatedformuladescribedaboveandprogramming therequiredvalue in theBRGregister,therequiredbaudratecanbesetup.Note:Baudrate=fSYS/[64×(N+1)]ifBRGH=0.
Baudrate=fSYS/[16×(N+1)]ifBRGH=1.
Baud Rate GeneratorTosetupthespeedoftheserialdatacommunication,theUARTfunctioncontainsitsowndedicatedbaudrategenerator.Thebaudrate iscontrolledbyitsowninternalfreerunning8-bit timer, theperiodofwhichisdeterminedbytwofactors.ThefirstoftheseisthevalueplacedinthebaudrateregisterBRGandthesecondis thevalueof theBRGHbitwith thecontrolregisterUCR2.TheBRGHbitdecidesifthebaudrategeneratoristobeusedinahighspeedmodeorlowspeedmode,whichinturndeterminestheformulathatisusedtocalculatethebaudrate.ThevalueNintheBRGregisterwhichisusedinthefollowingbaudratecalculationformuladeterminesthedivisionfactor.NotethatNisthedecimalvalueplacedintheBRGregisterandhasarangeofbetween0and255.
UCR2 BRGH Bit 0 1Baud Rate (BR) fSYS / [64 (�+1)] fSYS / [16 (�+1)]
ByprogrammingtheBRGHbitwhichallowsselectionoftherelatedformulaandprogrammingtherequiredvalueintheBRGregister,therequiredbaudratecanbesetup.Notethatbecausetheactualbaudrateisdeterminedusingadiscretevalue,N,placedintheBRGregister,therewillbeanerrorassociatedbetweentheactualandrequestedvalue.ThefollowingexampleshowshowtheBRGregistervalueNandtheerrorvaluecanbecalculated.
Rev. 1.60 1�0 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Calculating the Register and Error ValuesForaclockfrequencyof4MHz,andwithBRGHsetto“0”determinetheBRGregistervalueN,theactualbaudrateandtheerrorvalueforadesiredbaudrateof4800.
FromtheabovetablethedesiredbaudrateBR=fSYS/[64(N+1)]
Re-arrangingthisequationgivesN=[fSYS/(BR×64)]-1
GivingavalueforN=[4000000/(4800×64)]-1=12.0208
Toobtaintheclosestvalue,adecimalvalueof12shouldbeplacedintotheBRGregister.ThisgivesanactualorcalculatedbaudratevalueofBR=4000000/[64×(12+1)]=4808
Thereforetheerrorisequalto(4808-4800)/4800=0.16%
ThefollowingtableshowsactualvaluesofbaudrateanderrorvaluesforthetwovaluesofBRGH.
Baud RateK/BPS
fSYS=8MHz
Baud Rates for BRGH=0 Baud Rates for BRGH=1
BRG Kbaud Error (%) BRG Kbaud Error (%)
0.3 — — — — — —1.� 103 1.�0� 0.16 — — —�.4 51 �.404 0.16 �07 �.404 0.164.8 �5 4.808 0.16 103 4.808 0.169.6 1� 9.615 0.16 51 9.615 0.1619.� 6 17.8857 -6.99 �5 19.�31 0.1638.4 � 41.667 8.51 1� 38.46� 0.1657.6 1 6�.500 8.51 8 55.556 -3.55115.� 0 1�5 8.51 3 1�5 8.51�50 — — — 1 �50 0
Baud Rates and Error Values
UART Setup and ControlFordatatransfer,theUARTfunctionutilizesanon-return-to-zero,morecommonlyknownasNRZ,format.Thisiscomposedofonestartbit,eightorninedatabits,andoneortwostopbits.ParityissupportedbytheUARThardware,andcanbesetuptobeeven,oddornoparity.Forthemostcommondataformat,8databitsalongwithnoparityandonestopbit,denotedas8,N,1,isusedasthedefaultsetting,whichisthesettingatpower-on.Thenumberofdatabitsandstopbits,alongwiththeparity,aresetupbyprogrammingthecorrespondingBNO,PRT,PREN,andSTOPSbitsin theUCR1register.Thebaudrateusedtotransmitandreceivedata issetupusingtheinternal8-bitbaudrategenerator,whilethedataistransmittedandreceivedLSBfirst.AlthoughtheUARTtransmitterandreceiverarefunctionallyindependent,theybothusethesamedataformatandbaudrate.Inallcasesstopbitswillbeusedfordatatransmission.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Enabling/Disabling the UARTThebasicon/offfunctionoftheinternalUARTfunctioniscontrolledusingtheUARTENbitintheUCR1register.IftheUARTEN,TXENandRXENbitsareset,thenthesetwoUARTpinswillactasnormalTXoutputpinandRXinputpinrespectively.IfnodataisbeingtransmittedontheTXpin,thenitwilldefaulttoalogichighvalue.
ClearingtheUARTENbitwilldisabletheTXandRXpinsandallowthesetwopinstobeusedasnormalI/Oorotherpin-sharedfunctionalpins.WhentheUARTfunctionisdisabledthebufferwillberesettoanemptycondition,atthesametimediscardinganyremainingresidualdata.DisablingtheUARTwillalsoresettheerrorandstatusflagswithbitsTXEN,RXEN,TXBRK,RXIF,OERR,FERR,PERRandNFbeingclearedwhilebitsTIDLE,TXIFandRIDLEwillbeset.TheremainingcontrolbitsintheUCR1,UCR2andBRGregisterswillremainunaffected.IftheUARTENbitintheUCR1registerisclearedwhiletheUARTisactive,thenallpendingtransmissionsandreceptionswillbeimmediatelysuspendedandtheUARTwillberesettoaconditionasdefinedabove.IftheUARTisthensubsequentlyre-enabled,itwillrestartagaininthesameconfiguration.
Data, Parity and Stop bit SelectionTheformatof thedata tobe transferred iscomposedofvariousfactorssuchasdatabit length,parityon/off,paritytype,addressbitsandthenumberofstopbits.ThesefactorsaredeterminedbythesetupofvariousbitswithintheUCR1register.TheBNObitcontrols thenumberofdatabitswhichcanbesettoeither8or9,thePRTbitcontrolsthechoiceofoddorevenparity,thePRENbitcontrolstheparityon/offfunctionandtheSTOPSbitdecideswhetheroneortwostopbitsaretobeused.Thefollowingtableshowsvariousformatsfordatatransmission.Theaddressbitidentifiestheframeasanaddresscharacter.Thenumberofstopbits,whichcanbeeitheroneor two, isindependentofthedatalength.
Start Bit Data Bits Address Bits Parity Bits Stop BitExample of 8-bit Data Formats
1 8 0 0 11 7 0 1 11 7 1 0 1
Example of 9-bit Data Formats1 9 0 0 11 8 0 1 11 8 1 0 1
Transmitter Receiver Data Format
Thefollowingdiagramshows the transmitandreceivewaveformsforboth8-bitand9-bitdataformats.
� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �
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� � � �
Rev. 1.60 1�� �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
UART TransmitterDatawordlengthsofeither8or9bitscanbeselectedbyprogrammingtheBNObitintheUCR1register.WhenBNObitisset,thewordlengthwillbesetto9bits.Inthiscasethe9thbit,whichistheMSB,needstobestoredintheTX8bitintheUCR1register.AtthetransmittercoreliestheTransmitterShiftRegister,morecommonlyknownas theTSR,whosedata isobtainedfromthetransmitdataregister,whichisknownas theTXRregister.Thedata tobe transmittedis loadedintothisTXRregisterbytheapplicationprogram.TheTSRregisterisnotwrittentowithnewdatauntilthestopbitfromtheprevioustransmissionhasbeensentout.Assoonasthisstopbithasbeentransmitted,theTSRcanthenbeloadedwithnewdatafromtheTXRregister, ifit isavailable.ItshouldbenotedthattheTSRregister,unlikemanyotherregisters, isnotdirectlymappedintotheDataMemoryareaandassuch isnotavailable to theapplicationprogramfordirect read/writeoperations.AnactualtransmissionofdatawillnormallybeenabledwhentheTXENbitisset,butthedatawillnotbetransmitteduntiltheTXRregisterhasbeenloadedwithdataandthebaudrategeneratorhasdefinedashiftclocksource.However,thetransmissioncanalsobeinitiatedbyfirstloadingdataintotheTXRregister,afterwhichtheTXENbitcanbeset.Whenatransmissionofdatabegins,theTSRisnormallyempty,inwhichcaseatransfertotheTXRregisterwillresultinanimmediatetransfertotheTSR.IfduringatransmissiontheTXENbitiscleared,thetransmissionwillimmediatelyceaseandthetransmitterwillbereset.TheTXoutputpinwillthenreturntotheI/Oorotherpin-sharedfunction.
Transmitting DataWhentheUARTistransmittingdata,thedataisshiftedontheTXpinfromtheshiftregister,withthe leastsignificantbit first. In the transmitmode, theTXRregisterformsabufferbetweentheinternalbusandthetransmittershiftregister.Itshouldbenotedthatif9-bitdataformathasbeenselected,thentheMSBwillbetakenfromtheTX8bitintheUCR1register.Thestepstoinitiateadatatransfercanbesummarizedasfollows:
• MakethecorrectselectionoftheBNO,PRT,PRENandSTOPSbitstodefinetherequiredwordlength,paritytypeandnumberofstopbits.
• SetuptheBRGregistertoselectthedesiredbaudrate.
• SettheTXENbittoensurethattheTXpinisusedasaUARTtransmitterpin.
• AccesstheUSRregisterandwritethedatathatistobetransmittedintotheTXRregister.NotethatthisstepwillcleartheTXIFbit.
Thissequenceofeventscannowberepeatedtosendadditionaldata.
ItshouldbenotedthatwhenTXIF=0,datawillbeinhibitedfrombeingwrittentotheTXRregister.ClearingtheTXIFflagisalwaysachievedusingthefollowingsoftwaresequence:
• AUSRregisteraccess
• ATXRregisterwriteexecution
Theread-onlyTXIFflagissetbytheUARThardwareandifsetindicatesthattheTXRregisterisemptyandthatotherdatacannowbewrittenintotheTXRregisterwithoutoverwritingthepreviousdata.IftheTEIEbitissetthentheTXIFflagwillgenerateaninterrupt.
Rev. 1.60 1�3 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Duringadatatransmission,awriteinstructiontotheTXRregisterwillplacethedataintotheTXRregister,whichwillbecopiedtotheshiftregisterattheendofthepresenttransmission.Whenthereisnodatatransmissioninprogress,awriteinstructiontotheTXRregisterwillplacethedatadirectlyintotheshiftregister,resultinginthecommencementofdatatransmission,andtheTXIFbitbeingimmediatelyset.Whenaframetransmissioniscomplete,whichhappensafterstopbitsaresentorafterthebreakframe,theTIDLEbitwillbeset.TocleartheTIDLEbitthefollowingsoftwaresequenceisused:
• AUSRregisteraccess
• ATXRregisterwriteexecution
NotethatboththeTXIFandTIDLEbitsareclearedbythesamesoftwaresequence.
Transmit BreakIftheTXBRKbitissetthenbreakcharacterswillbesentonthenexttransmission.Breakcharactertransmissionconsistsofastartbit,followedby13×N‘0’bitsandstopbits,whereN=1,2,etc.IfabreakcharacteristobetransmittedthentheTXBRKbitmustbefirstsetbytheapplicationprogram,thenclearedtogeneratethestopbits.Transmittingabreakcharacterwillnotgenerateatransmitinterrupt.Notethatabreakconditionlengthisatleast13bitslong.IftheTXBRKbitiscontinuallykeptata logichighlevel thenthetransmittercircuitrywill transmitcontinuousbreakcharacters.AftertheapplicationprogramhasclearedtheTXBRKbit,thetransmitterwillfinishtransmittingthelastbreakcharacterandsubsequentlysendoutoneortwostopbits.Theautomaticlogichighsattheendofthelastbreakcharacterwillensurethatthestartbitofthenextframeisrecognized.
UART ReceiverTheUARTiscapableofreceivingwordlengthsofeither8or9bits.IftheBNObitisset,thewordlengthwillbesetto9bitswiththeMSBbeingstoredintheRX8bitoftheUCR1register.AtthereceivercoreliestheReceiveSerialShiftRegister,commonlyknownastheRSR.ThedatawhichisreceivedontheRXexternalinputpin,issenttothedatarecoveryblock.Thedatarecoveryblockoperatingspeedis16timesthatofthebaudrate,whilethemainreceiveserialshifteroperatesatthebaudrate.AftertheRXpinissampledforthestopbit,thereceiveddatainRSRistransferredtothereceivedataregister,iftheregisterisempty.ThedatawhichisreceivedontheexternalRXinputpinissampledthreetimesbyamajoritydetectcircuittodeterminethelogiclevelthathasbeenplacedontotheRXpin.ItshouldbenotedthattheRSRregister,unlikemanyotherregisters,isnotdirectlymappedintotheDataMemoryareaandassuchisnotavailabletotheapplicationprogramfordirectread/writeoperations.
Receiving DataWhentheUARTreceiverisreceivingdata,thedataisseriallyshiftedinontheexternalRXinputpin,LSBfirst.Inthereadmode,theRXRregisterformsabufferbetweentheinternalbusandthereceivershiftregister.TheRXRregisterisatwobytedeepFIFOdatabuffer,wheretwobytescanbeheldintheFIFOwhileathirdbytecancontinuetobereceived.Notethattheapplicationprogrammustensure that thedata is read fromRXRbefore the thirdbytehasbeencompletelyshiftedin,otherwise this thirdbytewillbediscardedandanoverrunerrorOERRwillbesubsequentlyindicated.Thestepstoinitiateadatatransfercanbesummarizedasfollows:
• MakethecorrectselectionofBNO,PRT,PRENandSTOPSbitstodefinethewordlength,paritytypeandnumberofstopbits.
• SetuptheBRGregistertoselectthedesiredbaudrate.
• SettheRXENbittoensurethattheRXpinisusedasaUARTreceiverpin.
Rev. 1.60 1�4 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Atthispointthereceiverwillbeenabledwhichwillbegintolookforastartbit.
Whenacharacterisreceivedthefollowingsequenceofeventswilloccur:
• TheRXIFbitintheUSRregisterwillbesetwhenRXRregisterhasdataavailable,atleastonemorecharactercanberead.
• WhenthecontentsoftheshiftregisterhavebeentransferredtotheRXRregister,theniftheRIEbitisset,aninterruptwillbegenerated.
• Ifduringreception,aframeerror,noiseerror,parityerror,oranoverrunerrorhasbeendetected,thentheerrorflagscanbeset.
TheRXIFbitcanbeclearedusingthefollowingsoftwaresequence:
• AUSRregisteraccess
• AnRXRregisterreadexecution
Receive BreakAnybreakcharacterreceivedbytheUARTwillbemanagedasaframingerror.ThereceiverwillcountandexpectacertainnumberofbittimesasspecifiedbythevaluesprogrammedintotheBNOandSTOPSbits.Ifthebreakismuchlongerthan13bittimes,thereceptionwillbeconsideredascompleteafterthenumberofbittimesspecifiedbyBNOandSTOPS.TheRXIFbitisset,FERRisset,zerosareloadedintothereceivedataregister,interruptsaregeneratedifappropriateandtheRIDLEbitisset.Ifalongbreaksignalhasbeendetectedandthereceiverhasreceivedastartbit,thedatabitsandtheinvalidstopbit,whichsetstheFERRflag,thereceivermustwaitforavalidstopbitbefore lookingfor thenextstartbit.Thereceiverwillnotmaketheassumptionthat thebreakconditiononthelineisthenextstartbit.AbreakisregardedasacharacterthatcontainsonlyzeroswiththeFERRflagset.Thebreakcharacterwillbeloadedintothebufferandnofurtherdatawillbereceiveduntilstopbitsarereceived.ItshouldbenotedthattheRIDLEreadonlyflagwillgohighwhenthestopbitshavenotyetbeenreceived.ThereceptionofabreakcharacterontheUARTregisterswillresultinthefollowing:
• Theframingerrorflag,FERR,willbeset.
• Thereceivedataregister,RXR,willbecleared.
• TheOERR,NF,PERR,RIDLEorRXIFflagswillpossiblybeset.
Idle StatusWhenthereceiverisreadingdata,whichmeansitwillbeinbetweenthedetectionofastartbitandthereadingofastopbit,thereceiverstatusflagintheUSRregister,otherwiseknownastheRIDLEflag,willhaveazerovalue.Inbetweenthereceptionofastopbitandthedetectionofthenextstartbit,theRIDLEflagwillhaveahighvalue,whichindicatesthereceiverisinanidlecondition.
Receiver interruptThereadonlyreceiveinterruptflagRXIFintheUSRregister issetbyanedgegeneratedbythereceiver.Aninterrupt isgenerated ifRIE=1,whenawordis transferredfromtheReceiveShiftRegister,RSR,totheReceiveDataRegister,RXR.AnoverrunerrorcanalsogenerateaninterruptifRIE=1.
Rev. 1.60 1�5 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Managing Receiver ErrorsSeveraltypesofreceptionerrorscanoccurwithintheUARTmodule,thefollowingsectiondescribesthevarioustypesandhowtheyaremanagedbytheUART.
Overrun Error – OERR FlagTheRXRregisteriscomposedofatwobytedeepFIFOdatabuffer,wheretwobytescanbeheldintheFIFOregister,whileathirdbytecancontinuetobereceived.Beforethisthirdbytehasbeenentirelyshiftedin,thedatashouldbereadfromtheRXRregister.If thisisnotdone,theoverrunerrorflagOERRwillbeconsequentlyindicated.
Intheeventofanoverrunerroroccurring,thefollowingwillhappen:
• TheOERRflagintheUSRregisterwillbeset.
• TheRXRcontentswillnotbelost.
• Theshiftregisterwillbeoverwritten.
• AninterruptwillbegeneratediftheRIEbitisset.
TheOERRflagcanbeclearedbyanaccess to theUSRregisterfollowedbyareadto theRXRregister.
Noise Error – NF FlagOver-sampling isusedfordata recovery to identifyvalid incomingdataandnoise. Ifnoise isdetectedwithinaframethefollowingwilloccur:
• Thereadonlynoiseflag,NF,intheUSRregisterwillbesetontherisingedgeoftheRXIFbit.
• DatawillbetransferredfromtheShiftregistertotheRXRregister.
• Nointerruptwillbegenerated.Howeverthisbitrisesat thesametimeastheRXIFbitwhichitselfgeneratesaninterrupt.
NotethattheNFflagisresetbyaUSRregisterreadoperationfollowedbyanRXRregisterreadoperation.
Framing Error – FERR FlagThereadonlyframingerrorflag,FERR,intheUSRregister,issetifazeroisdetectedinsteadofstopbits.Iftwostopbitsareselected,bothstopbitsmustbehigh,otherwisetheFERRflagwillbeset.TheFERRflagisbufferedalongwiththereceiveddataandisclearedonanyreset.
Parity Error – PERR FlagThereadonlyparityerrorflag,PERR,intheUSRregister,issetiftheparityofthereceivedwordisincorrect.Thiserrorflagisonlyapplicableiftheparityisenabled,PREN=1,andiftheparitytype,oddorevenisselected.ThereadonlyPERRflagisbufferedalongwiththereceiveddatabytes.Itisclearedonanyreset.ItshouldbenotedthattheFERRandPERRflagsarebufferedalongwiththecorrespondingwordandshouldbereadbeforereadingthedataword.
Rev. 1.60 1�6 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
UART Module Interrupt StructureSeveralindividualUARTconditionscangenerateaUARTinterrupt.Whentheseconditionsexist,a lowpulsewillbegeneratedtoget theattentionof themicrocontroller.Theseconditionsareatransmitterdataregisterempty, transmitter idle,receiverdataavailable,receiveroverrun,addressdetectandanRXpinwake-up.Whenanyof theseconditionsarecreated, if itscorrespondinginterruptcontrol isenabledandthestackisnotfull, theprogramwill jumpto itscorrespondinginterruptvectorwhere itcanbeservicedbefore returning to themainprogram.Fourof theseconditionshavethecorrespondingUSRregisterflagswhichwillgenerateaUARTinterruptif itsassociated interruptenablecontrolbit in theUCR2register isset.The twotransmitter interruptconditionshave theirowncorrespondingenablecontrolbits,while the two receiver interruptconditionshaveasharedenablecontrolbit.TheseenablebitscanbeusedtomaskoutindividualUARTinterruptsources.
Theaddressdetectcondition,whichisalsoaUARTinterruptsource,doesnothaveanassociatedflag,butwillgenerateaUARTinterruptwhenanaddressdetectconditionoccurs if itsfunctionisenabledbysettingtheADDENbit in theUCR2register.AnRXpinwake-up,whichisalsoaUARTinterruptsource,doesnothaveanassociatedflag,butwillgenerateaUARTinterruptifthemicrocontrolleriswokenupbyafallingedgeontheRXpin,iftheWAKEandRIEbitsintheUCRregisterareset.NotethatintheeventofanRXwake-upinterruptoccurring,therewillbeacertainperiodofdelay,commonlyknownas theSystemStart-upTime,for theoscillator torestartandstabilizebeforethesystemresumesnormaloperation.
Note that theUSRregister flagsare readonlyandcannotbeclearedorsetby theapplicationprogram,neitherwill theybeclearedwhen theprogramjumps to thecorresponding interruptservicing routine, as is the case for someof theother interrupts.The flagswill be clearedautomaticallywhencertainactionsare takenbytheUART,thedetailsofwhicharegivenintheUARTregistersection.TheoverallUARTinterruptcanbedisabledorenabledby the relatedinterruptenablecontrolbitsintheinterruptcontrolregistersofthemicrocontrollertodecidewhethertheinterruptrequestedbytheUARTmoduleismaskedoutorallowed.
T�ans�itte� E�ptyFlag TXIF
USR Registe�
T�ans�itte� IdleFlag TIDLE
Receive� Ove��unFlag OERR
Receive� DataAvaila�le RXIF
ADDE�
RX PinWake-up
WAKE 01
01
01
RX7 if B�O=0RX8 if B�O=1UCR� Registe�
OR RIE 01
TIIE 01
TEIE 01
UART Inte��upt Request Flag
UARF
UCR� Registe�
UARE
I�TC�Registe�
EMI
I�TC0Registe�
UART Interrupt Scheme
Rev. 1.60 1�7 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Address Detect ModeSettingtheAddressDetectModebit,ADDEN,intheUCR2register,enablesthisspecialmode.IfthisbitisenabledthenanadditionalqualifierwillbeplacedonthegenerationofaReceiverDataAvailableinterrupt,whichisrequestedbytheRXIFflag.IftheADDENbitisenabled,thenwhendataisavailable,aninterruptwillonlybegenerated, if thehighestreceivedbithasahighvalue.NotethattheMFE,UREandEMIinterruptenablebitsmustalsobeenabledforcorrect interruptgeneration.Thishighestaddressbit is the9thbit ifBNO=1or the8thbit ifBNO=0.If thisbitishigh, thenthereceivedwordwillbedefinedasanaddressrather thandata.ADataAvailableinterruptwillbegeneratedeverytimethelastbitof thereceivedwordisset. If theADDENbitisnotenabled, thenaReceiverDataAvailable interruptwillbegeneratedeach time theRXIFflagisset, irrespectiveof thedata lastbitstatus.Theaddressdetectmodeandparityenablearemutuallyexclusivefunctions.Thereforeiftheaddressdetectmodeisenabled,thentoensurecorrectoperation,theparityfunctionshouldbedisabledbyresettingtheparityenablebittozero.
ADDEN Bit 9 if BNO=1,Bit 8 if BNO=0 UART Interrupt Generated
00 √1 √
10 ×1 √
ADDEN Bit Function
UART Module Power Down and Wake-upWhentheMCUisinthePowerDownMode,theUARTwillceasetofunction.WhenthedeviceentersthePowerDownMode,allclocksourcestothemoduleareshutdown.IftheMCUentersthePowerDownModewhileatransmissionisstill inprogress, thenthetransmissionwillbepauseduntiltheUARTclocksourcederivedfromthemicrocontrollerisactivated.Inasimilarway,iftheMCUentersthePowerDownModewhilereceivingdata,thenthereceptionofdatawilllikewisebepaused.WhentheMCUentersthePowerDownMode,notethattheUSR,UCR1,UCR2,transmitandreceiveregisters,aswellastheBRGregisterwillnotbeaffected.ItisrecommendedtomakesurefirstthattheUARTdatatransmissionorreceptionhasbeenfinishedbeforethemicrocontrollerentersthePowerDownmode.
TheUARTfunctioncontainsareceiverRXpinwake-upfunction,which isenabledordisabledbytheWAKEbitintheUCR2register.Ifthisbit,alongwiththeUARTenablebit,UARTEN,thereceiverenablebit,RXENandthereceiverinterruptbit,RIE,areallsetbeforetheMCUentersthePowerDownMode,thenafallingedgeontheRXpinwillwakeuptheMCUfromthePowerDownMode.Note thatas it takescertainsystemclockcyclesafterawake-up,beforenormalmicrocontrolleroperationresumes,anydatareceivedduringthistimeontheRXpinwillbeignored.
ForaUARTwake-upinterrupttooccur,inadditiontothebitsforthewake-upbeingset,theglobalinterruptenablebit,EMI,andtheUARTinterruptenablebit,URE,mustalsobeset.Ifthesetwobitsarenotsetthenonlyawakeupeventwilloccurandnointerruptwillbegenerated.Notealsothatasittakescertainsystemclockcyclesafterawake-upbeforenormalmicrocontrollerresumes,theUARTinterruptwillnotbegenerateduntilafterthistimehaselapsed.
BelowtableillustratestheUARTRXwake-upfunctionsindifferentoperatingmode.
Rev. 1.60 1�8 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
OperationMode
DescriptionRX wake-up function
CPU fSYS fH fSUB
IDLE0 Mode Off Off Off OnWhen the CPU ente�s the IDLE0 �ode� a falling edge on the RX pin will not tu�n on the fSYS clock and not wake up the CPU even if UCR�.�(RIE)=1 and UCR�.3(WAKE)=1.
IDLE1 Mode Off On On On
When the UCR�.�(RIE)=1� UCR�.3(WAKE)=1 and the CPU is ente�ed in IDLE1 �ode:1. If the UART is not t�ansfe� and a falling edge occu��ed on
the RX pin� this will tu�n on fSYS and CPU is still off. If the UART t�ans�ission is on going� CPU will �e woken up in the end of t�ansfe�.
�. If the UART t�ans�ission is on going� the CPU will �e woken up in the end of t�ansfe�.
�ote: If RIE=0� WAKE=1 and the UART t�ans�ission is on going� the CPU will not �e woken up in the end of �eceive.
IDLE1 Mode Off On(fSYS=fH~fH/64) On Off
When the UCR�.�(RIE)=1� UCR�.3(WAKE)=1 and the CPU is ente�ed in IDLE1 �ode:1. If the UART is not t�ansfe� and a falling edge occu��ed on
the RX pin� this will tu�n on fSYS and CPU is still off. If the UART t�ans�ission is on going� CPU will �e woken up in the end of t�ansfe�.
�. If the UART t�ans�ission is on going� the CPU will �e woken up in the end of t�ansfe�.
�ote: If RIE=0� WAKE=1 and the UART t�ans�ission is on going� the CPU will not �e woken up in the end of �eceive.
SLEEP0/1 Mode Off Off Off On/OffWhen the UCR�.�(RIE)=1� UCR�.3(WAKE)=1 and the CPU is ente�ed in SLEEP �ode� a falling edge on the RX pin will tu�n on fSYS and wake-up CPU.
Rev. 1.60 1�9 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModuleoranA/Dconverterrequiresmicrocontrollerattention,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontroller todirectattentiontotheirrespectiveneeds.Thedevicecontainsseveralexternalinterruptandinternalinterruptsfunctions.TheexternalinterruptisgeneratedbytheactionoftheexternalINT0~INT3pins,whiletheinternalinterruptsaregeneratedbyvariousinternalfunctionssuchasTMs,TimeBase,LVD,EEPROM,UARTandtheA/Dconverter.
Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshownintheaccompanyingtable.Thefirst is theINTC0~INTC2registerswhichsetuptheprimaryinterrupts,thesecondistheMFI0~MFI4registerswhichsetuptheMulti-functioninterrupts.FinallythereisanINTEGregistertosetuptheexternalinterrupttriggeredgetype.
Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran“E”forenable/disablebitor“F”forrequestflag.
Function Enable Bit Request Flag NotesGlo�al EMI — —I�Tn Pin I�TnE I�TnF n=0~3A/D Conve�te� ADE ADF —Multi-function MFnE MFnF n=0~4Ti�e Base TBnE TBnF n=0 o� 1LVD LVE LVF —EEPROM DEE DEF —UART UARE UARF —
TMTnPE TnPF n=0~3TnAE TnAF n=0~3
Note:TheEEPROMInterruptisonlyfortheHT67F489.Interrupt Register Bit Naming Conventions
Register Name
Bit
7 6 5 4 3 2 1 0I�TEG I�T3S1 I�T3S0 I�T�S1 I�T�S0 I�T1S1 I�T1S0 I�T0S1 I�T0S0I�TC0 — MF0F I�T1F I�T0F MF0E I�T1E I�T0E EMII�TC1 ADF MF3F MF�F MF1F ADE MF3E MF�E MF1EI�TC� MF4F I�T3F I�T�F UARF MF4E I�T3E I�T�E UAREMFI0 — — T0AF T0PF — — T0AE T0PEMFI1 — — T1AF T1PF — — T1AE T1PEMFI� — — T�AF T�PF — — T�AE T�PEMFI3 — — T3AF T3PF — — T3AE T3PEMFI4 TB1F TB0F DEF LVF TB1E TB0E DEE LVE
Note:TheEEPROMInterruptisonlyfortheHT67F489.Interrupt Register Contents
Rev. 1.60 130 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
INTEG Register
Bit 7 6 5 4 3 2 1 0�a�e I�T3S1 I�T3S0 I�T�S1 I�T�S0 I�T1S1 I�T1S0 I�T0S1 I�T0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~6 INT3S1~INT3S0:InterruptedgecontrolforINT3pin00:Disable01:Risingedge10:Fallingedge11:Bothrisingandfallingedges
Bit5~4 INT2S1~INT2S0:InterruptedgecontrolforINT2pin00:Disable01:Risingedge10:Fallingedge11:Bothrisingandfallingedges
Bit3~2 INT1S1~INT1S0:InterruptedgecontrolforINT1pin00:Disable01:Risingedge10:Fallingedge11:Bothrisingandfallingedges
Bit1~0 INT0S1~INT0S0:InterruptedgecontrolforINT0pin00:Disable01:Risingedge10:Fallingedge11:Bothrisingandfallingedges
Rev. 1.60 131 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
INTC0 Register
Bit 7 6 5 4 3 2 1 0�a�e — MF0F I�T1F I�T0F MF0E I�T1E I�T0E EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0
Bit7 Unimplemented,readas“0”Bit6 MF0F:Multi-functionInterrupt0RequestFlag
0:Norequest1:Interruptrequest
Bit5 INT1F:INT1InterruptRequestFlag0:Norequest1:Interruptrequest
Bit4 INT0F:INT0InterruptRequestFlag0:Norequest1:Interruptrequest
Bit3 MF0E:Multi-function0InterruptControl0:Disable1:Enable
Bit2 INT1E:INT1InterruptControl0:Disable1:Enable
Bit1 INT0E:INT0InterruptControl0:Disable1:Enable
Bit0 EMI:GlobalInterruptControl0:Disable1:Enable
Rev. 1.60 13� �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
INTC1 Register
Bit 7 6 5 4 3 2 1 0�a�e ADF MF3F MF�F MF1F ADE MF3E MF�E MF1ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7 ADF:A/DConverterInterruptRequestFlag0:Norequest1:Interruptrequest
Bit6 MF3F:Multi-functionInterrupt3RequestFlag0:Norequest1:Interruptrequest
Bit5 MF2F:Multi-functionInterrupt2RequestFlag0:Norequest1:Interruptrequest
Bit4 MF1F:Multi-functionInterrupt1RequestFlag0:Norequest1:Interruptrequest
Bit3 ADE:A/DConverterInterruptControl0:Disable1:Enable
Bit2 MF3E:Multi-function3InterruptControl0:Disable1:Enable
Bit1 MF2E:Multi-function2InterruptControl0:Disable1:Enable
Bit0 MF1E:Multi-function1InterruptControl0:Disable1:Enable
Rev. 1.60 133 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
INTC2 Register
Bit 7 6 5 4 3 2 1 0�a�e MF4F I�T3F I�T�F UARF MF4E I�T3E I�T�E UARER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7 MF4F:Multi-functionInterrupt4RequestFlag0:Norequest1:Interruptrequest
Bit6 INT3F:INT3pininterruptrequestflag0:Norequest1:Interruptrequest
Bit5 INT2F:INT2pininterruptrequestflag0:Norequest1:Interruptrequest
Bit4 UARF:UARTinterruptrequestflag0:Norequest1:Interruptrequest
Bit3 MF4E:Multi-function4InterruptControl0:Disable1:Enable
Bit2 INT3E:INT3pininterruptcontrol0:Disable1:Enable
Bit1 INT2E:INT2pininterruptcontrol0:Disable1:Enable
Bit0 UARE:UARTinterruptcontrol0:Disable1:Enable
Rev. 1.60 134 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
MFI0 Register
Bit 7 6 5 4 3 2 1 0�a�e — — T0AF T0PF — — T0AE T0PER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0
Bit7~6 Unimplemented,readas“0”Bit5 T0AF:TM0ComparatorAmatchinterruptrequestflag
0:Norequest1:Interruptrequest
Bit4 T0PF:TM0ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit3~2 Unimplemented,readas“0”Bit1 T0AE:TM0ComparatorAmatchinterruptcontrol
0:Disable1:Enable
Bit0 T0PE:TM0ComparatorPmatchinterruptcontrol0:Disable1:Enable
MFI1 Register
Bit 7 6 5 4 3 2 1 0�a�e — — T1AF T1PF — — T1AE T1PER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0
Bit7~6 Unimplemented,readas“0”Bit5 T1AF:TM1ComparatorAmatchinterruptrequestflag
0:Norequest1:Interruptrequest
Bit4 T1PF:TM1ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit3~2 Unimplemented,readas“0”Bit1 T1AE:TM1ComparatorAmatchinterruptcontrol
0:Disable1:Enable
Bit0 T1PE:TM1ComparatorPmatchinterruptcontrol0:Disable1:Enable
Rev. 1.60 135 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
MFI2 Register
Bit 7 6 5 4 3 2 1 0�a�e — — T�AF T�PF — — T�AE T�PER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0
Bit7~6 Unimplemented,readas“0”Bit5 T2AF:TM2ComparatorAmatchinterruptrequestflag
0:Norequest1:Interruptrequest
Bit4 T2PF:TM2ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit3~2 Unimplemented,readas“0”Bit1 T2AE:TM2ComparatorAmatchinterruptcontrol
0:Disable1:Enable
Bit0 T2PE:TM2ComparatorPmatchinterruptcontrol0:Disable1:Enable
MFI3 Register
Bit 7 6 5 4 3 2 1 0�a�e — — T3AF T3PF — — T3AE T3PER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0
Bit7~6 Unimplemented,readas“0”Bit5 T3AF:TM3ComparatorAmatchinterruptrequestflag
0:Norequest1:Interruptrequest
Bit4 T3PF:TM3ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit3~2 Unimplemented,readas“0”Bit1 T3AE:TM3ComparatorAmatchinterruptcontrol
0:Disable1:Enable
Bit0 T3PE:TM3ComparatorPmatchinterruptcontrol0:Disable1:Enable
Rev. 1.60 136 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
MFI4 Register
Bit 7 6 5 4 3 2 1 0�a�e TB1F TB0F DEF LVF TB1E TB0E DEE LVER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7 TB1F:TimeBase1InterruptRequestFlag0:Norequest1:Interruptrequest
Bit6 TB0F:TimeBase0InterruptRequestFlag0:Norequest1:Interruptrequest
Bit5 DEF:DataEEPROMinterruptrequestflag0:Norequest1:Interruptrequest
Bit4 LVF:LVDinterruptrequestflag0:Norequest1:Interruptrequest
Bit3 TB1E:TimeBase1InterruptControl0:Disable1:Enable
Bit2 TB0E:TimeBase0InterruptControl0:Disable1:Enable
Bit1 DEE:DataEEPROMInterruptControl0:Disable1:Enable
Bit0 LVE:LVDInterruptControl0:Disable1:Enable
Note:TheEEPROMInterruptisonlyfortheHT67F489.
Rev. 1.60 137 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTMComparatorP,ComparatorAmatchorA/Dconversioncompletionetc,therelevantinterruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.If theenablebit issethighthentheprogramwill jumptoitsrelevantvector,iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.
Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea“JMP”whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha“RETI”,whichretrieves theoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.
Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theAccompanyingdiagramswith theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.
Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.
Rev. 1.60 138 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
04H
0CH
10H
1CH
Vector
Low
P�io�ityHighRequest
FlagsEna�le
BitsMaste�Ena�le
RequestFlags
Ena�leBits
EMI auto disa�led in ISR
Inte��upt�a�e
Inte��upt�a�e
EMI
EMI
EMI
EMI
T1AFTM1 A T1AE
T1PFTM1 P T1PE
I�T0FI�T0 Pin I�T0E
MF0FM. Funct. 0 MF0E
MF1FM. Funct. 1 MF1E
ADFA/D ADE
xxF
Legend
Request Flag – no auto �eset in ISR
xxF Request Flag – auto �eset in ISR
xxE Ena�le Bit
T0AFTM0 A
T0PFTM0 P
T0AE
T0PE
�8HEMII�T3FI�T3 Pin I�T3E
18HEMIMF3FM. Funct. 3 MF3E
�0HEMIUARFUART UARE
08HEMII�T1FI�T1 Pin I�T1E
14HEMI
T�AFTM� A T�AE
T�PFTM� P T�PE MF�FM. Funct. � MF�E
T3AFTM3 A T3AE
T3PFTM3 P T3PE
�4HEMII�T�FI�T� Pin I�T�E
�CHEMI
DEFEEPROM DEE
LVFLVD LVE
MF4FM. Funct. 4 MF4E
TB1FTi�e Base 1 TB1E
TB0FTi�e Base 0 TB0E
Inte��upts contained within Multi-Function Inte��upts
HT67F489 only
Interrupt Structure
Rev. 1.60 139 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
External InterruptTheexternal interrupt iscontrolledbysignal transitionsontheINTnpins.Anexternal interruptrequestwill takeplacewhentheexternal interruptrequestflag, INTnF, isset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternal interruptpin.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andrespectiveexternalinterruptenablebit,INTnE,mustfirstbeset.Additionallythecorrect interruptedgetypemustbeselectedusingtheINTEGregister toenable theexternalinterruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinispin-sharedwithI/Opin,itcanonlybeconfiguredasexternalinterruptpiniftheexternalinterruptenablebitinthecorrespondinginterruptregisterhasbeenset.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregister.Whentheinterruptisenabled,thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvectorwill takeplace.Whentheinterruptisserviced,theexternalinterruptrequestflag,INTnF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionsontheexternalinterruptpinwillremainvalidevenifthepinisusedasanexternalinterruptinput.
TheINTEGregisterisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.
Multi-function InterruptWithinthesedevicesthereareuptofourMulti-functioninterrupts.Unliketheotherindependentinterrupts, theseinterruptshavenoindependentsource,butratherareformedfromotherexistinginterruptsources,namely theTMInterrupts,LVDinterrupt,EEPROMinterruptandTimeBaseinterrupt.
AMulti-functioninterruptrequestwill takeplacetheMulti-functioninterruptrequestflag,MFnFisset.TheMulti-functioninterruptflagwillbesetwhenanyofitsincludedfunctionsgenerateaninterruptrequestflag.Toallowtheprogramtobranchto itsrespectiveinterruptvectoraddress,whentheMulti-functioninterruptisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-function interruptoccurs,asubroutinecall to theMulti-functioninterruptvectorwill takeplace.Whentheinterruptisserviced,therelatedMulti-Functionrequestflag,MFnF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.
However, itmustbenotedthat,althoughtheMulti-functionInterruptflagswillbeautomaticallyresetwhentheinterruptisserviced,therequestflagsfromtheoriginalsourceoftheMulti-functioninterrupts,namelytheTMInterrupts,LVDinterrupt,EEPROMinterruptandTimeBaseinterrupt,willnotbeautomaticallyresetandmustbemanuallyresetbytheapplicationprogram.
A/D Converter InterruptTheA/DConverterInterruptiscontrolledbytheterminationofanA/Dconversionprocess.AnA/DConverterInterruptrequestwilltakeplacewhentheA/DConverterInterruptrequestflag,ADF,isset,whichoccurswhentheA/Dconversionprocessfinishes.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andA/DInterruptenablebit,ADE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheA/Dconversionprocesshasended,asubroutinecalltotheA/DConverterInterruptvectorwilltakeplace.Whentheinterruptisserviced,theA/DConverterInterruptflag,ADF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.
Rev. 1.60 140 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
UART InterruptSeveralindividualUARTconditionscangenerateaUARTinterrupt.Whentheseconditionsexist,a lowpulsewillbegeneratedtoget theattentionof themicrocontroller.Theseconditionsareatransmitterdataregisterempty, transmitter idle,receiverdataavailable,receiveroverrun,addressdetectandanRXpinwake-up.Toallowtheprogramtobranchtotherespectiveinterruptvectoraddresses, theglobalinterruptenablebit,EMI,andUARTinterruptenablebit,UARE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanyoftheseconditionsarecreated,asubroutinecall totheUARTInterruptvectorwill takeplace.Whentheinterruptisserviced,theUARTInterruptflag,UARF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.However, theUSRregisterflagswillbeclearedautomaticallywhencertainactionsaretakenbytheUART,thedetailsofwhicharegivenintheUARTsection.
Time Base InterruptThefunctionoftheTimeBaseInterruptsistoprovideregulartimesignalintheformofaninternalinterrupt.Theyarecontrolledbytheoverflowsignalsfromtheirrespectivetimerfunctions.Whenthesehappens their respective interrupt request flags,TB0ForTB1Fwillbeset.Toallowtheprogramtobranchto their respective interruptvectoraddresses, theglobal interruptenablebit,EMIandTimeBaseenablebits,TB0EorTB1E,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecalltotheMulti-functionInterruptvectorwilltakeplace.WhentheTimeBaseInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheTB0ForTB1Fflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.
ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.TheirclocksourcesoriginatefromtheinternalclocksourcefTB.ThisfTB inputclockpasses throughadivider, thedivisionratioofwhich isselectedbyprogrammingtheappropriatebits in theTBCregistertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcethatgeneratesfTB,whichinturncontrolstheTimeBaseinterruptperiod,canoriginatefromseveraldifferentsources,asshownintheSystemOperatingModesection.
Rev. 1.60 141 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
TBC Register
Bit 7 6 5 4 3 2 1 0�a�e TBO� TBCK TB11 TB10 — TB0� TB01 TB00R/W R/W R/W R/W R/W — R/W R/W R/WPOR 0 0 1 1 — 1 1 1
Bit7 TBON:TB0andTB1Control0:Disable1:Enable
Bit6 TBCK:SelectfTBClock0:fTBC1:fSYS/4
Bit5~4 TB11, TB10:SelectTimeBase1Time-outPeriod00:4096/fTB01:8192/fTB10:16384/fTB11:32768/fTB
Bit3 Unimplemented,readas“0”Bit2~0 TB02~TB00:SelectTimeBase0Time-outPeriod
000:256/fTB001:512/fTB010:1024/fTB011:2048/fTB100:4096/fTB101:8192/fTB110:16384/fTB111:32768/fTB
���
���
� � �
� � � �
� � � � � �� � � � � � �� �
� � � � � � � �� � �
� � � � � � � � �
� � � � � � � � � � � � � � � � � � �
� � � � � � � � � � � � � � � � � � �
� � � � �� � � � � � � � � � � � � � �
� � � � � � �
� � � � � � � � �
� � �� � � �
Time Base Interrupt
EEPROM InterruptTheEEPROMinterrupt iscontainedwithintheMulti-functionInterrupt.AnEEPROMInterruptrequestwill takeplacewhen theEEPROMInterrupt request flag,DEF, is set,whichoccurswhenanEEPROMWritecycleends.Toallowtheprogramtobranchto itsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andEEPROMInterruptenablebit,DEE,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanEEPROMWritecycleends,asubroutinecall totherespectiveEEPROMInterruptvectorwill takeplace.When theEEPROMInterrupt isserviced, theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheDEFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.
Rev. 1.60 14� �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LVD InterruptTheLowVoltageDetector Interrupt iscontainedwithin theMulti-function Interrupt.AnLVDInterruptrequestwill takeplacewhentheLVDInterruptrequest flag,LVF, isset,whichoccurswhentheLowVoltageDetectorfunctiondetectsalowpowersupplyvoltage.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,LowVoltageInterruptenablebit,LVE,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalowvoltageconditionoccurs,asubroutinecalltotheMulti-functionInterruptvectorwilltakeplace.WhentheLowVoltageInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheLVFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.
TM Interrupts TheCompactandPeriodicTypeTMshave two interruptseach.Allof theTMinterruptsarecontainedwithintheMulti-functionInterrupts.Foreachof theCompactandPeriodicTypeTMstherearetwointerruptrequestflagsTnPFandTnAFandtwoenablebitsTnPEandTnAE.ATMinterruptrequestwilltakeplacewhenanyoftheTMrequestflagsareset,asituationwhichoccurswhenaTMcomparatorPorAmatchsituationhappens.
Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,respectiveTMInterruptenablebit,andrelevantMulti-functionInterruptenablebit,MFnE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecalltotherelevantMulti-functionInterruptvectorlocationswilltakeplace.WhentheTMinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytherelatedMFnFflagwillbeautomaticallycleared.AstheTMinterruptrequestflagswillnotbeautomaticallycleared,theyhavetobeclearedbytheapplicationprogram.
Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpins,alowpowersupplyvoltageorcomparatorinputchangemaycausetheirrespectiveinterruptflagtobesethighandconsequentlygenerateaninterrupt.Caremust thereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.
Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptservice routine isexecuted,asonly theMulti-function interrupt request flags,MFnF,willbeautomaticallycleared, the individual request flag for the functionneeds tobeclearedby theapplicationprogram.
It isrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.
Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.
AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.
Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Low Voltage Detector – LVDEachdevicehasaLowVoltageDetectorfunction,alsoknownasLVD.Thisenabledthedevicetomonitorthepowersupplyvoltage,VDD,andprovideawarningsignalshoulditfallbelowacertainlevel.Thisfunctionmaybeespeciallyusefulinbatteryapplicationswherethesupplyvoltagewillgraduallyreduceasthebatteryages,asitallowsanearlywarningbatterylowsignaltobegenerated.TheLowVoltageDetectoralsohasthecapabilityofgeneratinganinterruptsignal.
LVD RegisterTheLowVoltageDetectorfunctioniscontrolledusingasingleregisterwiththenameLVDC.Threebits inthisregister,VLVD2~VLVD0,areusedtoselectoneofeightfixedvoltagesbelowwhichalowvoltageconditionwillbedetermined.AlowvoltageconditionisindicatedwhentheLVDObitisset.IftheLVDObitislow,thisindicatesthattheVDDvoltageisabovethepresetlowvoltagevalue.TheLVDENbit isusedtocontrol theoverallon/offfunctionof thelowvoltagedetector.Settingthebithighwillenablethelowvoltagedetector.Clearingthebittozerowillswitchofftheinternallowvoltagedetectorcircuits.Asthelowvoltagedetectorwillconsumeacertainamountofpower,itmaybedesirabletoswitchoffthecircuitwhennotinuse,animportantconsiderationinpowersensitivebatterypoweredapplications.
LVDC Register
Bit 7 6 5 4 3 2 1 0�a�e — — LVDO LVDE� — VLVD� VLVD1 VLVD0R/W — — R R/W — R/W R/W R/WPOR — — 0 0 — 0 0 0
Bit7~6 Unimplemented,readas"0"Bit5 LVDO:LVDOutputFlag
0:NoLowVoltageDetect1:LowVoltageDetect
Bit4 LVDEN:LowVoltageDetectorControl0:Disable1:Enable
Bit3 Unimplemented,readas“0”Bit2~0 VLVD2~VLVD0:SelectLVDVoltage
000:2.0V001:2.2V010:2.4V011:2.7V100:3.0V101:3.3V110:3.6V111:4.0V
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LVD OperationTheLowVoltageDetectorfunctionoperatesbycomparingthepowersupplyvoltage,VDD,withapre-specifiedvoltagelevelstoredintheLVDCregister.Thishasarangeofbetween2.0Vand4.0V.Whenthepowersupplyvoltage,VDD,fallsbelowthispre-determinedvalue,theLVDObitwillbesethighindicatinga lowpowersupplyvoltagecondition.TheLowVoltageDetectorfunctionissuppliedbyareferencevoltagewhichwillbeautomaticallyenabled.WhenthedeviceispowereddownthelowvoltagedetectorwillremainactiveiftheLVDENbitishigh.AfterenablingtheLowVoltageDetector,atimedelaytLVDSshouldbeallowedforthecircuitrytostabilisebeforereadingtheLVDObit.NotealsothatastheVDDvoltagemayriseandfallratherslowly,atthevoltagenearsthatofVLVD,theremaybemultiplebitLVDOtransitions.
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LVD Operation
TheLowVoltageDetectoralsohasitsowninterruptwhichiscontainedwithinoneoftheMulti-functioninterrupts,providinganalternativemeansoflowvoltagedetection,inadditiontopollingtheLVDObit.TheinterruptwillonlybegeneratedafteradelayoftLVDaftertheLVDObithasbeensethighbyalowvoltagecondition.WhenthedeviceispowereddowntheLowVoltageDetectorwillremainactiveiftheLVDENbitishigh.Inthiscase,theLVFinterruptrequestflagwillbeset,causinganinterrupttobegeneratedifVDDfallsbelowthepresetLVDvoltage.Thiswillcausethedevicetowake-upfromtheSLEEPorIDLEMode,howeveriftheLowVoltageDetectorwakeupfunctionisnotrequiredthentheLVFflagshouldbefirstsethighbeforethedeviceenterstheSLEEPorIDLEMode.
WhenLVDfunctionisenabled,itisrecommencedtoclearLVDflagfirst,andthenenablesinterruptfunctiontoavoidmistakeaction.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Configuration OptionsConfigurationoptionsrefertocertainoptionswithintheMCUthatareprogrammedintothedeviceduringtheprogrammingprocess.Duringthedevelopmentprocess,theseoptionsareselectedusingtheHT-IDEsoftwaredevelopment tools.Astheseoptionsareprogrammedintothedeviceusingthehardwareprogrammingtools,once theyareselectedtheycannotbechangedlaterusingtheapplicationprogram.Alloptionsmustbedefinedforpropersystemfunction,thedetailsofwhichareshowninthetable.
No. Options
1 High Speed Syste� Oscillato� SelectionfH – HXT o� HIRC
Application Circuits
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Instruction Set
IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.
Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.
Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe“CLRPCL”or“MOVPCL,A”.Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.
Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.
Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.
Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction“RET”inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.
Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe“SET[m].i”or“CLR[m].i”instructionsrespectively.Thefeatureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.
Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemory tobesetasa tablewheredatacanbedirectlystored.Asetofeasy touse instructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.
Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe“HALT”instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Instruction Set SummaryTheinstructionsrelated to thedatamemoryaccess in thefollowingtablecanbeusedwhenthedesireddatamemoryislocatedinDataMemorysector0.
Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress
Mnemonic Description Cycles Flag AffectedArithmeticADD A�[�] Add Data Me�o�y to ACC 1 Z� C� AC� OV� SCADDM A�[�] Add ACC to Data Me�o�y 1�ote Z� C� AC� OV� SCADD A�x Add i��ediate data to ACC 1 Z� C� AC� OV� SCADC A�[�] Add Data Me�o�y to ACC with Ca��y 1 Z� C� AC� OV� SCADCM A�[�] Add ACC to Data �e�o�y with Ca��y 1�ote Z� C� AC� OV� SCSUB A�x Su�t�act i��ediate data f�o� the ACC 1 Z� C� AC� OV� SC� CZSUB A�[�] Su�t�act Data Me�o�y f�o� ACC 1 Z� C� AC� OV� SC� CZSUBM A�[�] Su�t�act Data Me�o�y f�o� ACC with �esult in Data Me�o�y 1�ote Z� C� AC� OV� SC� CZSBC A�x Su�t�act i��ediate data f�o� ACC with Ca��y 1 Z� C� AC� OV� SC� CZSBC A�[�] Su�t�act Data Me�o�y f�o� ACC with Ca��y 1 Z� C� AC� OV� SC� CZSBCM A�[�] Su�t�act Data Me�o�y f�o� ACC with Ca��y� �esult in Data Me�o�y 1�ote Z� C� AC� OV� SC� CZDAA [�] Deci�al adjust ACC fo� Addition with �esult in Data Me�o�y 1�ote CLogic OperationA�D A�[�] Logical A�D Data Me�o�y to ACC 1 ZOR A�[�] Logical OR Data Me�o�y to ACC 1 ZXOR A�[�] Logical XOR Data Me�o�y to ACC 1 ZA�DM A�[�] Logical A�D ACC to Data Me�o�y 1�ote ZORM A�[�] Logical OR ACC to Data Me�o�y 1�ote ZXORM A�[�] Logical XOR ACC to Data Me�o�y 1�ote ZA�D A�x Logical A�D i��ediate Data to ACC 1 ZOR A�x Logical OR i��ediate Data to ACC 1 ZXOR A�x Logical XOR i��ediate Data to ACC 1 ZCPL [�] Co�ple�ent Data Me�o�y 1�ote ZCPLA [�] Co�ple�ent Data Me�o�y with �esult in ACC 1 ZIncrement & DecrementI�CA [�] Inc�e�ent Data Me�o�y with �esult in ACC 1 ZI�C [�] Inc�e�ent Data Me�o�y 1�ote ZDECA [�] Dec�e�ent Data Me�o�y with �esult in ACC 1 ZDEC [�] Dec�e�ent Data Me�o�y 1�ote ZRotateRRA [�] Rotate Data Me�o�y �ight with �esult in ACC 1 �oneRR [�] Rotate Data Me�o�y �ight 1�ote �oneRRCA [�] Rotate Data Me�o�y �ight th�ough Ca��y with �esult in ACC 1 CRRC [�] Rotate Data Me�o�y �ight th�ough Ca��y 1�ote CRLA [�] Rotate Data Me�o�y left with �esult in ACC 1 �oneRL [�] Rotate Data Me�o�y left 1�ote �oneRLCA [�] Rotate Data Me�o�y left th�ough Ca��y with �esult in ACC 1 CRLC [�] Rotate Data Me�o�y left th�ough Ca��y 1�ote C
Rev. 1.60 150 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Mnemonic Description Cycles Flag AffectedData MoveMOV A�[�] Move Data Me�o�y to ACC 1 �oneMOV [�]�A Move ACC to Data Me�o�y 1�ote �oneMOV A�x Move i��ediate data to ACC 1 �oneBit OperationCLR [�].i Clea� �it of Data Me�o�y 1�ote �oneSET [�].i Set �it of Data Me�o�y 1�ote �oneBranch OperationJMP add� Ju�p unconditionally � �oneSZ [�] Skip if Data Me�o�y is ze�o 1�ote �oneSZA [�] Skip if Data Me�o�y is ze�o with data �ove�ent to ACC 1�ote �oneSZ [�].i Skip if �it i of Data Me�o�y is ze�o 1�ote �oneS�Z [�] Skip if Data Me�o�y is not ze�o 1�ote �oneS�Z [�].i Skip if �it i of Data Me�o�y is not ze�o 1�ote �oneSIZ [�] Skip if inc�e�ent Data Me�o�y is ze�o 1�ote �oneSDZ [�] Skip if dec�e�ent Data Me�o�y is ze�o 1�ote �oneSIZA [�] Skip if inc�e�ent Data Me�o�y is ze�o with �esult in ACC 1�ote �oneSDZA [�] Skip if dec�e�ent Data Me�o�y is ze�o with �esult in ACC 1�ote �oneCALL add� Su��outine call � �oneRET Retu�n f�o� su��outine � �oneRET A�x Retu�n f�o� su��outine and load i��ediate data to ACC � �oneRETI Retu�n f�o� inte��upt � �oneTable Read OperationTABRD [�] Read table (specific page) to TBLH and Data Memory ��ote �oneTABRDL [�] Read ta�le (last page) to TBLH and Data Me�o�y ��ote �oneITABRD [�] Increment table pointer TBLP first and Read table to TBLH and Data Memory ��ote �one
ITABRDL [�] Increment table pointer TBLP first and Read table (last page) to TBLH and Data Me�o�y ��ote �one
Miscellaneous�OP �o ope�ation 1 �oneCLR [�] Clea� Data Me�o�y 1�ote �oneSET [�] Set Data Me�o�y 1�ote �oneCLR WDT Clea� Watchdog Ti�e� 1 TO� PDFSWAP [�] Swap ni��les of Data Me�o�y 1�ote �oneSWAPA [�] Swap ni��les of Data Me�o�y with �esult in ACC 1 �oneHALT Ente� powe� down �ode 1 TO� PDF
Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthenuptothreecyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.
2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.Forthe“CLRWDT”instructiontheTOandPDFflagsmaybeaffectedbytheexecutionstatus.TheTOandPDFflagsareclearedafter the“CLRWDT”instructionsisexecuted.OtherwisetheTOandPDFflagsremainunchanged.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Extended Instruction SetTheextendedinstructionsareusedtosupport thefullrangeaddressaccessfor thedatamemory.When theaccesseddatamemory is located inanydatamemorysectionsexcept sector0, theextendedinstructioncanbeusedtoaccessthedatamemoryinsteadofusingtheindirectaddressingaccesstoimprovetheCPUfirmwareperformance.
Mnemonic Description Cycles Flag AffectedArithmeticLADD A�[�] Add Data Me�o�y to ACC � Z� C� AC� OV� SCLADDM A�[�] Add ACC to Data Me�o�y ��ote Z� C� AC� OV� SCLADC A�[�] Add Data Me�o�y to ACC with Ca��y � Z� C� AC� OV� SCLADCM A�[�] Add ACC to Data �e�o�y with Ca��y ��ote Z� C� AC� OV� SCLSUB A�[�] Su�t�act Data Me�o�y f�o� ACC � Z� C� AC� OV� SC� CZLSUBM A�[�] Su�t�act Data Me�o�y f�o� ACC with �esult in Data Me�o�y ��ote Z� C� AC� OV� SC� CZLSBC A�[�] Su�t�act Data Me�o�y f�o� ACC with Ca��y � Z� C� AC� OV� SC� CZLSBCM A�[�] Su�t�act Data Me�o�y f�o� ACC with Ca��y� �esult in Data Me�o�y ��ote Z� C� AC� OV� SC� CZLDAA [�] Deci�al adjust ACC fo� Addition with �esult in Data Me�o�y ��ote CLogic OperationLA�D A�[�] Logical A�D Data Me�o�y to ACC � ZLOR A�[�] Logical OR Data Me�o�y to ACC � ZLXOR A�[�] Logical XOR Data Me�o�y to ACC � ZLA�DM A�[�] Logical A�D ACC to Data Me�o�y ��ote ZLORM A�[�] Logical OR ACC to Data Me�o�y ��ote ZLXORM A�[�] Logical XOR ACC to Data Me�o�y ��ote ZLCPL [�] Co�ple�ent Data Me�o�y ��ote ZLCPLA [�] Co�ple�ent Data Me�o�y with �esult in ACC � ZIncrement & DecrementLI�CA [�] Inc�e�ent Data Me�o�y with �esult in ACC � ZLI�C [�] Inc�e�ent Data Me�o�y ��ote ZLDECA [�] Dec�e�ent Data Me�o�y with �esult in ACC � ZLDEC [�] Dec�e�ent Data Me�o�y ��ote ZRotateLRRA [�] Rotate Data Me�o�y �ight with �esult in ACC � �oneLRR [�] Rotate Data Me�o�y �ight ��ote �oneLRRCA [�] Rotate Data Me�o�y �ight th�ough Ca��y with �esult in ACC � CLRRC [�] Rotate Data Me�o�y �ight th�ough Ca��y ��ote CLRLA [�] Rotate Data Me�o�y left with �esult in ACC � �oneLRL [�] Rotate Data Me�o�y left ��ote �oneLRLCA [�] Rotate Data Me�o�y left th�ough Ca��y with �esult in ACC � CLRLC [�] Rotate Data Me�o�y left th�ough Ca��y ��ote CData MoveLMOV A�[�] Move Data Me�o�y to ACC � �oneLMOV [�]�A Move ACC to Data Me�o�y ��ote �oneBit OperationLCLR [�].i Clea� �it of Data Me�o�y ��ote �oneLSET [�].i Set �it of Data Me�o�y ��ote �one
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Mnemonic Description Cycles Flag AffectedBranchLSZ [�] Skip if Data Me�o�y is ze�o ��ote �oneLSZA [�] Skip if Data Me�o�y is ze�o with data �ove�ent to ACC ��ote �oneLS�Z [�] Skip if Data Me�o�y is not ze�o ��ote �oneLSZ [�].i Skip if �it i of Data Me�o�y is ze�o ��ote �oneLS�Z [�].i Skip if �it i of Data Me�o�y is not ze�o ��ote �oneLSIZ [�] Skip if inc�e�ent Data Me�o�y is ze�o ��ote �oneLSDZ [�] Skip if dec�e�ent Data Me�o�y is ze�o ��ote �oneLSIZA [�] Skip if inc�e�ent Data Me�o�y is ze�o with �esult in ACC ��ote �oneLSDZA [�] Skip if dec�e�ent Data Me�o�y is ze�o with �esult in ACC ��ote �oneTable ReadLTABRD [�] Read ta�le to TBLH and Data Me�o�y 3�ote �oneLTABRDL [�] Read ta�le (last page) to TBLH and Data Me�o�y 3�ote �oneLITABRD [�] Increment table pointer TBLP first and Read table to TBLH and Data Memory 3�ote �one
LITABRDL [�] Increment table pointer TBLP first and Read table (last page) to TBLH and Data Me�o�y 3�ote �one
MiscellaneousLCLR [�] Clea� Data Me�o�y ��ote �oneLSET [�] Set Data Me�o�y ��ote �oneLSWAP [�] Swap ni��les of Data Me�o�y ��ote �oneLSWAPA [�] Swap ni��les of Data Me�o�y with �esult in ACC � �one
Note:1.Fortheseextendedskipinstructions,iftheresultofthecomparisoninvolvesaskipthenuptofourcyclesarerequired,ifnoskiptakesplacetwocyclesisrequired.
2.AnyextendedinstructionwhichchangesthecontentsofthePCLregisterwillalsorequirethreecyclesforexecution.
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Instruction Definition
ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC
ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC
ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC
ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C,SC
ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC
AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z
AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z
ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None
CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None
CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None
CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF
CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z
CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z
DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z
DECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z
HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF
INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z
INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z
JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None
MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None
MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None
MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None
OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z
OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z
ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z
RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None
RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None
RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None
RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None
RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C
RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C
RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None
RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryisrotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None
RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C
SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ
SBC A, x SubtractimmediatedatafromACCwithCarryDescription Theimmediatedataandthecomplementofthecarryflagaresubtractedfromthe Accumulator.TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionis negative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflag willbesetto1.Operation ACC←ACC-[m]-CAffectedflag(s) OV,Z,AC,C,SC,CZ
SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ
SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None
SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None
SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None
SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None
SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None
SNZ [m].i SkipifDataMemoryisnot0Description IfthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisrequiresthe insertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None
SNZ [m] SkipifDataMemoryisnot0Description IfthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisrequiresthe insertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]≠0Affectedflag(s) None
SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ
SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C,SC,CZ
SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None
SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None
SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None
SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None
SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBLPandTBHP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
ITABRD [m] IncrementtablepointerlowbytefirstandreadtabletoTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthentheprogramcodeaddressedbythe tablepointer(TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbyte movedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
ITABRDL [m] Incrementtablepointerlowbytefirstandreadtable(lastpage)toTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthenthelowbyteoftheprogramcode (lastpage)addressedbythetablepointer(TBLP)ismovedtothespecifiedDataMemoryand thehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z
XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z
XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Extended Instruction DefinitionTheextendedinstructionsareusedtodirectlyaccessthedatastoredinanydatamemorysections.
LADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC
LADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC
LADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC
LADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC
LAND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z
LANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z
LCLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None
LCLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LCPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z
LCPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z
LDAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C
LDEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z
LDECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z
LINC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z
LINCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LMOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None
LMOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None
LOR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z
LORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z
LRL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None
LRLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None
LRLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C
LRLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LRR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None
LRRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryisrotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None
LRRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C
LRRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C
LSBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ
LSBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LSDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None
LSDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None
LSET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None
LSET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None
LSIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None
LSIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None
LSNZ [m].i SkipifDataMemoryisnot0Description IfthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisrequiresthe insertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LSNZ [m] SkipifDataMemoryisnot0Description IfthecontentofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.As thisrequirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisa twocycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]≠0Affectedflag(s) None
LSUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ
LSUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ
LSWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None
LSWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None
LSZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None
LSZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
LSZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None
LTABRD [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
LTABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
LITABRD [m] IncrementtablepointerlowbytefirstandreadtabletoTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthentheprogramcodeaddressedbythe tablepointer(TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbyte movedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)
Affectedflag(s) None
LITABRDL [m] Incrementtablepointerlowbytefirstandreadtable(lastpage)toTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthenthelowbyteoftheprogramcode (lastpage)addressedbythetablepointer(TBLP)ismovedtothespecifiedDataMemoryand thehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
LXOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z
LXORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z
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HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
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Rev. 1.60 170 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions
SymbolDimensions in inch
Min. Nom. Max.A — 0.47� BSC —B — 0.394 BSC —C — 0.47� BSC —D — 0.394 BSC —E — 0.03� BSC —F 0.01� 0.015 0.018G 0.053 0.055 0.057H — — 0.063I 0.00� — 0.006J 0.018 0.0�4 0.030K 0.004 — 0.008α 0° — 7°
SymbolDimensions in mm
Min. Nom. Max.A — 1�.00 BSC —B — 10.00 BSC —C — 1�.00 BSC —D — 10.00 BSC —E — 0.80 BSC —F 0.30 0.37 0.45G 1.35 1.40 1.45H — — 1.60I 0.05 — 0.15J 0.45 0.60 0.75K 0.09 — 0.�0α 0° — 7°
Rev. 1.60 171 �ove��e� ��� �016
HT67F488/HT67F489TinyPowerTM A/D Flash MCU with LCD & EEPROM
Copy�ight© �016 �y HOLTEK SEMICO�DUCTOR I�C.
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