Transcript of TimingAnalysis Presentation v1 1
Slide 1* - page *
Scope
Why Timing Analysis Needed?
Requirement specification of any digital system consists of
Functional Spec and Timing Spec.
Functional verification and LEC takes care of verifying the
implementation of the functional Spec.
GLS and STA takes care of verifying the implementation of Timing
Specifications.
GDS-II
RTL
What is Timing Analysis
Any digital circuit comprises of sequential elements such as DFF,
Memories, PLL etc.
Each element has its own operating timing limits
To validate that each component meets its own operating
restriction.
Each component has its own limit which are bound by the variations
in the operating environment.
* - page *
Process variation (P)
Supply voltage (V)
Operating Temperature (T)
Because of these parameters governing the behavior of the
components, we have three corners
Fast corner (Min)
Slow corner (Max)
Typical corner
Performance of a circuit depends on the delays of the path
To guarantee timing spec be met under any parameter settings, delay
is measured at the ‘corners’ of the parameter space.
Measurements are provided in the cell libraries.
Corners are expected to bound the performance.
* - page *
Fast process, Highest voltage and Lowest temperature
Checks for the Hold time
Worst Case/Slow Corner/Max Corner:
Checks for Setup Time
Checks for both Hold and Setup Time.
Provides an approximate estimate of the frequency that can be
met
* - page *
Timing Analysis at PVT corners
Timing analysis should be performed at PVT corners to determine the
timing margins
Take the timing parameters at each extreme PVT corner to calculate
the timing margins
All active devices in the circuit will specify Min, Typ, and Max
values for delays.
We use Min and Max values to find out the worst case minimum delays
and worst case maximum delays
Consider separate worst case conditions for data and clock
* - page *
When C is high, Q just follows the input.
(It is called a transparent latch)
When C is low, it just retains its state.
* - page *
Four different delay parameters are shown.
Signals propagate from C or D input to Q output.
At transitions 1 and 4, latch is initially closed so D input is
opposite of Q output.
When C goes to 1, latch opens up and Q output changes after
delay
tpLH(CQ) or tpHL(CQ) .
At transitions 2 and 3, the C input is already 1 and the latch is
open so Q transparently follows the transition on D with delay
tpLH(DQ) or tpHL(DQ).
* - page *
Useful timing parameters for a D latch (Cont’d)
D Input must not change in the (shaded) window of time around the
falling edge of C.
Window begins at time tsetup before the falling (latching) edge of
C which is the setup time.
Window ends at time thold afterward which is the hold time.
If D changes at any time during the setup- and hold- time window,
the output of the latch is unpredictable and may become
metastable.
* - page *
Metastability
Metastability is the state that exist between either “valid”
digital logic state.
Digital circuits have two stable states - but all have a third
metastable state halfway between 0 and 1.
When the setup and hold times of a latch/flip-flop are not met, it
could be put into the metastable state.
Noise will be amplified and push the latch/flip-flop one way or
other.
* - page *
Edge triggered D Flip-Flop
Positive edge triggered D F/F combines a pair of D latches and CLK
signal.
Samples D input and changes its Q and QN outputs only at the rising
edge of a CLK signal.
* - page *
Timing Behavior of Positive-edge triggered D Flip-Flop
It has a setup- and hold-time window during which the D input must
not change.
This window occurs around the triggering edge of CLK.
If setup and hold times are not met, the flip-flop output goes to
metastable state.
If the Flip Flop goes into the metastable state, it will return to
a stable state on its own only after a probabilistic delay.
It can also be forced into a stable state by applying another
triggering clock edge with a D input that meets the setup- and
hold-time requirements.
* - page *
Dynamic Timing Analysis
Dynamic Timing Analysis
Determines the full behavior of the circuit for a given set of
input stimulus vectors.
Reuse of Functional Verification.
Needs to be exhaustive to cover each and every path.
Limitation of Dynamic Timing Analysis
Basic problem is controllability for complex circuits.
Consumes more run time
Dependent on stimulus vectors
An example circuit
In this example circuit, the path taken or verified depends on the
stimulus applied. If stimulus is not exhaustive, timing check is
not done for some of the paths. Hence Dynamic Timing analysis is
not exhaustive and complete.
* - page *
Static Timing Analysis
Static Timing Analysis
Method to determine if a design meets timing constraints w/o having
to simulate the design with vectors.
STA consists of three major steps:
Break the design into Fan-in Cone for each destination flop .
Delay of each Fan-in cone is calculated using formal, mathematical
techniques instead of vectors.
All path delays are checked against timing constraints
Does not use dynamic logic simulation.
100 % exhaustive for sequential input to sequential output.
* - page *
An STA tool
Computes its performance bounds
Outputs a pass or fail
Cone Based Analysis
Exhaustive Timing coverage
Vectors not required
Assertions and reports are concise and easy to interpret
Disadvantages:
Pessimistic (too conservative).
If you are doing worst case analysis then path delay considered is
worst for all the elements within the path where-as in actual
scenario it might not be so worse.
It might happen that the PVT may not correspond to the real working
environment but still we need to close timing in all corners.
Difficult to get correct timing models/parameters for Analog
components to perform STA. Not a limitation from STA tool point of
view.
100 % path coverage is possible because no design specific pattern
is required
Facilitates less designer involvement
Constraints (sdc/tcl) : The design related data
Net Delays
Parasitics (SPEF) : These are the parasitics of the design
extracted from physical design tools.
OR
SDF : Standard Delay Format file containing back-annotated
delays.
Models (lib/db): The delay model of every cell in the library
Outputs
Reports : The timing paths report which can be used for
analyzing.
* - page *
Introduction
Basic
Advance
* - page *
Gate delay
Transistors within a gate, take a finite amount of time to switch.
This means that a change on the input of a gate takes a finite
amount of time to cause a change on the output.
Net delay
The delay between the time a signal is first applied to the net and
the time it reaches other devices connected to that net.
[Source : Timing Analysis Basics presentation from Cadence]
Stage Delay
Gate delay
Delays encountered in digital circuitry are composed of two
principle components: gate delay and net (interconnect)
delay.
Historically gate delay has been the major limiting factor but with
device sizes reaching sub-micron dimensions, internal interconnect
delays and component interconnect delays dominate the gate
delays.
Depending on the process technology, different physical elements
have different levels of contribution. Major change in recent years
is the contribution of RC to circuit delay. RC is not a major
contributing factor above 0. micron process technology. Below 0.5,
RC becomes the dominant factor in determining delays.
Propagation delay: This is the time required for a signal to
propagate through a gate or net. For gates, this is the time it
takes for a event at the gate input to affect the gate output. For
nets, it is the delay between the time a signal is first applied to
the net and the time it reaches other devices connected to that
net.
Each stage delay represents the time required to propagate a signal
from the input of one gate to the input of the next.
* - page *
Gate Delay
Delay through a cell is often determined by the cell’s intrinsic
delay, load that it is driving, and input transition (slew)
Transition is the time it takes for the pin to change state
[Source : Timing Analysis Basics presentation from Cadence]
A
Slew
Intrinsic delay is defined as the delay between an input, and
output pin pair of a cell, when a near-zero slew is applied to the
input pin, and the output pin does not see any load ( no-load
condition ).
Propagation delay: This is the time required for a signal to
propagate through a gate or net. For gates, this is the time it
takes for a event at the gate input to affect the gate output. For
nets, it is the delay between the time a signal is first applied to
the net and the time it reaches other devices connected to that
net.
Delay is the time difference between the input signal crossing a
threshold point and the output signal crossing a threshold
point.
Propagation delay 1/voltage supply
Net Delay
Interconnect causes the timing arc to be from pin to pin
These net delays are computed using wireload model estimation, or
are computed using back-annotated delay information if
available
[Source : Timing Analysis Basics presentation from Cadence]
Y
A
Y
A
v -> v
Propagation delay: This is the time required for a signal to
propagate through a gate or net. For gates, this is the time it
takes for a event at the gate input to affect the gate output. For
nets, it is the delay between the time a signal is first applied to
the net and the time it reaches other devices connected to that
net.
prior to Layout of a chip, cell delay are taken from technology
library (known as .lib) whereas net parasitic and delays can not be
calculated accurately .So timing tool will assume R and C
based on Wire Load Model (WLM) .
Wire Load Model is a set of tables:
netfanout v/s load
netfanout v/s resistance
netfaout v/s area.
These WLM are simple table look up models which
calculates load (capacitance), resistance, area, based on fanout
.i.e., for a value of fanout you will have statistical values for
resistance and load.
Netdelay is a function of net capacitance. RC delay is the net
delay; Every routing net has resistance and capacitance.
* - page *
What is a Timing path?
A timing path is a point-to-point path in a design which can
propagate data from from one flip-flop to another
Each path has a startpoint and an endpoint
Startpoints (Input ports, Clock pins of flip-flops)
Endpoints ( Output ports, Data input pins of flip-flops)
D Q
Each path has a startpoint and an endpoint.
The startpoint is a place in the design where data is launched by a
clock edge. The data is propagated through combinational logic in
the path and then captured at the endpoint by another clock
edge.
The startpoint of a path is a clock pin of a sequential element, or
possibly an input port of the design (because the input data can be
launched from some external source).
The endpoint of a path is a data input pin of a sequential element,
or possibly an output port of the design (because the output data
can be captured by some external sink).
* - page *
Setup & Hold Times
Setup Time: the amount of time the synchronous input (D) must be
stable before the active edge of clock
Hold Time: the amount of time the synchronous input (D) must be
stable after the active edge of clock.
Together, the setup time and hold time form a Data Required Window,
the time around a clock edge in which data must be stable.
[Source : Altera’s Timing Analysis Introduction presentation]
D
Q
CLR
PRE
CLK
DATA
CLK
Th
Valid
DATA
Tsu
Setup and hold checks are the most common types of timing checks
used in timing verification
Synchronous inputs (e.g. D) have Setup, Hold time specification
with respect to the CLOCK input
These checks specify that the data input must remain stable for a
specified interval before and after the clock input changes
* - page *
The data valid time available after meeting the setup
requirement
* - page *
The data valid time available after meeting the hold
requirement
* - page *
Setup Time Requirement
Assumption in the above formulae
Interconnect delays & Clock Skews ignored.
Effect of Interconnect delay & clock skew can be analyzed in a
similar fashion as an exercise.
While calculating the setup margins, minimum clock path delays and
maximum data path delays should be considered.
Worst case is the one where clock reaches the receiver at the
earliest and data reaches with maximum delay
For calculating hold margin, maximum clock path delays and minimum
data path delays should be considered.
Worst case is the one where clock reaches the receiver at the
latest and data reaches at the earliest
* - page *
For a sequential circuit, the following timing parameters are given
-
tcomb = 1 ns, min and 8 ns, max
tffpd = 2 ns, min and 10 ns, max
tsetup = 2 ns, min & max
thold = 1 ns, min & max
Calculate Setup Margin at 25 Mhz clk frequency, Maximum frequency
and the hold margin?
* - page *
Arrival time:
Time elapsed for a signal to arrive at a certain point.
To calculate the arrival time, delay calculation of all the
component of the path will be required.
Required time:
Latest time at which a signal can arrive without making the clock
cycle longer than desired.
Slack:
It is the difference between the required time and the arrival
time.
This is the amount of time by which a violation is avoided
E.g.: for a setup constraint, if a signal must reach a cell input
at no later than 8 ns and is determined to arrive at 5 ns, the
slack is 3 ns.
A slack of 0 means that the constraint is just barely
satisfied.
A negative slack indicates a timing violation.
* - page *
Hold violation
Setup Violation
Hold violation is caused when the clock travels slower than the
path from one register to another – allowing data to penetrate two
registers in the same clock tick, or might destroy the integrity of
the latched data.
Setup Violation is caused if the data signal gets delayed from the
source flip-flop, so that the data signal has that much less time
to reach the destination flip-flop before the next clock
tick.
Which is more dangerous – setup violation or hold violation?
Hold violation is more serious than a setup violation because it
cannot be fixed by increasing the clock period.
* - page *
Data Arrival Time
The time for data to arrive at destination register’s D input
Data Arrival Time = launch edge + Tclk1 + Tco +Tdata
[Source : Altera’s Timing Analysis Introduction presentation]
TCO
PRE
Clock Arrival Time
The time for clock to arrive at destination register’s clock
input
Clock Arrival Time = latch edge + Tclk2
[Source : Altera’s Timing Analysis Introduction presentation]
PRE
Data Required Time - Setup
The minimum time required for the data to get latched into the
destination register
Data Required Time = Clock Arrival Time – Tsu
[Source : Altera’s Timing Analysis Introduction presentation]
PRE
Relative to REG2
Data Required Time - Hold
The minimum time required for the data to get latched into the
destination register
Data Required Time = Clock Arrival Time + Th
[Source : Altera’s Timing Analysis Introduction presentation]
PRE
Setup Slack
The margin by which the setup timing requirement is met. It ensures
launched data arrives in time to meet the latching
requirement.
[Source : Altera’s Timing Analysis Introduction presentation]
TCO
PRE
Positive slack
CALCULATION:
Arrival time (max) = clock delay FF1 (max) +clock-to-Q delay FF1
(max) + comb. Delay( max)
Required time = clock adjust + clock delay FF2 (min) - set up time
FF2
Slack = Required time - Arrival time (since we want data to arrive
before it is required)
clock adjust = clock period (since setup is analyzed at next
edge)
A setup constraint specifies how much time is necessary for data to
be available at the input of a sequential device before the clock
edge that captures the data in the device. This constraint enforces
a maximum delay on the data path relative to the clock path.
* - page *
Hold Slack
The margin by which the hold timing requirement is met. It ensures
latch data is not corrupted by data from another launch edge. It
also prevents “double-clocking”.
[Source : Altera’s Timing Analysis Introduction presentation]
TCO
PRE
Edge
“Double-clocking” is when data is data arrival time is so low when
compared to the clock arrival time that it is clocked through two
subsequent register stages during one clock cycle
* - page *
Positive slack
CALCULATION:
Arrival time = clock delay FF1 (min) +clock-to-Q delay FF1 (min) +
comb. Delay( min)
Required time = clock adjust + clock delay FF2 (max) + hold time
FF2
Slack = Arrival time - Required time (since we want data to arrive
after it is required)
clock adjust = 0 (since hold is analyzed at same edge)
A hold constraint specifies how much time is necessary for data to
be stable at the input of a sequential device after the clock edge
that captures the data in the device. This constraint enforces a
minimum delay on the data path relative to the clock path.
* - page *
Recovery & Removal
Recovery time is the minimum time that an asynchronous control must
be stable before the clock active-edge transition, when async
signal is asserted.
Removal time is the minimum length of time that an asynchronous
control must be stable after the clock active-edge transition, when
async signal is deasserted.
D
Q
CLR
SET
CLK
ASYNC
Asynch resets are synchronized before giving to CLRZ (reset) pin of
flip-flops
* - page *
I/O Analysis
Analyzing I/O performance in a synchronous design uses the same
slack equations
Must include external device & PCB timing parameters
[Source : Altera’s Timing Analysis Introduction presentation]
Tdata
PRE
How many timing paths?
Path 1 starts at an input port and ends at the data input of a
sequential element.
Path 2 starts at the clock pin of a sequential element and ends at
the data input of a sequential element.
Path 3 starts at the clock pin of a sequential element and ends at
an output port.
Path 4 starts at an input port and ends at an output port.
Path 1
Path 2
Path 3
Path 4
A combinational logic cloud might contain multiple paths. Tool
(PrimeTime) uses the longest path to calculate a maximum delay or
the shortest path to calculate a minimum delay.
A combinational logic cloud might contain multiple paths. Tool
(PrimeTime) uses the longest path to calculate a maximum delay or
the shortest path to calculate a minimum delay.
* - page *
Register to Register
Register to Output port
[Source : Timing Analysis Basics presentation from Cadence]
FF2
FF1
IdlClk
OUT_1
IN_2
IN_1
OUT_2
[Source : Timing Analysis Basics presentation from Cadence]
D Q
[Source : Timing Analysis Basics presentation from Cadence]
D Q
External_delay = comb delay + setup
[Source : Timing Analysis Basics presentation from Cadence]
D Q
Understanding Timing Paths: Input Port to Output Port
Input delay and output delay are set with respect to a clock
Default single-cycle
Setup requirement:
Hold requirement:
Combinational paths have no clocks defined for the module
Setup requirement:
Hold requirement:
[Source : Timing Analysis Basics presentation from Cadence]
* - page *
More Reports :
****************************************
****************************************
Endpoint:
U_vpe/U0vpu/U1thra/U7vpu_fpu/Ux_vpu_fmac_mc/RES_W_reg[22]
Path Group: vpe_clk
Path Type: min
-----------------------------------------------------------------------------
U_vpe/U0vpu/U1thra/U7vpu_fpu/Ux_vpu_fmac_mc/NORM_X3_reg[19]/CK
(SDFFQX4AD)
0.032 0.000 0.756 r
U_vpe/U0vpu/U1thra/U7vpu_fpu/Ux_vpu_fmac_mc/NORM_X3_reg[19]/Q
(SDFFQX4AD)
0.074 0.083 & 0.840 f
U_vpe/U0vpu/U1thra/U7vpu_fpu/Ux_vpu_fmac_mc/C20579/I6853_C1_1__n_4
(net)
4 0.073
U_vpe/U0vpu/U1thra/U7vpu_fpu/Ux_vpu_fmac_mc/C20579/I6853_C1_1__n_10
(net)
14 0.127
U_vpe/U0vpu/U1thra/U7vpu_fpu/Ux_vpu_fmac_mc/C20579/I6853_C1_1__n_22
(net)
8 0.046
U_vpe/U0vpu/U1thra/U7vpu_fpu/Ux_vpu_fmac_mc/C20579/I6853_C1_1__n_21
(net)
1 0.018
U_vpe/U0vpu/U1thra/U7vpu_fpu/Ux_vpu_fmac_mc/C20579/I7115_C4_8_C4/Y
(CLKMX2X12AD)
U_vpe/U0vpu/U1thra/U7vpu_fpu/Ux_vpu_fmac_mc/N4473_6 (net)
1 0.007
U_vpe/U0vpu/U1thra/U7vpu_fpu/Ux_vpu_fmac_mc/N4473_5 (net)
1 0.036
U_vpe/U0vpu/U1thra/U7vpu_fpu/Ux_vpu_fmac_mc/C20579/I7123_C4_40_C3/Y
(AOI22X4AD)
U_vpe/U0vpu/U1thra/U7vpu_fpu/Ux_vpu_fmac_mc/N5295_7 (net)
1 0.081
U_vpe/U0vpu/U1thra/U7vpu_fpu/Ux_vpu_fmac_mc/N5295_8 (net)
1 0.071
clock reconvergence pessimism -0.124 1.263
inter-clock uncertainty 0.100 1.363
U_vpe/U0vpu/U1thra/U7vpu_fpu/Ux_vpu_fmac_mc/RES_W_reg[22]/CK
(SDFFQX2AD)
data required time 1.339
****************************************
****************************************
Endpoint: U_vpe/U3vpu/U13dmemb/U1DMEM00/u0/u0
Path Group: vpe_clk
Path Type: min
-----------------------------------------------------------------------------
U_vpe/U3vpu/U13dmemb/U1DMEM00_mbist/mbistWrapperLogic/mbistPartialWriteData_reg_reg[3]/CK
(SDFFTRX4AD)
U_vpe/U3vpu/U13dmemb/toMem_TD_0_63_3 (net)
1 0.003
U_vpe/U3vpu/U13dmemb/toMem_TD_0_63_1 (net)
9 0.102
clock reconvergence pessimism -0.105 0.752
inter-clock uncertainty 0.100 0.852
U_vpe/U3vpu/U13dmemb/U1DMEM00/u0/u0/CLK (rfrw_512x64_wm4) 0.852
r
data required time 0.883
* - page *
R: Cell delay when Output pin transitions from 0->1
F: Cell delay when Output pin transitions from 1->0
What is the longest data arrival time?
What is the shortest data arrival time?
* - page *
Lab Session 3
Delays given are :
U1 = 1.1 ns, U2 = 1.1 ns, U3 = 1 ns, U4 = 0.11ns, U5 = 0.11ns
Clk2Q = 0.5 ns max, 0.4 ns min, Tsu = 0.21ns
TH= 0.1ns
Calculate (i) Data Arrival Time for setup, (ii) Data Required time
for setup, (iii) Setup Slack, i.e. is setup timing met? (iv) Data
Required time for Hold, (v) Hold Slack, i.e. is hold timing
met?
* - page *
Lab Session 4
Perform Setup/Hold Analysis for the following circuitry and report
slack. If there are any timing violations, suggest fixes that can
be done on the circuit so that the circuit operates within the
stated timing objective.
Frequency of CLK = 100 MHz
Setup time of Flip-Flop (FF1, FF2, FF3, FF4 etc) = 2 ns
Hold time of Flip-Flop (FF1, FF2, FF3, FF4 etc) = 1 ns
Clock to Q delay of Flip-Flop (FF1, FF2, FF3, FF4 etc) = 300
ps.
Propagation delay of Buffers in the library (B1, B2, B3, B4, B5
etc) is 500 ps.
Propagation delay of 2:1 Mux in the library (M1 etc) from input
IN1/IN2 to OUT is 1 ns.
Propagation delay of 2:1 Mux in the library (M1 etc) from input SEL
to OUT is 500 ps.
Assume all net delays as zero.
* - page *
* - page *
Lab Session 5
For the circuit shown below, find the maximum frequency of CLK?
Also draw the output waveform of SIGA for input CLK at the maximum
frequency.
Setup time of D Flip-Flop (D-FF) = 2 ns
Hold time of D Flip-Flop (D-FF) = 1 ns
Clock to Q delay of Flip-Flop (D-FF) = 500 ps.
Propagation delay of the Invertor (I1) = 500 ps.
Assume all net delays as zero.
* - page *
Lab Session 6
In the circuit given below what is the maximum delay allowed in the
combo cloud to operate the circuit at 100MHz.
Clk to Q of Flop = 1ns
Flop Setup Time = 700ps
Flop Hold Time = 300ps
(Assume Wire Delays and Inverter Delay I1 are Zero and
the Duty cycle is 50%)
* - page *
What is the function of this circuit?
Which of the following is correct? (Answer the questions
based on the figure below)
Compared to Figure 1 In Figure 2 FF2 Setup margin increased and
Hold margin increased
Compared to Figure 1 In Figure 2 FF2 Setup margin decreased and
hold margin increased
Compared to Figure 1 In Figure 2 FF2 Setup margin decreased and
hold margin decreased
Compared to Figure 1 In Figure 2 FF2 Setup margin increased and
hold margin decreased
Ans: (b)
Need for Timing Analysis