DATA ACQUISITION AND REAL-TIME DISPLAY FOR HIGH CHANNEL COUNT

ELECTROPHYSIOLOGY

Advisor: Prof. Jonathan Viventi

Co-Advisor: Prof. N. Sertac ArtanPresenter: Ashraf ElSharif

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OUTLINE

•Self Introduction

•Purpose

•Open Ephys System

•64 Channel Real-Time System

• Intro & Method

• Results & Tests

•Scaling Up

•Conclusion

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ABOUT ME•Education

• Masters : NYU Polytechnic SoE – MS Computer Engineering – VLSI (Jan’13-Jan’15)• GPA: 3.91 – Thesis : Data Acquisition for High Channel Count Electrophysiology

• Graduate Innovation Fellowship & Grant based on undergrad project

• Bachelors : Ain Shams University Faculty of Engineering – BS Communication Systems Engineering – (Sep’07-Jun’12)• GPA: 3.14 – Graduation Project : LTE Planning Tool

•Professional

• Research Assistant – Translational Neuroengineering Lab (Jun’13-Dec’14)• Seizure Detection Medical Device

• Open Source High Channel Count DAQ System for Electrophysiology (Presentation)

• Teaching Assistant – CS2204 Digital Logic and State Machine Design (Sep’13-Dec’14)

• Embedded Systems Software Intern – Motorola Solutions (Jun’14-Aug’14)• Emerging Business Office

• Worked on bringing up & writing firmware for a prototype board for a new project.

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ABOUT TNEURO (THE LAB)

Our research applies innovations in flexible electronics tocreate new technology for interfacing with the brain at a much finer scale and with broader coverage than previously possible. We create new tools for neuroscience research and technology to diagnose and treat neurological disorders, such as epilepsy. Using these tools, we collaborate with neuroscientists and clinicians to explore the fundamental properties of brain networks in both health and disease. Our research program works closely with industry, including filing five patents and several licensing agreements. Our work has also been featured as cover articles in Science Translational Medicine and Nature Materials, and has also appeared in Nature Neuroscience, the Journal of Neurophysiology, and Brain.

Source : TNEURO.com

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PURPOSE

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PURPOSE

•Data Acquisition System for Electrophysiology

• With Real-Time display

• Benefits our lab

• Benefits research

• Open-Source

• Benefits our lab

• Benefits Brain Computer Interface Applications

• Leverages existing Open-Source system

• Interoperability with existing systems in other labs

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OPEN EPHYS SYSTEM

•Open-Source Data Acquisition and Real-Time Display

• FPGA Acquisition Board

• Graphical User Interface (GUI)

• Works With Intan© Head-stages

• Supports up to 512 Channels , 128Ch per Port

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Intan© HeadstageOpen Ephys FPGA

Open Ephys GUI

FOOLING THE OPEN EPHYS SYSTEM

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DIFFERENCE BETWEEN RHD2XXX AND DDC232

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RHD2xxx Protocol

DDC232 Protocol

MODIFICATION TO OPEN EPHYS SYSTEM

•Inserting a Translating FPGA in between the Headstage andOpen Ephys FPGA

• Benefits

• Could be on headstage

• Could be on a commutator

• Provides an abstraction, Modifiable

• Small size (4*4 mm)

• High bandwidth

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64 CHANNEL REAL-TIME SYSTEM

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64 CHANNEL REAL-TIME SYSTEM

•Proof of concept

• Uses existing 64 Channel current sensing head-stage

• Existing electrodes

• Helps in lab experiments

• Could be tested on a chronically implanted albino rat

•System Block Diagram

• Signaling, connectivity.

• Connectors, Physical Layer

• Modules

• Roles

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HARDWARE MODULES

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2xDDC232 Headstage Translating FPGA Board Open Ephys Board

METHOD

•Translating FPGA

• Picking the FPGA

• Small size to potentially fit on a head-stage

• LVDS Inputs/Outputs

• RAM availability

• Low Cost

• Not much LUTs since the FPGA will do minimal work

• At least 1 PLL

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PICKING THE FPGA

•Xilinx

• Spartan 6 8x8mm , Artix 7 10x10mm, Zynq 7000 13x13mm

• Spartan 6 XC6SLX16 2278 Slices (14k Logic Cells) , 576kb BRAM , 116 LVDS Pairs

•Altera

• Cyclone V 5CGC4 11x11mm , 50k Logical Elements

•Lattice

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Area Best Option Features

3 x 3 mm LP1K - 49 ucBGA (0.4 mm) 0 PLL, 35 GPIO, 5 LVDS

4 x 4 mm LP8K - 81 ucBGA (0.4 mm) 1 PLL, 63 GPIO, 9 LVDS

5 x 5 mm LP8K - 121 ucBGA (0.4 mm) 2 PLL, 93 GPIO, 13 LVDS

LATTICE ICE40 LP/HX FAMILY

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Features LP384 LP640 LP1K LP4K LP8K HX1K HX4K HX8K

Logic Cells 384 640 1280 3520 7680 1280 3520 7680

Non-Volatile Config.

Mem.(NVCM)

Yes Yes Yes Yes Yes Yes Yes Yes

Static Current 21 uA 100 uA 100 uA 250 uA 250 uA 296 uA 1140 uA 1140 uA

Embedded RAM Bits 0 64 K 64 K 80 K 128 K 64 K 80 K 128 K

Phase-Locked Loops - - 1 2 2 1 2 2

ICE40 ARCHITECTURE

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SB_IO MODULE

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•Input/Output Block• In Pairs

• DDR ( Double Data Rate)

• LVDS

THE TRANSLATING FPGA

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SPI SLAVE MODULE

•198 Logic Cells after PAR

•283 MHz Max Frequency (~FPGA MAX)

•No Adders, Replaced with Shift Registers

• Higher Clock frequency

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SPI SLAVE MODULE – TIMING SIMULATIONS

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Loopback Test

Chip Select to MISO1 Delay

(The Critical Path)

DDC DRIVE MODULE

•436 Logic Cells after PAR

•135 MHz Max Frequency

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DDC DRIVE MODULE – TIMING SIMULATIONS

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DDC232 Datasheet

Timing Simulation

DDC DRIVE MODULE – TEST VS SIMULATION

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ddc_dvalid

conv

ddc_dclk

TOP MODULE (TRANSLATING FPGA)

•Merges between the SPI Slave & DDC Drive Modules.

•Responds to commands from Open Ephys Board

•Sends configuration data to DDC Drive Module

•Resets DDC Drive Module

•Generates Convert Signal to DDC Drive Module

•Crosses signals across 3 Clock Domains using Multi Cycle Path Formulation (explained later )

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TOP MODULE – RESOURCE CONSUMPTION

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Category Consumption

LogicCells 1482/7680

BRAMs 2/32

IOs and GBIOs 26/206

PLLs 2/2

TOP MODULE – IMPORTANT PROCESSES & COMMANDS

•Slave Capture Process

• Raises interrupt to Command Center Process when data is ready at SPI Slave

•Slave Command Center Process

• Generates replies to Commands.

• Convert(channel)

• Reads data that has been saved to the RAM

• ReadRegister(register)

• WriteRegister(register,value)

•DDC Data Capture Process

• Captures data from headstage and saves to the RAM

•Cyclic Buffer Solution to different Read/Write timings.

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RAM ORGANIZATION

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BANKA_1 BANKA_2

buffer0 buffer0

buffer1 buffer1

buffer2 buffer2

buffer3 buffer3

CLOCK DOMAIN CROSSING (CDC)

•Multi-Cycle Path Formulation

• Uses a Synchronizer to synchronize a Flag signal. The Data Bus needs not tobe synchronized.

• Simple to implement.

• Good for most applications which require synchronization.

• Another method could use an async FIFOand Gray Counter but uses more resources.

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CLOCK DOMAIN CROSSING

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𝑀𝑇𝐵𝐹 =1

𝑓𝑟𝑒𝑞𝑓𝑙𝑎𝑔 ∗ 𝑓𝑟𝑒𝑞𝑑𝑠𝑡_𝑐𝑙𝑘 ∗ 𝑇𝑜∗ 𝑒(

𝑡′𝑇) • With 2 FF synchronizer

• To & T Depend on Technology.

MODIFIED OPEN EPHYS GUI

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RESULTS AND TESTS

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IN LAB TESTS (SALINE + SIGNAL GENERATOR)

•An input signal was input into a saline solution and varied depending on test.

•The rest of the system was hooked up as if it were used in field.34

SEQUENCE NUMBER CHECK

•A 15 minute recording of all 64 channels was run , the sequence number was sent on channel 64 and checked on Matlab to see if there were any drops. There were 0 drops from 5388288 samples

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FREQUENCY TEST

Another recording without the sequence number being sent was run with an input frequency of 10 Hz. A non clipping channel with low impedance was chosen and the results are as follows

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SIGNAL DIFF TEST

This tests purpose is to determine if there were bit inversions or skips in the signal which would give high difference between samples.

The following is a 1 second snap of the samples and difference function for both signal and control.

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SIGNAL DIFF TEST - HISTOGRAMS

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The diffs for both the control and 10 Hz signal were confined from negative 2000 to 2000 and there were no outliers which would have been attributed to a Bit Error Rate.

The surprising result, the 10 Hz diff looks nothing like the bath-tub curve which I would have expected.

STD=293 STD=168

SIGNAL DIFF TEST - HISTOGRAMS

This graph is generated by using the control noise signal and adding a sin wave of 10Hz to it with higher amplitudes. Blue signifies no while Red signifies a high amplitude sin wave of 2.5*10^5 ADC Ticks.

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IN FIELD TESTS

•This test has occurred in the Skirball Institute of Bio-molecular Medicine at the NYU Langone Medical Center

•The test subject was an albino rat, chronically implanted with an electrode array placed in the subdural cavity in proximity to the auditory cortex.

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IN FIELD TESTS - CONTINUED

•The test was a series of pips played at different frequencies and amplitudes in order to test the evoked response.

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CONCLUSION

•Able to demonstrate a 64 channel Open-Source Real-Time Electrophysiology System

•Could be scaled up to achieve 1024 channels without significant changes in the Open Ephys FPGA and protocols

•The Open Ephys software would need to be modified to achieve channel counts higher than 512

•To assure no failure, we should utilize a single clock domain. Although practically the chance of a failure and it’s affect is minor, but it can be avoided.

•The design could be inserted in a smaller capacity FPGA since it used only 1482/7680 Logic Cells.

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SCALING UP

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MULTIPLEXING THE CHANNELS ON STREAMS

•Does not require change of the Open Ephys FPGA code

•Requires minor changes on the Translating FPGA & Open Ephys GUI

•Just increase number of Block Rams and replicate the input channels for the test ( No new Head-stage ) as a proof of concept.

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RESULT

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FINAL CONCLUSION AND FUTURE WORK•We were able to demonstrate how to build a 64 channel system , and how to scale it up to 128.

•Next step will be to have 4 DDC264 Head-stages connected to the Translating FPGA and that would yield a channel count of 256.

•We can reach to 512 Channels with minor changes.

•Reaching to 1024 channels would require Changes on the GUI

•Reaching beyond 1024 channels would require a protocol change to increase the bandwidth of the SPI line.

•An open-loop half-SPI/LVDS line could reach 140 MHz which we have tested in the lab using a loop-back test.

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THANK YOU Questions?

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