Post on 07-Oct-2020
There’s Plenty of Room at the Bottom‐ and at the Top
Tsu‐Jae King LiuDepartment of Electrical Engineering and Computer Sciences
University of California, Berkeley
August 16, 2016SFBA Nano Seminar
14 nm chip X‐SEM from www.intel.com/content/dam/www/public/us/en/documents/pdf/foundry/mark‐bohr‐2014‐idf‐presentation.pdf
Outline
• Introduction– Transistor scaling limit
• Extending the Era of Moore’s Law
• Beyond Moore: Mechanical Computing Redux
• Summary
2
MOSFET Operation: Gate Control
Current flowing between Source & Drain is controlled by the Gate voltage.
Desired characteristics:• High ON current• Low OFF current
Electron Energy Band Profile
increa
sing
E
distance
n(E) exp (‐E/kT)
SourceDrain
VDD
ION
IOFF
Inverse slope is subthreshold swing, S[mV/dec]
log ID
increasingVGS VTH
GATE VOLTAGE0
3
Metal‐Oxide‐Semiconductor (MOS)Field‐Effect Transistor (FET)
Gate length, LG
CMOS Circuits
0 1
1 0
STATIC MEMORY (SRAM) CELL
DS
G
DS
G
CIRCUIT SYMBOLSN-channelMOSFET
P-channelMOSFET
GND
VDD
CMOS INVERTER CIRCUIT
VIN VOUT
S
S
DD
VOUT
VIN0 VDD
VDD
INVERTERLOGIC SYMBOL
BIT LINE
WORD LINE
BIT LINE
CMOS NAND GATE
NOT AND (NAND)TRUTH TABLE
or or
ON
OFF
4
Improving ION/IOFFlog ID
VGSVDD
ION
• The greater the capacitive coupling between Gate and channel, the better control the Gate has over the channel potential.
Body
Gate
Drain
CoxCdep
higher ION/IOFF for fixed VDD, or lower VDD to achieve target ION/IOFFreduced short‐channel effect and drain‐induced barrier lowering:
Source
SourceDraindecreasing LG,
or increasing VDS
ox
total
CCS
log ID
VGS
decreasing LGor increasing VDS IOFF
5
Source
DrainGate
LG
FinFET/Tri‐Gate Transistor
• Superior gate control higher ION/IOFF or lower VDD
Wfin
Hfin
GATE
SOURCE
DRAIN20 nm
10 nm
Y.‐K. Choi et al., (UC Berkeley) IEDM 2001
15nm Lg FinFET
D. Hisamoto et al. (UC Berkeley), IEDM 1998
Intel Corp., May 2011
log ID
VGS
ION
VDD
• Multiple fins can be connected in parallel to achieve higher drive current.
6
Foundry Technology Node: 14 nm 10 nm 7 nmGate length, LG 25 nm 20 nm 15 nmFin width, Wfin ~10 nm ~8 nm ~6 nmEquivalent oxide thickness 0.9 nm 0.85 nm 0.8 nm
C. Auth et al. (Intel Corp.)VLSI Symp. 2012
X‐SEM Images
Si
SiO2 SiO2
Gate
Intel Technology Node 22 nm 14 nm 10 nm2012 2014 2017
2015
Gate
Si SiSiO2
S. Natarajan et al. (Intel Corp.)IEDM 2014
Year:
Year:
3‐D Transistor Technology Roadmap
7
MOSFET Evolution32 nmplanar
P. Packan et al. (Intel), IEDM 2009
beyond 7 nmstacked nanowires?
C. Dupré et al. (CEA‐LETI)IEDM 2008
Stacked gate‐all‐around (GAA) FETs achieve the highest layout efficiency.
22 nmthin body
Intel Corp.
FinFET:
FD‐SOI:
K. Cheng et al. (IBM), VLSI Symp. 2011
8
J. Wang et al., IEDM Technical Digest, pp. 707‐710, 2002
Channel‐Length Scaling Limit• Quantum mechanical tunneling sets a fundamental scaling
limit for the channel length (LC).
SOURCE DRAIN
EC
EC
If electrons can easily tunnel through the source potential barrier, the gate cannot shut off the transistor.nMOSFET Energy Band Diagram(OFF state)
9
Ultimately Scaled MOSFETsM. Luisier et al., IEDM 2011
LG = 5 nm
10
Outline
• Introduction
• Extending the Era of Moore’s Law
• Beyond Moore: Mechanical Computing Redux
• Summary
11
12Sang Wan Kim02/25/2016
Samsung, EUVL Symposium 2009ASML, SPIE Advanced Lithography 2012
SingleExposure
LELE SingleSpacer
DoubleSpacer
0
1
2
3
4
5
Nor
mal
ized
Cos
t and
Ste
ps
Cost Steps
Multiple‐patterning techniques have extended Moore’s Law beyond the lithographic resolution limit at increasing cost
“The sheer cost and complexity of this lithographic solution could dissuade chipmakers from jumping to future nodes, thereby stunting the growth rates of the IC industry.”
‐ Semiconductor Engineering, April 17th, 2014
12
Tilted ion implantation (TII) Approach• A sub‐lithographic damage region can be achieved by tilted
ion implantation (TII) + photoresist/hard mask– self‐aligned to pre‐existing mask features on surface
13
Impact of TII on SiO2 Etch Rate
0 10 20 30 40 500.0
0.3
0.6
0.9
1.2
1.5
Etch
rate
[Å/s
ec]
SiO2 Depth [Å]
2E14
3E14
0.4
0.8
1.2
1.6
2.0
2.4
no implant
2E14D
amage [x10
22/cm3]
3E14
~9X~6X
Ar+ implant conditions: 15° tilt; 1.5 keV; dose = 0, 2 or 3 x 1014/cm2
Symbols & solid lines: etch rate in 200:1 DHF
Dotted lines: damage profile (SRIM)
14
S. W. Kim et al. (UC Berkeley), SPIE Advanced Lithography 2016
Double‐Patterning by TII
Si
Silicon
αα
Wtrench
θ
x x
yhard mask
SiO2
• Thermal SiO2: masking layer• Formation of linear a-Si hard-mask
features by spacer patterning
• First implant: positive tilt anglex ≅ Wtrench – y(tan(θ) – cot(α))
15
hard mask
SiO2
• Thermal SiO2: masking layer• Formation of linear a-Si hard-mask
features by spacer patterning
• First implant: positive tilt anglex ≅ Wtrench – y(tan(θ) – cot(α))
• Second implant: negative tilt anglex ≅ Wtrench – y(tan(θ) – cot(α))
Double‐Patterning by TII
16
Si
Silicon
α
WfinWfinx xx x
yhard mask
SiO2
• Thermal SiO2: masking layer• Formation of linear a-Si hard-mask
features by spacer patterning
• First implant: positive tilt anglex ≅ Wtrench – y(tan(θ) – cot(α))
• Second implant: negative tilt anglex ≅ Wtrench – y(tan(θ) – cot(α))
• Selective removal of damaged SiO2• Si substrate dry etch
Wfin ≅ 2y(tan(θ) – cot(α)) – Wtrench
Double‐Patterning by TII
17
remaining a-Si
Si substrate
etched a-Si15°
①②
③
Ar-ion implantation with θ = 15°
Si substrate
Proof of Concept: Single Implant
• Sub‐lithographic features (~45 nm) achieved by 15° tilt, 3.0 keV Ar+ implant into 10 nm‐thick SiO2 hard mask dilute HF etch Si dry etch
Cross‐sectional Scanning Electron Micrographs
18
S. W. Kim et al. (UC Berkeley), SPIE Advanced Lithography 2016
Self‐Aligned Nature of TII Patterning
• The TII‐defined edge closely tracks the HM edge
= a‐Si hard mask = un‐etched c‐Si = etched c‐Si 19
P. Zheng et al. (UC Berkeley), to be published
Line‐Edge Roughess Comparison
• TII improves low‐ and mid‐frequency line‐edge roughness
36 samples, 2.74 µm long
20
P. Zheng et al. (UC Berkeley), to be published
①②
③
a-Si
Si substrate
15°
①
②
③
LTO
Double Tilted Implant Results
• Local pitch‐halving achieved with ±15° tilt, 3.0 keV Ar+ implants• ~21 nm half‐pitch of the etched Si features
Cross-sectional SEM Plan-view SEM
21
S. W. Kim et al. (UC Berkeley), SPIE Advanced Lithography 2016
SiO2 (Oxidation)
Silicon
Hard mask (CVD)
SiO2 (Oxidation)
Silicon
SiO2 (Oxidation)
Silicon
Silicon Silicon
Tilted Ion Implantation (TII)Spacer lithography (SADP)
Double‐Patterning Approaches
22
Cost Comparison
• If photoresist is used as the mandrel layer, the cost of TII double‐patterning can be only ~50% of the cost of SADP.
Self-aligned Double Patterning TII Double Patterning Process Steps Cost Process Steps Cost
Process Description (a.u./wafer) Process Description (a.u./wafer) PECVD Etch stop layer 1.5 LPCVD Mask layer 2
CVD Mandrel layer 2 CVD Mandrel layer 2 Photolithography Patterning 30 Photolithography Patterning 30
Dry etch Mandrel etch 10 Dry etch Mandrel etch 10 ALD Spacer deposition 3 Ion implantation Double implants 1.7
Dry etch Spacer etch 16 Wet etch Selective mask etch 1 Mandrel pull Dry etch Mandrel removal 16 Wet clean Clean 1 Pattern transfer
Dry etch Pattern transfer 16 Wet etch Mask removal 1 Pattern transfer
Wet etch Spacer removal 1 Wet etch Etch stopper strip 1
Total: 81.5 Total: 63.7
P. Zheng et al. (UC Berkeley), to be published
23
Outline
• Introduction
• Extending the Era of Moore’s Law
• Beyond Moore: Mechanical Computing Redux
• Summary
24
Impact of Moore’s Law
Source: Morgan Stanley Research
# DEV
ICES
YEAR
1011
1010
109
108
107
106
1960 1970 1980 1990 2000 2010 20302020
MarketGrowth
Investment
TransistorScaling
Lower Cost/ComponentHigher Performance
Mobile Internet
Desktop Internet
PC
Minicomputer
Mainframe
Internet of Things (IoT)
25
The Cloud(millions)
The Swarm(trillions)
A Vision of the Future
Mobile devices(billions)
Source: J. Rabaey, ASPDAC 2008
Ultra‐low‐power ‐chips required!
26
Micro‐Electro‐Mechanical Switch
Source Drain
Measured I‐VCharacteristic
Gate
ON State:
Felec
Fspring
OFF State:
Fadhesion
• Zero off‐state leakage Zero passive energy consumption
Three‐Terminal Switch
• Abrupt switching behavior Low VDD (low active energy)
27
Vmin
Surface Micromachining Process
sacrificial layerstructural film
Cross‐sectional View
Si wafer substrate • Structures are freed by selective removal of sacrificial layer(s)
• Mechanical structures can be made using conventional microfabrication techniques
28
IC Technology Advancement
Time
D. C. Edelstein, 214th ECS Meeting, Abstract #2073, 2008
S. Natarajan et al. (Intel), IEDM 2014
Intel’s 14nm CMOS technology
• Advanced back‐end‐of‐line (BEOL) processes have air‐gapped interconnects
can be adapted for fabrication of compact NEMS!29
• A relay can be implemented using multiple metal layersVias can be used for electrical connection and as torsional elements for lower keff
• Actuation electrodes on opposite sides of movable electrode structure 2 stable states (contacting D0 or D1)
• Low‐voltage (<1 V) operation can be achieved with small footprint (< 0.1 m2).
courtesy of Dr. Kimihiko Kato (UC Berkeley)
INPUT
D0D1
VDDGND
VDDGND
VDD
GND M2
M3
M4
M5
BEOL NEM SwitchN. Xu et al. (UC Berkeley), 2014 IEEE International Electron Devices Meeting
30
• A bi‐stable NEM switch is projected to operate with much less energy and delay than other non‐volatile switching devicescan be used to continually shadow the information stored in an SRAM cell
Non‐Volatile Device Comparison
31
N. Xu et al. (UC Berkeley), 2014 IEEE International Electron Devices Meeting
In‐Memory Computing• NV‐NEMory cell array for memory‐based super‐parallel data searching
Data11100
DL0
DL1
DL0
DL1
DL0
Data21101
Data31000
Data4Not programmed
WL1
WL2
WL3
WL4
BL1 BL2 BL3 BL4
A A A A
K. Kato et al., IEEE Electron Device Letters, Vol. 37, pp. 31‐34, 2016
32
Year 2015 2017 2019 2021 2023 2025
Half pitch, F (nm) 25.3 20.1 15.9 12.6 10.0 7.09
DL1DL0
AL1
AL0
Beam
BL
WL
Diffusion
Deformedbeam
VprogFloat
GND
AL0
AL1
DL0
DL1
BL
FFFF
F F
Deformationdirection
DL1 / AL1
DL0 / AL0
8F2
Metal: Al (Young’s modulus: 70 GPa)Gap: Air
Non‐Volatile NEMory Cell StructureK. Kato et al., IEEE Electron Device Letters, Vol. 37, pp. 31‐34, 2016
33
Data Search Step 1: Match “0”Reference Data: 1100
Data11100
DL 0
DL 1
DL 0
DL 1
DL 0
Data21101
Data31000
Data4Not programed
BL1
BL2
BL3
BL4
BL1 BL2 BL3 BL4
A A A A
a) Activate DL1 lines
b)Access rows for 0 bits in reference
c) Zero BL current Matched 0s
K. Kato et al., IEEE Electron Device Letters, Vol. 37, pp. 31‐34, 2016
34
Data Search Step 2: Match “1”Reference Data: 1100
Data11100
DL 0
DL 1
DL 0
DL 1
DL 0
Data21101
Data31000
Data4Not programed
WL1
WL2
WL3
WL4
BL1 BL2 BL3 BL4
A A A A
a) Activate DL0 lines
b)Access rows for 1 bits in reference
c) Zero BL current Matched 1s
K. Kato et al., IEEE Electron Device Letters, Vol. 37, pp. 31‐34, 2016
35
Energy and Delay for Data Search
• The location of a data string can be found in <0.5 ns with less than 2.5 pJ. For a die size of 42 mm2 (same as DDR4 DRAM) at F = 20 nm and cell
density of 65% (similar to DRAM), a NV‐NEMory chip would have the capacity 8 Gb and would consume only 300 nJ to find a match on the whole chip.
In comparison, it would take CPU+DRAM ~90 mJ, 80 ms for the same task.
EnergyDelay
Cells involved: 1 column 1 row
1 column 256 rows
256 columns 256 rows
Program (Vprog = 2.5 V) 15 fJ 2.0 pJ N/A < 10 ns
Match “0” or Match “1” N/A N/A 1.2 pJ < 0.2 ns
256 × 256 NV‐NEMory Array
Relatively fast read speed & low power consumption make NV‐NEMorytechnology well‐suited for real‐time data searching applications!
K. Kato et al., IEEE Electron Device Letters, Vol. 37, pp. 31‐34, 2016
36
Outline
• Introduction
• Extending the Era of Moore’s Law
• Beyond Moore: Mechanical Computing Redux
• Summary
37
Summary
• Tilted ion implantation (TII) is an effective sub‐lithographic patterning and pitch‐halving technique – features are self‐aligned to pre‐existing mask – process flow is much simpler (lower cost) than SADP
shows promise for extending Moore’s Law!• Electronic devices which enable more energy‐efficient computation and data storage, at ever lower cost per function, will be required for ubiquitous computing.• BEOL NEM devices show promise in this regard
38
Acknowledgements• TII‐Enhanced Lithography:
– Dr. Sang Wan Kim (UC Berkeley)– Dr. Peng Zheng (now with Intel Corporation)– Dr. Leonard Rubin (Axcelis Technologies)– UC Berkeley Marvell Nanofabrication Laboratory– Funding from Applied Materials, Lam Research
• BEOL NEM Relays Technology:– Dr. Nuo Xu (now with Samsung Semiconductor, Inc.)– Dr. Kimihiko Kato (now at University of Tokyo)– Prof. Vladimir Stojanović (UC Berkeley)– Funding from National Science Foundation
• Center for Energy Efficient Electronics Science39