THE INVERTERS. DIGITAL GATES Fundamental Parameters l Functionality l Reliability, Robustness l Area...

THE INVERTERS

DIGITAL GATES Fundamental Parameters

Functionality Reliability, Robustness Area Performance

» Speed (delay)» Power Consumption» Energy

Digital Integrated Circuits © Prentice Hall 1995IntroductionIntroduction

Noise in Digital Integrated Circuits

VDDv(t)

(a) Inductive coupling (b) Capacitive coupling (c) Power and ground

DC Operation: Voltage Transfer Characteristic

VOHVOL

fV(y)=V(x)

Switching Threshold

Nominal Voltage Levels

V(y)V(x)

Mapping between analog and digital signals

UndefinedRegion

Slope = -1

Definition of Noise Margins

UndefinedRegion

Gate Output Gate Input

Noise Margin High

Noise Margin Low

The Regenerative Property

(a) A chain of inverters.

v0, v2, ...

v1, v3, ... v1, v3, ...

v0, v2, ...

(b) Regenerative gate

finv(v)

(c) Non-regenerative gate

v0 v1 v2 v3 v4 v5 v6

Fan-in and Fan-out

(a) Fan-out N

(b) Fan-in M

The Ideal Gate

Ro = 0

VTC of Real Inverter

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

Delay Definitions

Ring Oscillator

v0 v1 v2 v3 v4 v5

v0 v1 v5

T = 2 tp N

Power Dissipation

CMOS INVERTER

The CMOS Inverter: A First Glance

Vin Vout

CMOS Inverters

Polysilicon

Metal1

1.2 m=2

Switch Model of CMOS Transistor

|VGS| < |VT||VGS| > |VT|

CMOS Inverter: Steady State Response

VDD VDD

VoutVout

Vin = VDD Vin = 0

VOH = VDD

VOL= 0

VM = Ronp) f(Ronn,

CMOS Inverter: Transient Response

Vin = VDD

tpHL = f(Ron.CL)

= 0.69 RonCL

ln(0.5)

CMOS Properties

Full rail-to-rail swing Symmetrical VTC Propagation delay function of load

capacitance and resistance of transistors No static power dissipation Direct path current during switching

Voltage TransferCharacteristic

PMOS Load Lines

VGSp=-5

VGSp=-2VDSp

IDnVin=0

Vin = VDD-VGSpIDn = - IDp

Vout = VDD-VDSp

IDnVin = VDD-VGSpIDn = - IDp

Vout = VDD-VDSp

CMOS Inverter Load Characteristics

In,pVin = 5

Vin = 4

Vin = 3

Vin = 0

Vin = 1

Vin = 2

NMOSPMOS

Vin = 0

Vin = 1

Vin = 2Vin = 3

Vin = 4

Vin = 5

Vin = 2Vin = 3

CMOS Inverter VTC

Vin1 2 3 4 5

NMOS linPMOS off

NMOS satPMOS sat

NMOS offPMOS lin

NMOS satPMOS lin

NMOS linPMOS sat

Simulated VTC

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

Gate Switching Threshold

0.1 0.3 1.0 3.2 10.01.0

MOS Transistor Small Signal Model

rogmvgsvgs

Determining VIH and VIL

Propagation Delay

CMOS Inverter: Transient Response

Vin = VDD

tpHL = f(Ron.CL)

= 0.69 RonCL

ln(0.5)

CMOS Inverter Propagation Delay

Vin = VDD

tpHL = CL Vswing/2

kn VDD

Computing the Capacitances

VDD VDD

VinVout

M4Cdb2

Fanout

Interconnect

VoutVin

SimplifiedModel

CMOS Inverters

Polysilicon

Metal1

1.2 m=2

The Miller Effect

Cgd1Vout

Vout V

“A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value.”

Computing the Capacitances

Impact of Rise Time on Delayt p

trise (nsec)10.80.60.40.20

Delay as a function of VDD

2.00 4.001.00 5.003.00

VDD (V)

Where Does Power Go in CMOS?

• Dynamic Power Consumption

• Short Circuit Currents

• Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors

MOS Transistors (again) Device Equations:

» Off (ignore sub-threshold): Vgs < Vt– Ids = 0

» Linear: Vgs > Vt & |Vdg|<|Vth|

» Saturation:Vgs>Vt & |Vgd| > |Vth|

Current Flow in an InverterR = 100 Ohms C = 0.1 pf (100 ff)

Spice Deck

*** SPICE DECK created from inv1.sim, tech=scmos

M1 2 4 1 1 CMOSP L=3.0U W=6.0U

M2 0 4 3 0 CMOSN L=3.0U W=6.0U

R3 2 5 100

R4 3 5 100

R5 5 6 100

C6 6 0 0.1000PF

*vin 4

*vout 6

vdd 1 0 dc 5v

****************V1 V2 Del Tr Tf Tpw Period

vin 4 0 pulse (0v 5v 5ns 5ns 5ns 5ns 50ns)

Dynamic Power Dissipation

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f

Need to reduce CL, Vdd , and f to reduce power.

Vin Vout

Not a function of transistor sizes!

Impact ofTechnology Scaling

Technology Evolution

Technology Scaling (1)

Technology Scaling (2)

Propagation Delay Scaling

Technology Scaling Models

• Full Scaling (Constant Electrical Field)

• Fixed Voltage Scaling

• General Scaling

ideal model — dimensions and voltage scaletogether by the same factor S

most common model until recently —only dimensions scale, voltages remain constant

most realistic for todays situation —voltages and dimensions scale with different factors

Scaling Relationships for Long Channel

Devices

Scaling of Short Channel Devices

THE INVERTERS. DIGITAL GATES Fundamental Parameters l Functionality l Reliability, Robustness l Area...

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