Post on 05-Jan-2016
description
Silicon Design Page 1
The Creation of a New Computer ChipThe Creation of a New Computer Chip
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A group of people from marketing, design,applications, manufacturing and finance develop the basic concept, features and rough specifications for a new product.
The Concept
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They all go off and work on their particularpieces of the proposal
Marketing – what are the customers asking for and what will sell vs. the competition, what is
the marketing plan, what will it cost
Design – how will it be designed, how long will it take, what design tools will be necessary, how many
people will it take, what will it cost
Manufacturing – how will it be manufactured, what tooling will be necessary, how many manufacturing
lines will it need, what will it cost
Finance – will the product make money, what is the return on investment, what resources are available and what will need to be acquired, what will it cost
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They all get back together again with management and decide whether or not toproceed will the project.
The Decision
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GO!
Once the decision is made to proceed,the design team swings into action
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Logic Level
RTL Level
Transistor Level
Logic Simulation
Extract Parasitics& create timing
model
RTL Simulation
Block Level
Physical LayoutLevel – (masks)
The Design Flow
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The Block Diagram
The problem is broken down into basicfunctions blocks and the interfaces are specified
Memory Registers ALU
Control BranchControl
Clock &Timing
I/O
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The High Level Description
The blocks are then broken down intofunctional units and registers. The functionalityis coded in a high level descriptive language.This is known as the RTL description.
operand selectionand register control
ALU controlmaster control
IR RegisterFile
ALU
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The High Level Simulation
The RTL description is simulated toensure that the design performs as itshould.
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The Logic Level Description
The functional units are then broken down into logic gates and registers. This is known as the logic level description.
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The Logic Level Simulation
The logic description is simulated toensure that the design performs as itshould. It is also compared against theRTL simulation.
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The Transistor Description
The logic gates are broken down to theircomponent transistors. From this description,the timing delays and electrical parasitics can be estimated. If necessary, transistors can beresized.
P
Field Effect Transistors
N type P type
OR
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Field Effect Transistor Operation
N type P type
S
D
G
S
D
G
Gate = Ground = ‘0’
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Field Effect Transistor Operation
N type P type
S
D
G
S
D
G
Gate = Vcc = ‘1’
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Silicon Wafer
P type substrate
GND
GND
N Type Field Effect Transistor
no current flow
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Silicon Wafer
P type substrate
GND
Vcc
N Type Field Effect Transistor
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Silicon Wafer
P type substrate
GND
Vcc
N Type Field Effect Transistor
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Silicon Wafer
P type substrate
GND
Vcc
current flow
N Type Field Effect Transistor
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Silicon Wafer
P type substrate
GND
Vcc
P Type Field Effect Transistor
no current flow
Vcc N-Well
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Silicon Wafer
P type substrate
GND
GND
P Type Field Effect Transistor
Vcc N-Well
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Silicon Wafer
P type substrate
GND
GND
P Type Field Effect Transistor
Vcc N-Well
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Silicon Wafer
P type substrate
GND
GND
P Type Field Effect Transistor
Vcc N-Well
current flow
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Logic Gate Implementation UsingField Effect Transistors
P
I O P
P
I1 I2
O
P PI2
I1O
I1
I2
O
I1
I2
OI O
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Silicon Wafer
P type substrate
Silicon Wafer
P type substrate
So how do we build Field Effect Transistors?
We start with a blank piece of silicon wafer
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Silicon Wafer
P type substrate
Silicon Wafer
P type substrate
Cover it with an N-well Mask
Silicon Wafer
P type substrate
Silicon Wafer
P type substrate
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N type dopant
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
Bombard it with negatively charged ions to create the N-well
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Create the N-well
N type dopant
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
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Create the N-well
N type dopant
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
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Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
Grow the Gate Oxide layer
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Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
Grow the Gate Oxide layer
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Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
Deposit Polysilicon
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Cover it with a Polysilicon mask
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
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Etchant
Etch the Polysilicon and Oxide
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
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Etchant
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
Etch the Polysilicon and Oxide
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Etchant
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
Etch the Polysilicon and Oxide
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Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
Etch the Polysilicon and Oxide
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Cover it with an N Transistor mask
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
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Implant the N type Dopant
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
N type dopant
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Implant N Dopant
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
N type dopant
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Cover it with a P Transistor mask
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
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Implant P Dopant
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
P type dopant
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Implant P Dopant
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
P type dopant
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Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
Grow more Oxide
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Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
Grow more Oxide
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Cover it with a Contact mask
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
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Etch the Oxide
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
Etchant
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Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
Etchant
Etch the Oxide
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Deposit Metal
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
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Deposit Metal
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
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Cover it with a Metal mask
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
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Etch the Metal
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
Etchant
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Etch the Metal
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
Etchant
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Deposit Insulation
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
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Deposit Insulation
Silicon Wafer
P type substrate
Silicon Wafer
P type substrateSilicon Wafer
P type substrate
Silicon Wafer
P type substrate
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A CMOS Inverter
IN
OUT
Gnd
Vcc
N-well
P
I OI O
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N-well Mask
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Polysilicon Mask
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N Transistor Mask
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P Transistor Mask
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Metal Mask
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Contact Mask
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IN
OUT
Gnd
Vcc
N-well
The Completed Circuit
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Partial Die Plot
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More Partial Die Plots
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Complete Chip Plot
Intel Microcontroller Chip – 80C196KJ
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Another Chip Plot
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Intel Pentium 4
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Processed Silicon Wafer
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Processed Silicon Wafer
A wafer
A die
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Wafer Fabrication
• Preceding steps done in a “wafer fab” – Silicon wafer fabrication facility
• Fabs are expensive– rely on high volumes to get part cost down
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Post-Wafer Fabrication
• Each die is tested to see which work
• Wafer is cut up– Good die are kept– Bad die are thrown away
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Packaging
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Packaging
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Packaging
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Packaging
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Packaging
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Packaging
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Final Testing
• Packaged chips are tested again– Burn-in used to eliminate infant mortality
• Good chips labelled and shipped