Telematics group -...

Telematics groupUniversity of Göttingen, Germany

Computer Science II(Summer Semester 2003)

Prof. Dr. Dieter HogrefeDr. Xiaoming FuKevin Scott, M.A.

Telematics groupUniversity of Göttingen, Germany

Computer Science II

Part I:

Digital Logic and Boolean Algebra

3SS 2003 Computer Science II

Table of Content

• Digital Number Systems• Logic Gates• Boolean Algebra• Karnaugh Maps• Applications: Addition and multiplication• Flip-Flops

Credits: • Howard Huang, UIUC

Digital Number System

• Decimal System – consists of 10 symbols: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9– using these symbols as digits of a number, we can express any

quantity. – The decimal system is also called the base-10 system because it

has 10 digits.

Decimalpoint

.Least SignificantDigit

Most SignificantDigit

=0.01=0.1=1=10=100=100010-210-1100101102103

Digital Number System (cont.)

• Binary System:– In the binary system, there are only two symbols or possible

digit values, 0 and 1. – This base-2 system can be used to represent any quantity that

can be represented in decimal or other number system.

Binarypoint

.Least SignificantBit

Most SignificantBit

=1/4=1/2=1=2=4=82-22-120212223

The Binary counting sequence is shown in the following table:

Binary Counting

Representing Binary Quantities• In digital systems the information is presented in binary form. Binary quantities

can be represented by any device that has only two operating states or possible conditions.

• Eg. a switch has only open or closed. By assigning it with binary 0 (open) and 1 (closed), we can represent any binary number by using series of switches.

• Typical Voltage Assignment– Binary 1: Any voltage between 2V to 5V– Binary 0: Any voltage between 0V to 0.8V– Not used: Voltage between 0.8V to 2V, this may cause error in a digital circuit.

Number Systems and Codes

• Decimal (base-10): universial used to represent quantites outside a digital system

• Binary (base-2): most important in digital systems, but it is too long to express

• Thus, other systems were introduced:– octal (base-8)– hexadecimal (base-16)

• How can one convert from one numbersystem to another??

Binary-To-Decimal Conversion

• Method: find the weights (i.e., power of 2) of the various positions in the binary number which contain a 1, and add them up. Example:1 1 0 1 1 2 (binary)24+23+0+21+20 = 16+8+0+2+1= 2710 (decimal)��

1 0 1 1 0 1 0 1 2 (binary)27+0+25+24+0+22+0+20 =128+0+32+16+0+4+0+1

= 18110 (decimal)

Decimal-To-Binary Conversion

• (A) Revese of Binary-To-Digital Method45 10 = 32 + 0 + 8 + 4 +0 + 1

= 25+0+23+22+0+20

= 1 0 1 1 0 12

• (B) Repeat DivisionThis method uses repeated division by 2. Eg. convert 2510 to binary

��

Octal Number System

• The octal number system has a base of eight, meaning that it has eight possible digits: 0,1,2,3,4,5,6,7.

• Octal to Decimal Conversioneg. 24.68 = 2 x (81) + 4 x (80) + 6 x (8-1) = 20.7510

Octalpoint

.Least SignificantDigit

=1/512=1/8=1=8=64=512

8-28-180818283

Binary-To-Octal / Octal-To-Binary Conversion

Octal Digit 0 1 2 3 4 5 6 7Binary Equivalent 000 001 010 011 100 101 110 111

Each Octal digit is represented by three bits of binary digit.eg. 100 111 0102 = (100) (111) (010)2 = 4 7 28

Repeat DivisionThis method uses repeated division by 8. Eg. convert 17710 to octal and binary:��

��

Hexadecimal Number System

• The hexadecimal system uses base 16. Thus, it has 16 possible digit symbols. It uses the digits 0 through 9 plus the letters A, B, C, D, E, and F as the 16 digit symbols.

Hexa-decimalpoint

Least SignificantDigit

=1/4096=1/16=1=16=256=4096

16-216-1160161162163

Hexadecimal to Decimal Conversion

• eg. 2AF16 = 2 x (162) + 10 x (161) + 15 x (160) = 68710

Repeat Division: Convert decimal to hexadecimalThis method uses repeated division by 16.

Eg. convert 37810 to hexadecimal and binary:

��

Other Conversions

• Binary-To-Hexadecimal / Hexadecimal-To-Binary ConversionHexadecimal Digit 0 1 2 3 4 5 6 7Binary Equivalent 0000 0001 0010 0011 0100 0101 0110 0111Hexadecimal Digit 8 9 A B C D E FBinary Equivalent 1000 1001 1010 1011 1100 1101 1110 1111

Each Hexadecimal digit is represented by four bits of binary digit.eg. 1011 0010 11112 = (1011) (0010) (1111)2 = B 2 F16

• Octal-To-Hexadecimal / Hexadecimal-To-Octal Conversion1) Convert Octal (Hexadecimal) to Binary first.2a) Regroup the binary number in 3 bits a group starts from the LSB if Octal is required.2b) Regroup the binary number in 4 bits a group from the LSB if Hexadecimal is required.

eg. Convert 5A816 to Octal:5A816 = 0101 1010 1000 (Binary) = 2 6 5 0 (Octal)

Table of Content

Boolean Variables

• Boolean algebra differs from ordinary algebra in that booleanconstants and variables are allowed to have only two possible values, 0 or 1.

• Boolean 0 and 1 do not represent actual numbers but instead represent its logic level.

• Some common representation of 0 and 1:

• There are three basic logic operations for boolean 0 and 1:OR, AND and NOT.

• Two extended operations:NOR, and NAND are also used extensively in digital circuits. Close

switchOpen switch

YesNoHighLowOnOffTrueFalseLogic 1Logic 0

Truth Table

• A means for describing how a logic circuit's output depends on the logic levels present at the circuit's inputs.

• A truth table lists all possible combinations of logic levels present at inputs (A and B in the following example) along with the corresponding output level (X).

When either input A OR B is 1, the output X is 1. Therefore the "?" in the box is an OR gate. • We will explore more on the OR gate later.

FunctionOutputInput(s)

Function

We can represent logical functions in two analogous ways.—A Boolean expression is finite but not unique.— A truth table turns out to be unique and finite.

OR Operation

• The expression X = A + B reads as "X equals A OR B". The + sign stands for the OR operation, not for ordinary addition.

• The OR operation produces a result of 1 when any of the input variable is 1.• The OR operation produces a result of 0 only when all the input variables are 0.

AND Operation

• The expression X = A * B (or X=AB) reads as "X equals A AND B". The multiplication sign stands for the AND operation, same for ordinary multiplication of 1s and 0s.

• The AND operation produces a result of 1 occurs only for the single case when all of the input variables are 1.

• The output is 0 for any case where one or more inputs are 0.

NOT Operation • The NOT operation is unlike the OR and AND operations in that it can be performed

on a single input variable. For example, if the variable A is subjected to the NOT operation, the result x can be expressed as x = A'

• where the prime (') represents the NOT operation. This expression is read as:x equals NOT A x equals the inverse of A x equals the complement of A

• Each of these is in common usage and all indicate that the logic value of x = A' is opposite to the logic value of A.

• The NOT operation is also referred to as inversion or complementation, and these terms are used interchangeably.

NOR Operation

• NOR is the same as the OR gate symbol except that it has a small circleon the output. This small circle represents the inversion operation. Therefore, the output expression of the two input NOR gate is:X = ( A + B )', or X = A NOR B

NAND Operation • NAND is the same as the AND gate symbol except that

it has a small circle on the output. This small circle represents the inversion operation. Therefore the output expression of the two input NAND gate is:X = (AB)', or X = A NAND B

A NAND for everything

yxxxyx

yxxyxxx

'xy'y y' NAND '

)' NAND ( NAND '

+=⊕=+==not

andorxor

Table of Content

Describing Logic Circuits Using Boolean Expressions

• Any logic circuit can be described using the Boolean operations– Because OR gate, AND gate, and NOT circuit are the basic

building blocks of digital systems!• Examples of circuits using Boolean expression:

• A more complex example (with NOT):

Note:If an expression contains both AND and OR operations, the AND operations are performed first (X=AB+C : AB is performed first), unless there are parentheses in the expression, in which case the operation inside the parentheses is to be performed first (X=(A+B)+C : A+B is performed first).

Simplifying Circuits

• The last example in previous page is actuallyequivalent to this simpler one:

• Simpler hardware is almost always better.– In many cases, simpler circuits are faster.– Less hardware means lower costs.– A smaller circuit also consumes less power.

• So were we able to simplify this particular circuit?

Boolean Theorems: Single Variable

Boolean Theorems: Mutiple Variables

x + x'y = x + y(15)

x + xy = x, x(x+y) = x (absorption law)(14)

(w+x)(y+z) = wy + xy + wz + xz(13b)

x (y+z) = xy + xz, x + yz = (x+y)(x+z) (distribution law)(13a)

x (yz) = (xy) z = xyz (associative law)(12)

x+ (y+z) = (x+y) +z = x+y+z (associative law)(11)

x * y = y * x (commutative law)(10)

x + y = y + x (commutative law)(9)

DeMorgan's Theorem

DeMorgan's Theorems(16) (x+y)' = x' * y'(17) (x*y)' = x' + y'

They are extremely useful in simplifying expressions in which a product or sum of variables is inverted. E.g.,

X= [(A'+C) * (B+D')]' = (A'+C)' + (B+D')' [by theorem(17)]= (A''*C') + (B'+D'') [by theorem (16)] = AC' + B'D

Three Variables DeMorgan's Theorem(18) (x+y+z)' = x' * y' * z'(19) (xyz)' = x' + y' + z'

Implications of DeMorgan's TheoremFor (16): (x+y)' = x' * y' For (17): (x*y)' = x' + y'

Alternate Logic Gate Representations1. Invert each input and output of the standard symbol2. Change the operation symbol from AND to OR, or from OR to AND. Then, the alternate symbols are the same as standard symbols! They represent

the same physical circuits.

Sum of products expressions

• There are many equivalent ways to write a function, but some formsturn out to be more useful than others

• A sum of product (SOP) expression consists of:– One or more terms summed (OR'ed) together.– Each of those terms is a product of literals.

F(x, y, z) = y' + x‘yz‘ + xz• SOP expressions can be implemented with two-level circuits.

Minterms• A minterm is a special product term, where each input variable

appears exactly once.• A function with n variables has up to 2n minterms. For example, a

three-variable function like f(x,y,z) has up to 8 minterms:

• Each minterm is true for exactly one combination of inputs:

x’y’z’ x’y’z x’yz’ x’yzxy’z’ xy’z xyz’ xyz

Minterm Is true when… Shorthandx’y’z’ xyz = 000 m0x’y’z xyz = 001 m1x’yz’ xyz = 010 m2x’yz xyz = 011 m3xy’z’ xyz = 100 m4xy’z xyz = 101 m5xyz’ xyz = 110 m6xyz xyz = 110 m7

Hey! This looks like a truth table!

Sum of minterms form• Every function can be written as a sum of minterms, which is a

special kind of sum of products form.• The sum of minterms form for any function is unique.• If you have a truth table for a function, you can write a sum of

minterms expression just by picking out the rows of the table where the function output is 1.

x y z f(x,y,z) f’(x,y,z)0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1

f = m0 + m1 + m2 + m3 + m6= Σm(0,1,2,3,6)= x’y’z’ + x’y’z + x’yz’ + x’yz + xyz’

f’ = m4 + m5 + m7= Σm(4,5,7)= xy’z’ + xy’z + xyz

f’ contains all the minterms not in f.

Table of Content

Karnaugh Maps

• So far we used Boolean Algebra to build hardwarecircuits– The basic Boolean operations are AND, OR and NOT– Logic gates implement these operations in hardware– Boolean algebra helps us simplify expressions and circuits

• Expressions can be written in many ways, so standard representations like sum of products and sums of minterms are sometimes useful.

• Now we study Karnaugh Maps, an alternative, more"graphical" simplication technique that enables us to build and study larger, more realistic circuits.

Minimum Sums of Products

• When used properly, Karnaugh maps can reduceexpressions to a minimal sum of products (MSP)form.– There are a minimal number of product terms.– Each product has a minimal number of literals.

• A minimal sum of products may not be "minimal" byother definitions! E.g., x (y + z) = xy + xz– The expression on the left has fewer literals and fewer

operators than the one on the right, but it is not a sum of products.

– On the other hand, xy+xz is a sum of products, and it isminimal.

K-Map• Re-arrange them into a Karnaugh

map, or K-Map

• You can show either the actualminterms or just the mintermnumbers

• Notice the minterms are almost, but not quite, in numeric order

• Recall that an n-variable function has up to 2n

minterms, one for eachpossible input combination

• A function with input x, y and z includes up to 8 minterms:

xyz‘xyzxy‘zxy‘z‘

x‘yz‘x‘yzx‘y‘zx‘y‘z‘

m6m7m5m4

m2m3m1m0

The Pattern of K-Map• The literal x occurs in 4

minterms in the bottom, while x‘ occurs in top 4.

• The literal y occurs in right 4, while y‘ in left.

• The literal z occurs in middle 4 squares, whilez‘ occurs in the 1st and 4th columns.

z' z z'

We can base on this feature and simplify sums of minterms, without any Boolean algebra at all !e.g., x'y'z' + x'y'z = x'y

x'yz + x'yz' + xyz + xyz' = y

Map Simplifications• Four steps

– Start with a sum of minterms or truetable

– Plot the minterms on a K-map: put 1 in the K-map squares that correspondto the function minterms, 0 in theothers

– Find rectangular groups of mintermswhose sizes are powers of two.

– Reduce each group to one productterm.

• Two important goals when formingminterm groups– Making as few groups as possible– Making each group as large as

possible• Doing this properly will get a minimal

sum of products.

Multiple solutions are possible

Table of Content

Adding two bits

• How to make a hardwareadder?– We recall how human adds

• Now we start with a half adder, which adds two bitsX and Y and produces a two-bit results: a sum S (theright bit) and a carry out C (the left bit).

• Here are truth tables, expressions, circuits and bock symbol.

Adding three bits

Full adder expressions

Full adder circuit• We write the expression this way to highlight the hierarchical

nature of adder circuits – you can build a full adder by combiningtwo half adders!

2x2 binary multiplication

• Here is an outline of multiplying thetwo-bit numbers A1A0 and B1B0, to produce the four-bit product P3-P0.

• The bits of each partial product arecomputed by multiplying two bits of the input

• Since two-bit multiplication is thesame as the logical AND operation, we can use AND gates to generatethe partial products.

A 2x2 binary multiplier

• Here is a circuit thatmultiplies A1A0 and B1B0, resulting P3-P0

• For a 2x2 multiplier we canjust use two half adders to sum the partial products. In general, however, we‘ll needfull adders

• The diagram on the nextpage shows how this can beextended to a four-bitmultiplier, taking inputs A3-A0 and B3-B0 and outputtingthe product P7-P0.

A 4x4 binary multiplier

Shifty arithmetic operations

• In decimal, an easy way to multiply by 10 is to shift all the digits to the left, and tack a 0 to the right end.

128 x 10 = 1280• We can do similarly in binary. Shifting left once

multiplies by two.11x 10 = 110 (in decimal, 3x2 = 6)

• Shifting left twice is equivalent to multiplying by four.11x 100 = 1100 (in decimal, 3x4 = 12)

• Similarly, shifting once to the right is equivalent to dividing by two.

1100 / 10 = 100 (in decimal, 12/2 = 6)

Summary

• Arithmetic is the most basic thing that you can do with a computer; the circuits reflect human algorithmsfor addition and multiplication

• Addition, and multiplication are central operations of Arithmetic-Logic Units (ALUs), which are the "heart" of CPUs

• Adders and multiplication are built hierarchically– Start with half adders and full adders and base on them

• Note: adder circuits are limited in the number of bitsthat can handled. An overflow occurs when a resultexceeds this limit.

Table of Content

Combinational Circuits

• So far we‘ve only worked with combination circuits, where applying the same inputs always produces thesame outputs– This corresponds to a mathematical function, where every

input has a single, unique output– In programming terminology, combination circuits are similar

to "functional programs" that do not contain variables and assignments

• Such circuits are relatively easy to design and analyze

Combinational CircuitsInputs Outputs

Sequential Circuits

• In contrast, the outputs of a sequential circuit dependon not only the inputs, but also the state, or thecurrent contents of some memory.

• This makes things more difficult to understand sincethe same inputs can yield different outputs, depending on what's stored in memory.

• The memory contents can also change as the circuitruns, so the order in which things occur makes a difference.

Combinational CircuitsInputs Outputs

Memory

Memory Elements

� Memory element: a device which can remember value indefinitely, or change value on command from its inputs.

� Characteristic table:Command(at time t)

Q(t) Q(t+1)

Set X 1

Reset X 0

0 0Memorise /No Change 1 1

commandMemory element stored value

Q(t): current state

Q(t+1) or Q+: next state

Memory Elements

� Memory element with clock. Flip-flops are memory elements that change state on clock signals.

� Clock is usually a square wave.

commandMemory element stored value

Positive edges Negative edges

Positive pulses

Memory Elements

� Two types of triggering/activation:� pulse-triggered� edge-triggered

� Pulse-triggered� latches� ON = 1, OFF = 0

� Edge-triggered� flip-flops� positive edge-triggered (ON = from 0 to 1; OFF = other

time)� negative edge-triggered (ON = from 1 to 0; OFF = other

An interesting circuit

• An SR latch above has two inputs S and R, which will let us control theoutputs Q and Q‘.

• Here Q and Q‘ feedback into the circuit. They are not only outputs, they‘re also inputs!

• To figure out how Q and Q‘ change, we have to look at both inputs S and R, but also the current values of Q and Q‘:

Qnext = (R+Q‘current)‘Qnext = (S+Q‘current)‘

• If S = 0, R=0: Qnext = Qcurren, Q‘next = Q‘current• This is exactly what we need to store values in the latch.• Instable state: SR=11 will cause Q and Q‘ cycle between 0 and 1

forever. � Nobody sets SR = 11.

Setting and Resetting the LatchQnext = (R+Q‘current)‘ Qnext = (S+Q‘current)‘

• Setting the latch:– If S = 1, R = 0. Q‘next = 0 � Qnext = 1– This is how you set the latch to 1, S means "Set“– Notice it can take up to two steps (two gate delays)

from the time S becomes 1 to the time Qnext = 1. – But once Qnext becomes 1, the outputs will stop

changing. This is a stable state.• Resetting the latch:

– If S = 0, R = 1. Qnext = 1 � Qnext = 0– This is how you reset or clear the latch to 0, R means "Reset“– Again it can take up to two steps (two gate delays) from the time R becomes 1 to the time Qnext = 0. – But once Qnext becomes 0, the outputs will stop changing. This is also a stable state.

• Timing considerations:– Assume initially Q=0, Q‘=1. Input SR=10.– As S=1, Q‘ will change from 1 to 0 after one NOR-gate delay (vertical lines in the figure)– This change in Q‘, along with R=0, causes Q to become 1 after another gate delay– The latch then stablizes until S or R changes again– You have to think about time-critical issue in computing: e.g., signals arrive at some time, while the logic takes

some time to react�Difficult to control timing in a large circuit.

SR latch with control input

• Here is an SR latch with control input C, or so-called GatedSR latch. C behaves like an enabler: Outputs change (if necessary) only when C is HIGH.

• Drawback of S-R latch: invalid condition exists and must be avoided.

D latch

• a D latch is based on an S'R' latch and additional gates, together with inputs D and C– When C = 0, S‘ and R‘ are both 1, so Q doesn‘t change– When C = 1, then Q = D (if D=1, latch is set; otherwise is reset)

• Features:– If C=0, Q ‘follows’ the D (data) input.– It only needs one input (C) for resetting– No "invalid“ input combinations

Latch Circuits: Not Suitable

� Latch circuits are not suitable in synchronous logic circuits.

� When the enable signal is active, the excitation inputs are gated directly to the output Q. Thus, any change in the excitation input immediately causes a change in the latch output.

� The problem is solved by using a special timing control signal called a clock to restrict the times at which the states of the memory elements may change.

� This leads us to the edge-triggered memory elements called flip-flops.

Edge-Triggered Flip-flops� Flip-flops: synchronous bistable devices

– Syncronous: output changes state only when the clock input istriggered. i.e., changes in the output occur in syncronization withthe clock.

– Bistable: there are two stable states. It is able to retain the twostates (SET and RESET) indefinitely.

� Output changes state at a specified point on a triggering input called the clock.

� Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock signal.

Positive edges Negative edges

Clock signal

Edge-Triggered Flip-flops

� S-R, D and J-K edge-triggered flip-flops. Note the “>” symbol at the clock input.

Positive edge-triggered flip-flops

Negative edge-triggered flip-flops

S-R Flip-flop

� S-R flip-flop: on the triggering edge of the clock pulse,� S=HIGH (and R=LOW) � SET state� R=HIGH (and S=LOW) � RESET state� both inputs LOW � no change� both inputs HIGH � invalid

� Characteristic table of positive edge-triggered S-R flip-flop:

X = irrelevant (“don’t care”)↑↑↑↑ = clock transition LOW to HIGH

S R CLK Q(t+1) Comments

0 0 X Q(t) No change0 1 ↑↑↑↑ 0 Reset1 0 ↑↑↑↑ 1 Set1 1 ↑↑↑↑ ? Invalid

S-R Flip-flop

� It comprises 3 parts:�a basic NAND latch�a pulse-steering circuit�a pulse transition detector (or edge detector)

circuit

� The pulse transition detector detects a rising (or falling) edge and produces a very short-duration spike.

S-R Flip-flop

The pulse transition detector. S

Pulse transition detector

Positive-going transition(rising edge)

CLKCLK'

Negative-going transition(falling edge)

CLKCLK'

D Flip-flop

� D flip-flop: single input D (data)� D=HIGH � SET state� D=LOW � RESET state

� Q follows D at the clock edge.

� Convert S-R flip-flop into a D flip-flop: add an inverter.

A positive edge-triggered D flip-flop formed with an S-R flip-flop.

D D CLK Q(t+1) Comments

1 ↑↑↑↑ 1 Set0 ↑↑↑↑ 0 Reset

↑↑↑↑ = clock transition LOW to HIGH

D Flip-flop

� Application: Parallel data transfer.To transfer logic-circuit outputs X, Y, Z to flip-flops Q1, Q2 and Q3 for storage.

* After occurrence of negative-going transition

Q1 = X*D

Q2 = Y*D

Q3 = Z*D

Combinational logic circuit

Transfer

J-K Flip-flop

� J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND gates.

� No invalid state.

� Include a toggle state.�J=HIGH (and K=LOW) � SET state�K=HIGH (and J=LOW) � RESET state�both inputs LOW � no change�both inputs HIGH � toggle

J-K Flip-flop

� J-K flip-flop.

� Characteristic table.

CLKPulse

transition detector

J K CLK Q(t+1) Comments

0 0 ↑↑↑↑ Q(t) No change0 1 ↑↑↑↑ 0 Reset1 0 ↑↑↑↑ 1 Set1 1 ↑↑↑↑ Q(t)' Toggle

Q J K Q(t+1)

0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 0

Q(t+1) = J.Q' + K'.Q

Asynchronous Inputs

� S-R, D and J-K inputs are synchronous inputs, as data on these inputs are transferred to the flip-flop’s output only on the triggered edge of the clock pulse.

� Asynchronous inputs affect the state of the flip-flop independent of the clock; example: preset (PRE) and clear (CLR) [or direct set (SD) and direct reset (RD)]

� When PRE=HIGH, Q is immediately set to HIGH.� When CLR=HIGH, Q is immediately cleared to LOW.� Flip-flop in normal operation mode when both PRE

and CLR are LOW.

Asynchronous Inputs

� A J-K flip-flop with active-LOW preset and clear inputs.

Pulse transition detector

QPreset Toggle ClearJ = K = HIGH

Flip-flop Characteristic Tables

� Each type of flip-flop has its own behavior. The characteristic tables for the various types of flip-flops are shown below:

S R Q(t+1) Comments

0 0 Q(t) No change0 1 0 Reset1 0 1 Set1 1 ? Unpredictable

J K Q(t+1) Comments

0 0 Q(t) No change0 1 0 Reset1 0 1 Set1 1 Q(t)' Toggle

T Q(t+1)

0 Q(t) No change1 Q(t)' Toggle

D Q(t+1)

0 0 Reset1 1 Set

JK Flip-flop SR Flip-flop

D Flip-flop T Flip-flop

Sequential Circuit Analysis

� Given a sequential circuit diagram, analyze its behaviour by deriving its state table and hence its state diagram.

� Requires state equations to be derived for the flip-flop inputs, as well as output functions for the circuit outputs other than the flip-flops (if any).

� We use A(t) and A(t+1) to represent the present state and next state, respectively, of a flip-flop represented by A.

� Alternatively, we could simply use A and A+ for the present state and next state respectively.

� Example (using D flip-flops):

State equations:A+ = A.x + B.xB+ = A'.x

Output function:y = (A + B).x'

Figure 1.

� From the state equations and output function, we derive the state table, consisting of all possible binary combinations of present states and inputs.

� State table�Similar to truth table.� Inputs and present state on the left side.�Outputs and next state on the right side.

� m flip-flops and n inputs → 2m+n rows.

� State table for the circuit of Figure 1:State equations:A+ = A.x + B.xB+ = A'.x

Output function:y = (A + B).x'

Present NextState Input State OutputA B x A+ B+ y0 0 0 0 0 00 0 1 0 1 00 1 0 0 0 10 1 1 1 1 01 0 0 0 0 11 0 1 1 0 01 1 0 0 0 11 1 1 1 0 0

� Alternate form of state table:Present Next

State Input State OutputA B x A+ B+ y0 0 0 0 0 00 0 1 0 1 00 1 0 0 0 10 1 1 1 1 01 0 0 0 0 11 0 1 1 0 01 1 0 0 0 11 1 1 1 0 0

Present Next State OutputState x=0 x=1 x=0 x=1AB A+B+ A+B+ y y00 00 01 0 001 00 11 1 010 00 10 1 011 00 10 1 0

� From the state table, we can draw the state diagram.

� State diagram� Each state is denoted by a circle.� Each arrow (between two circles) denotes a transition of the

sequential circuit (a row in state table).� A label of the form a/b is attached to each arrow where a

denotes the inputs while b denotes the outputs of the circuit in that transition.

� Each combination of the flip-flop values represents a state. Hence, m flip-flops → up to 2m states.

� State diagram of the circuit of Figure 1:Present Next State Output

State x=0 x=1 x=0 x=1AB A+B+ A+B+ y y00 00 01 0 001 00 11 1 010 00 10 1 011 00 10 1 0 00

0/10/0

1/0 0/1

Flip-flop Input Functions

� The outputs of a sequential circuit are functions of the present states of the flip-flops and the inputs. These are described algebraically by the circuit output functions.� In Figure 1: y = (A + B).x'

� The part of the circuit that generates inputs to the flip-flops are described algebraically by the flip-flop input functions (or flip-flop input equations).

� The flip-flop input functions determine the next state generation.

� From the flip-flop input functions and the characteristic tables of the flip-flops, we obtain the next states of the flip-flops.

� Example: circuit with a JK flip-flop.

� We use 2 letters to denote each flip-flop input: the first letter denotes the input of the flip-flop (J or K for JK flip-flop, S or R for SR flip-flop, D for D flip-flop, Tfor T flip-flop) and the second letter denotes the name of the flip-flop.

JA = B.C'.x + B'.C.x’KA = B + y

� In Figure 1, we obtain the following state equations by observing that Q+ = DQ for a D flip-flop:

A+ = A.x + B.x (since DA = A.x + B.x)B+ = A'.x (since DB = A'.x)

Figure 1.

Analysis: Example #2

� Given Figure 2, a sequential circuit with two JK flip-flops A and B, and one input x.

� Obtain the flip-flop input functions from the circuit:JA = B JB = x'KA = B.x' KB = A'.x + A.x' = A NOR x

Q'KFigure 2.

� Flip-flop input functions:JA = B JB = x'KA = B.x' JB = A'.x + A.x' = A NOR x

� Fill the state table using the above functions, knowing the characteristics of the flip-flops used.

Present Nextstate Input state Flip-flop inputs

A B x A+ B+ JA KA JB KB0 0 0 0 0 1 00 0 1 0 0 0 10 1 0 1 1 1 00 1 1 1 0 0 11 0 0 0 0 1 11 0 1 0 0 0 01 1 0 1 1 1 11 1 1 1 0 0 0

0 10 01 11 01 11 00 01 1

J K Q(t+1) Comments

0 0 Q(t) No change0 1 0 Reset1 0 1 Set1 1 Q(t)' Toggle

� Draw the state diagram from the state table.Present Next

state Input state Flip-flop inputsA B x A+ B+ JA KA JB KB0 0 0 0 1 0 0 1 00 0 1 0 0 0 0 0 10 1 0 1 1 1 1 1 00 1 1 1 0 1 0 0 11 0 0 1 1 0 0 1 11 0 1 1 0 0 0 0 01 1 0 0 0 1 1 1 11 1 1 1 1 1 0 0 0

Sequential Circuit Design

� Design procedure:� Start with circuit specifications – description of circuit

behaviour.� Derive the state table.� Perform state reduction if necessary.� Perform state assignment.� Determine number of flip-flops and label them.� Choose the type of flip-flop to be used.� Derive circuit output tables from the state table.� Derive circuit output functions and flip-flop input functions.� Draw the logic diagram.

Design Example

� Given the following state diagram, design the sequential circuit using JK flip-flops.

Design Example

� Circuit state table, using JK flip-flops.

Present Next StateState x=0 x=1AB A+B+ A+B+

00 00 0101 10 0110 10 1111 11 00

Present Nextstate Input state Flip-flop inputs

A B x A+ B+ JA KA JB KB0 0 0 0 00 0 1 0 10 1 0 1 00 1 1 0 11 0 0 1 01 0 1 1 11 1 0 1 11 1 1 0 0

0 X0 X1 X0 XX 0X 0X 0X 1

0 X1 XX 1X 00 X1 XX 0X 1

Design Example

� From state table, get flip-flop input functions.Present Next

state Input state Flip-flop inputsA B x A+ B+ JA KA JB KB0 0 0 0 0 0 X 0 X0 0 1 0 1 0 X 1 X0 1 0 1 0 1 X X 10 1 1 0 1 0 X X 01 0 0 1 0 X 0 0 X1 0 1 1 1 X 0 1 X1 1 0 1 1 X 0 X 01 1 1 0 0 X 1 X 1

00 01 11 10

X X X X

JA = B.x'

JB = x

00 01 11 10

KA = B.x

00 01 11 10

KB = (A ⊕⊕⊕⊕ x)'

00 01 11 10

Design Example

� Flip-flop input functions.JA = B.x' JB = xKA = B.x KB = (A ⊕ x)'

� Logic diagram:

Summary

� Sequential circuits can be used to build memories and they are more powerful than combinational circuits.

� Analyzing sequential circuits� Flip-flop characteristic table� State Table� State diagram

� Designing sequential circuits� Flip-flop state table� Circuit output function� Flip-flop input function

Telematics group -...

Documents

Transcript of Telematics group -...

- Binary Number Systems - Hexadecimal Code - Binary …e-book.ram.edu/e-book/c/CT455/ct455-2.pdf · - Binary Number Systems - Hexadecimal Code - Binary Codes - Binary Arithmetic -

Optimized FMIPv6 Using IEEE 802.21 MIH Services in ...user.informatik.uni-goettingen.de/~fu/pub/ieee-tvt07_MIH.pdf · mussabbir etal.: optimized fmipv6 using ieee 802.21 mih services

Binary Conversions Number systems Binary to decimal Decimal to binary.

Detecting Malicious Accounts in Online Developer ...user.informatik.uni-goettingen.de/~ychen/papers/GitSec...Detecting Malicious Accounts in Online Developer Communities Using Deep

Computational Rumor Detection Without Non …user.informatik.uni-goettingen.de/~ychen/papers/Rumor...830 IEEE TRANSACTIONS ON COMPUTATIONAL SOCIAL SYSTEMS, VOL. 6, NO. 5, OCTOBER 2019

Modeling and Discovering Vulnerabilities with Code ...user.informatik.uni-goettingen.de/~krieck/docs/2014-ieeesp.pdf · capabilities of code property graphs in practice. In summary,

Binary Decision Diagrams1 BINARY DECISION DIAGRAMS.

MATLAB Spring18 02 - user.informatik.uni-goettingen.deuser.informatik.uni-goettingen.de/~ychen/MATLAB/MATLAB_Spring18_02.pdf · 23.2995 24.4205 25.5955 26.8270 28.1177 29.4705 30.8884

The Power of Comments: Fostering Social Interactions in ...user.informatik.uni-goettingen.de/~ychen/papers/Weibo_FCS16.pdf · analysis of the Sina Weibo microblogging service. Often

Securing IMS against Novel Threats - uni-goettingen.deuser.informatik.uni-goettingen.de/~krieck/docs/2009-bltj.… · · 2015-02-14Securing IMS against Novel Threats Stefan Wahl1,

Career MLM Software, Binary Plan Software, Binary Software, Binary Marketin...

Binary Stars. Double Stars/Binary Stars Binary Star Double Star Earth.

1 Binary Trees Binary Trees Binary Search Trees Binary Search Trees CSE 30331 Lecture 13 –Trees.

Binary Trees, Binary Search Trees - Drexel CCIamd435/courses/cs260/lectures/L-5_BST... · Binary Trees, Binary Search Trees huamin/ COMP171/bst.ppt. ... • Will not be a binary tree

Understanding the Behavioral Differences Between American ...user.informatik.uni-goettingen.de/~ychen/papers/Yelp_BDMA18.pdf · Europe, understanding the behavioral differences between

SnapTask: Towards Efficient Visual Crowdsourcing for Indoor …user.informatik.uni-goettingen.de/~ychen/papers/SnapTask... · 2018. 12. 18. · for Indoor Mapping Marius Noreikis

Binary Search and Binary Tree Binary Search Heap Binary Tree.

Technical Report IFI-TB-2013-02 - uni-goettingen.deuser.informatik.uni-goettingen.de/~krieck/docs/2013-drebin.pdf · Technical Report IFI-TB-2013-02 ... DroidRanger [31] and DroidScope

Binary Numbers 1. Outcome Familiar with the binary system Binary to Decimal and decimal to binary Adding two binary sequences Logic gates Hexadecimal.

A Methodology for Analyzing the Performance of ...user.informatik.uni-goettingen.de/~fu/ptls/p458-harbitter.pdf · plication of the methodology to protocol design issues: Kerberos