Post on 20-Jun-2019
September 12, 2005 1
SVTSVT UPGRADE STATUSP. Giannetti for the SVT Upgrade group
July 21 2005: first AM++ & AMSRW
Inside SVT
The SVT team at work in Trigger room (90% italian)
September 12, 2005 2
SVTOUTLINE
• What is the SVTupgrade
• Why it is important
• Many upgrade steps at Fermilab: no shutdownwhat has been done what has to be done
• After the hardware installation algorithm optimization
Short description
September 12, 2005 3
SVTSVT: Silicon Vertex Trigger
XFT tracksSVX hits
Finding tracks in the silicon
September 12, 2005 4
SVT
TsukubaChicagoFermilab
Chicago
Pisa1st Pulsar:
Sequencer & Road Warrior
Associative Memory 512 kpatterns
2nd Pulsar:Hit Buffer
3nd Pulsar:Track Fitter
September 12, 2005 5
SVTLarge Impact on Upgrade from Italy (~20 names)
Project Leader: Alberto AnnoviAMchip03 project: Sartori, Tripiccione, Pedron, Schifano (FE)
validation, test: Annovi, Dell’Orso, Giovacchini (PI)AM++ - LAMB Bardi, Giannetti (PI)RW Belforte, Carosi, Catastini, Spinella (TS-PI-SI)AMSRW Bitossi, Giannetti, Piendibene, Spinella (PI)Software svtvme: Annovi, Giovacchini (PI)
monitoring-configuration: Carosi, Simoni, Volpi (PI)simulation: Annovi, Cerri, Simoni, Torre(PI-LBL-SI)spymon: Di Ruzza, Rescigno(RO)
Tests: Annovi, Giovacchini, TorreInstallazione: Annovi, Dell’Orso, Giannetti, Giovacchini,
Piendibene (PI), Torre (SI), Di Ruzza, Rescigno (RO)USA: Adelman (TF++), Bellinger (software), Chappa (HB),
Furic(HB), Maruyama (HB), Tang (mezz.), Shochet(mezz.)
September 12, 2005 6
SVTTEMPI DI REALIZZAZIONE2003 Schedule
• Nuova AM-board: inizio estate 2004 (Pisa)durante estate 2004: test con FPGA (Pisa)
• Progetto prototipo AM-chip: luglio 2004 (Ferrara-Pisa)consegna chip ~2 mesi – disponibile ad ottobre.
• Nuova LAMB: montare nuovo AM-chip a ottobre 2004 (Pisa)
• test del chip + scheda: ottobre – dicembre 2004 (Pisa-Ferrara)
• produzione: inizio 2005 (Pisa-Ferrara)• installazione: estate 2005 (Pisa-Ferrara)• Altri DAQ/Trigger upgrade: previsti nel 2006
Road Warrior: . . . (~60 k$ Fermilab)messa in opera entro fine 2003
September 12, 2005 7
SVTL1 accept rate is bottle neck
•L1A rate ~ 20 kHz (vs 50kHz design)•L1A rate limited by L2 exec timeRates at @ L=100E30 (current luminosity):~15kHz high Pt L1A~15kHz TTT L1A (now PS = 2)Rates growing quadratically with luminosity
Level 2 pipeline structure:
Siliconreadout
SVTprocessing
L2 decisionprocessing
Optimized but slower than
design
Upgrade in progress
Upgrade in progress
SVT upgrade has large impact on maximum L1A rate!
September 12, 2005 9
SVTSVT before July
SVT00Tracking
SVT01Tracking
SVT074 Road
Warrior
SVT02Tracking
SVT06Final MRG
GB
SVT03Tracking
SVT05Tracking
SVT04Tracking
cablesSVT088 Road
Warrior
Need extra crate
8
8
AMB
AMB
AMS
MERGER
HF
HF
HF
HB
TF
AMB
AMB
AMS
MERGER
HF
HF
HF
HB
TF
SVT tracking crate
(2 wedges)RW
RW
September 12, 2005 10
SVTFinal configuration
SVT00Tracking
SVT01Tracking
SVT074 Hit
buffer
SVT02Tracking
SVT062 Hit
buffer
SVT03Tracking
SVT05Tracking
SVT04Tracking
SVT098 Track fitter
SVT08Final MRGGB 4 TF
AM++
AM++
newHB
cables
AMBUS slots
toLVL2
1
12
SVTtracking
crate(2 wedges)
AMS/RW
M
R
MERGER
AMS/RW
newHB
newTF
newTF
ERGE
AM++
AM++
HF
HF
HF
HF
HF
HF
September 12, 2005 11
SVTUpgrade stepsReal data
Board/software Validation (step # 0)• Boards will be first tested in the test stand• Then they will be tested parasitically
with real data• Need few slots in a test stand placed near SVT
Hardware installation in 3 steps: 1. AMS/RW and AM++ inside SVT (July 29)2. TF++ installed in ex-Road Warrior Pulsars → 128 kpat3. Install finally HB and 2nd AM++ board → 512 kpat
Study of performances – firmware optimization (4th step - 06)Other hardware improvements?? (5th step – after 06.. may be)
We are here
September 12, 2005 12
SVTJuly: AM++ installation (1st step)
• AMS/RW + one AM++ board have been installed with minimal impact
AMB
AMB
AMS
MERGER
HF
HF
HF
HB
TF
AMS/RW
AM++
MERGER
HF
HF
HF
HB
TF
• Compatible with old boards (can work with 32k patterns)• Minimal re-cabling and reconfiguration
Gain: 2 µsec reduction on average SVT processing time@Lum=[78-25]*1030 due to RW moved before the HB.
September 12, 2005 13
SVTAugust: Track Fitter installation (2nd step)
After RW has been replaced by AMS/RW.Just reprogram the 12 RW boards with TF firmware
2- 3 µsec gain at Lum=[91-81] *1030
<T>=25.1 µsec <T>=22.8 µsec
September 12, 2005 14
SVTSVT timing w/TF++
TF++ Run w/TF last week
(Similar luminosities ~85)
RMS=18
RMS=10.7
As expected, core of timing stays the same, but significantly reduced tails (look at RMS)
September 12, 2005 15
SVTTF++ impact on L1 bandwidth
TF++ EFFECT
0
1
2
3
4
5
6
7
8
9
10
15000 17000 19000 21000 23000 25000 27000 29000
L1A RATE
DEA
D
TIM
E
Blue-red TF++ Lum=100-55
Brown-light BlueoldTF Lum=130-100
Brown-light BlueoldTF Lum=100-63
YellowoldTF Lum=118-100
White TF++ Lum=80-45
5% deadtime
September 12, 2005 16
SVT128 kpatterns vs 32 kpatterns (fakehits)E
ntr
ies
648
69M
ean
1
7.83
RM
S
9.2
64U
nd
erfl
ow
0
Ove
rflo
w
0
SV
T p
roc.
tim
e (1
ms
ran
ge)
(u
s)0
5010
015
020
025
030
0
Event Count
210
310
410
En
trie
s 7
6795
Mea
n
17.
84R
MS
9
.259
Un
der
flo
w
0O
verf
low
0
FR
OM
GB
bo
ard
Ru
n N
um
ber
= 2
0370
9 L
ast
Up
dat
ed a
t =
2005
/09/
02 1
4:23
:55
En
trie
s 2
1131
3M
ean
2
0.73
RM
S
12.
81U
nd
erfl
ow
0
Ove
rflo
w
0
SV
T p
roc.
tim
e (1
ms
ran
ge)
(u
s)0
5010
015
020
025
030
0
Event Count
10
210
310
410
En
trie
s 2
2318
2M
ean
2
0.71
RM
S
12
.8U
nd
erfl
ow
0
Ove
rflo
w
0
FR
OM
GB
bo
ard
Ru
n N
um
ber
= 2
0331
4 L
ast
Up
dat
ed a
t =
2005
/08/
26 1
1:25
:08
<T>=17.84 RMS=9.26 <T>=20.7 RMS=12.8
September 12, 2005 17
SVTNovember: HB + AM++ enlargement (3rd step)
Status after new HB
installation
AM++
AM++
newHB
AMBUS slots
AM++
AM++
AMS/RW
HF
HF
HF
AMS/RW
HF
HF
HF
newTF
M
R
MERGER
ERGE
newHB
newTF
Final configuration
512 kpat/wedge
newTF
newTF
MERGER
AM++
HF
HF
HF
newHB
MERGER
AM++
HF
HF
HF
AMS/RW
AMS/RW
empty
newHB
September 12, 2005 18
SVT2006:better Timing → better algorithm (4rd step)
0.1
0.6 x6x3
Increasing luminosity→ Low SVT
Background rejection
ScenA: Two_TRK2_Oppq_Dphi135_Sumpt5.5
x2
September 12, 2005 19
SVTAlso Scenario C shows exactly same problem
x6
x3
ScenC: Two_TRK2.5_Oppq_Dphi135_Sumpt6.5
x2
September 12, 2005 20
SVTFirst very good idea: veto events with a large number of interactions
MORE SVT studies:1) Limited # fits per road2) Adjust Chi**2 cut3) Adjust Hit Finder THRs4) Use new XFT infos (z?)5) Adjust L2 processor
algorithms
September 12, 2005 21
SVTHOW to fill the available L1 bandwidth (step 4)??New Trigger Table
TF++ EFFECT
0
1
2
3
4
5
6
7
8
9
10
15000 17000 19000 21000 23000 25000 27000 29000 31000
L1A RATE Hz
DEA
D
TIM
E %
Green-white-black TF++ Lum=120-55
Brown-light BlueoldTF Lum=130-100
Brown-light BlueoldTF Lum=100-63Yellow
oldTF Lum=118-100
Pink TF++ Lum=80-45
Pink TF++ Lum=45-28
25kHz
10 % dead time
A lot of discussion!!
September 12, 2005 22
SVTConclusion
• Parasitic tests of all boards before installation
• AMS/RW, AM++ and TF have been installed before the shutdown (July- August)
• Complete the upgrade (November 2005)
• A) Optimize Track finding: XFT-SVT-L2processorsB) Fill L1 rate as much as possible (2006)
• May be after 2006….GigaFitter (R&D proposed to Murst.)? More AM??
DONE
To be DONE
September 12, 2005 25
SVT
Level 2• Asynchronous 3 Stage Pipeline• 20 µs Latency• 300 Hz accept rate
DetectorRaw Data
L1Accept
Level 2Trigger
Level 2 buffer:
4 events
L2Accept
Level 1•7.6 MHz Synchromous Pipeline•5544 ns Latency•50 KHz accept rate
7.6 MHz Crossing rate
Level 1Trigger
•50 kHz accept rate
• 20 µs average Latency
~20 kHz actual
~35 µs actual
CDF DAQ & Trigger
Level 1
pipeline:
42 clock
cycles
SVT here
DAQ buffers
L3 Farm To Mass Storage (50~100 Hz)
Tails are important
September 12, 2005 26
SVTYear chip boards devel. Total
2003? 120 kE 10 kE (test b.) 5 kE 135 kE
2004 Ferrara 10 kE (protot.) 30 kE 40 kE
2005 53 kE 100 kE (produc.) 153 k+40 kE +40 kE+50 kE +50 kE
+60 kE (MURST)
PisaLe Pulsar sono pagate dagli USAtotale secondo upgrade 310k$
September 12, 2005 27
SVTAM++ board (Pisa)
• Standard cell AMchip prototype working >40MHz– Production received: evaluating yield
• LAMB and AM++ vme board:– 3nd prototype build and tested– Need final test w/ board full of AMchips
• Building a 4th AM++ vme board prototype– fix minor issues– Production available by June
• ON SCHEDULE
September 12, 2005 28
SVTAMS/RW status (Pisa)
• AMS and RW firmware implemented and tested
• next step implement SVT firmware tools
• ON SCHEDULE
Pisa had the most risky responsibilities,but we are now in very good shape
September 12, 2005 29
SVTNon italian responsabilities
• Pulsars – Pulsar production arrived– Large RAM mezzanine production done– Small RAM mezzanine prototype under test– ON SCHEDULE
• TF– First firmware written– Standalone tests starting– ON SCHEDULE
• HB– Firmware writing just started
– BEHIND SCHEDULE– More man power (firmware engineer joined)
September 12, 2005 30
SVTSoftware and integration
• SOFTWARE– Work in progress
– Critical part for test and installation
– BEHIND SCHEDULE
– project reorganized after internal review• 4 main blocks identified
• coordinators assigned: R. Carosi, A. Annovi, A. Cerri, M. Rescigno
– Additional man power (w.r.t. baseline) mostly Pisa people
– CAN RECOVER
• INTEGRATION– Vertical slice parasitic test begun
with AM++ and AMS/RW
– Add boards as they become available
Real data
September 12, 2005 31
SVTInstallation plan• Fermilab goal was to install during the shutdown
• Shutdown postponed to October (at least)
• Plan to install 128kpatterns per wedge by July/August
• Installing also new TF (as soon as it is ready)
• Take advantage, as soon as possible, of• better AM resolution• RW function moved before HB• faster TF