Post on 13-Jan-2016
S.Veneziano – INFN Roma July 2003 TDAQ week
CMA LVL1 Barrel status
ATLAS TDAQ weekJuly 2003
S.Veneziano – INFN Roma July 2003 TDAQ week
History
• CMA ASIC submitted 20th November 2001• 49 dies packaged by March 15th with
four-pin bonding following preliminary specs (package 0208).New wafers had to selected for packaging with final Bonding.
• Loadboard arrived 10th March to test site (Milano), following specifications (package 0219), had to be fixed to package 0208.
• Industry tests started 21st March on 49 packages 0208 with scan tests.
S.Veneziano – INFN Roma July 2003 TDAQ week
History 2
• 7th April functional tests sent by Rome to industry
• 15th April 5 0208 tested devices (no RAM tests) and loadboard sent to Rome.
• 20th April RAM test vectors sent by Rome to industry.
• 29th April 44 fully tested 0208 package devices at Microtech.
• 23rd May 37 devices with package 0219 tested at Microtech.
S.Veneziano – INFN Roma July 2003 TDAQ week
CM ASIC layout and architecture
• 430 kgates UMC 0.18 m, 320 MHz PLL (X8), 24 double-port RAMs.
S.Veneziano – INFN Roma July 2003 TDAQ week
CMA ASIC pinout
• Package 0208 and 0219 differ only on the position of PLL signals and supplies. Both of them are working correctly
S.Veneziano – INFN Roma July 2003 TDAQ week
CMA Loadboard
• Loadboard developped for Teradyne tester, has been designed with additional connectors for PLL test and lab tests in Rome.
S.Veneziano – INFN Roma July 2003 TDAQ week
Test patterns
• Scan and functional tests were performed on Teradyne machine at 1 Mhz, 40 Mhz, at room and at 125C temperatures. PLL lock was also tested.– SCAN tests: 32 scan chains, maximum of 900
cells, generated with Synopsys Test Compiler.– RAM tests: using single dedicated scan chain
(23,743,440 cycles), generated from RTL model adn converted to compressed ATP format.
– Functional tests 105576 vectors, to test I2C interface and start PLL, generated from full netlist+timing simulation, converted to ATP format.
S.Veneziano – INFN Roma July 2003 TDAQ week
Industrial test results• 49 0208 packages tested:
– 7 failing on GND– 1 RAM fail– 1 SCAN fail– 40 OK (81.6% yield)
• 37 1219 packages tested:– No GND fails (already discarded?)– 4 RAM fails– 3 SCAN fails– 30 OK (81.1% yield)
• 70 ASICs good, to be used for further tests and irradiation.
S.Veneziano – INFN Roma July 2003 TDAQ week
LAB setup36x64K T=6.125nsPattern generator
Clock jitter
WaveformAnalyser T=10ns
GeneratorPODs
GPIBLAN
loadboard
I2C on RJ45
S.Veneziano – INFN Roma July 2003 TDAQ week
Tests done in Rome
• LAB setup with limited capability has been used to do preliminary tests.– I2C on parallel port interface and C++
linux application has been used to initialize ASIC on all tests shown here.
• Four CM ASICs mounted on CM boards will be used for further tests.
S.Veneziano – INFN Roma July 2003 TDAQ week
PLL tests
• 160 MHz derived clock output has been used to check PLL stability (320 MHz)
40 MHz input
160 MHz on dedicated IO
S.Veneziano – INFN Roma July 2003 TDAQ week
PLL tests 2
• PLL has been characterized vs V and vs input Frequency.
• PLL is working to specifications
S.Veneziano – INFN Roma July 2003 TDAQ week
PLL vs Voltage
PLL jitter
020406080
100120140160180
1.5 1.6 1.7 1.8 1.9
Vdd [V]
Jitt
er
[ps]
Pk-Pkstd. dev.
S.Veneziano – INFN Roma July 2003 TDAQ week
PLL vs frequency
PLL jitter
0
100
200
300
400
500
600
10 20 30 40 50
Input clock [MHz]
Jitt
er
[ps]
Pk-Pkstd. dev.
S.Veneziano – INFN Roma July 2003 TDAQ week
Trigger tests
• Trigger tests have been done so far on a limited number of input channels, due to limitations on the laboratory setup.– Minimum pulse width measurement
• Twmin > 6.126 ns (12 ns in specs)
• Dead timer, pulse shaping and pipeline delay working according to specs.
S.Veneziano – INFN Roma July 2003 TDAQ week
Trigger output latency
• Input to K-pattern delay– Tlatkpat = 59 +- 1 ns
• Input to THReshold/OVerLap delay– Tlatthr = 63-88 +-1 ns
• Skew between THR and OVL signals – Toutskew = 2 +- 0.5 ns.
S.Veneziano – INFN Roma July 2003 TDAQ week
Readout tests• Readout link is a two-wire Dslink protocol
working at 80-40-20-10-5-2.5-1.125 Mbit/s• Readout tests done at 40 Mbit/s using:
– 10ns period sampling with waveform analyser– GPIB LAN box connected to waveform analyser
CMID L1ID
… BCID + 16-bit hits …
8-bitCRC
S.Veneziano – INFN Roma July 2003 TDAQ week
Readout tests 2
• VISA-GPIB library (linux) in deserializer program has been used to convert waveform vectors to readout data fragments.
c151 -- CMID 0 FEL1ID 33787d8 -- FEBCID 20080700 -- BC 0 TIME 7 IJK 0 STRIP 00745 -- BC 0 TIME 7 IJK 2 STRIP 50685 -- BC 0 TIME 6 IJK 4 STRIP 507c0 -- BC 0 TIME 7 IJK 6 STRIP 007e3 -- BC 0 TIME 7 OVL 0 THR 34075 -- CRC 75
S.Veneziano – INFN Roma July 2003 TDAQ week
Time interpolator linearity
• Hits on four channels have been generated, in 1 ns steps, within a range of 4 BCs (CH 1-4), also trigger output time is measured (K).
10
18
26
34
42
50
0 25 50 75 100
delay [ns]
tim
e s
lot
CH 0
CH 1
CH 2
CH 3
K
Very preliminary
S.Veneziano – INFN Roma July 2003 TDAQ week
0.00
100.00
200.00
300.00
400.00
500.00
600.00
700.00
800.00
0 2 4 6 8 10 12 14 16 18hits
ma
x L
VL
1 f
req
ue
nc
y (
kH
z) LVl1 max f (kHz) 40Mbit/s
LVl1 max f (kHz) 80Mbit/s
Readout latency
• Max LVL1 input frequency.
1% RPC occupancy1-BC window
S.Veneziano – INFN Roma July 2003 TDAQ week
Power vs voltage
Power consumption vs. voltage
0.55
0.60
0.65
0.70
0.75
0.80
1.50 1.60 1.70 1.80 1.90
Vdd [V]
I [m
A]
S.Veneziano – INFN Roma July 2003 TDAQ week
Power vs frequency
Power consumption vs. clock frequency
0
100
200
300
400
500
600
700
800
900
2.5 12.5 22.5 32.5 42.5
freq. [MHz]
I [m
A]
S.Veneziano – INFN Roma July 2003 TDAQ week
CM board Eta
• PCBs to be mounted on PAD prototype are ready
RJ45(from splitters)
PAD Motherboardconnections
LVDSreceivers
CMA
S.Veneziano – INFN Roma July 2003 TDAQ week
CM board Phi
• Four ASICs mounted on two eta and two phi boards by June 21st.
FE receivers
RN connectors(from wired-OR)
CMA