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TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232Digital Signal Controllers (DSCs)
Data Manual
PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
Literature Number: SPRS439HJune 2007Revised March 2010
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232SPRS439HJUNE 2007REVISED MARCH 2010 www.ti.com
Contents1 TMS320F2833x, TMS320F2823x DSCs .................................................................................. 11
1.1 Features .................................................................................................................... 111.2 Getting Started ............................................................................................................. 12
2 Introduction ...................................................................................................................... 132.1 Pin Assignments ........................................................................................................... 152.2 Signal Descriptions ........................................................................................................ 24
3 Functional Overview .......................................................................................................... 343.1 Memory Maps .............................................................................................................. 353.2 Brief Descriptions .......................................................................................................... 42
3.2.1 C28x CPU ....................................................................................................... 423.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 423.2.3 Peripheral Bus .................................................................................................. 423.2.4 Real-Time JTAG and Analysis ................................................................................ 433.2.5 External Interface (XINTF) .................................................................................... 433.2.6 Flash ............................................................................................................. 433.2.7 M0, M1 SARAMs ............................................................................................... 433.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs ..................................................................... 443.2.9 Boot ROM ....................................................................................................... 443.2.10 Security .......................................................................................................... 443.2.11 Peripheral Interrupt Expansion (PIE) Block ................................................................. 463.2.12 External Interrupts (XINT1XINT7, XNMI) .................................................................. 463.2.13 Oscillator and PLL .............................................................................................. 463.2.14 Watchdog ........................................................................................................ 463.2.15 Peripheral Clocking ............................................................................................. 463.2.16 Low-Power Modes .............................................................................................. 463.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 473.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 473.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 473.2.20 Control Peripherals ............................................................................................. 483.2.21 Serial Port Peripherals ......................................................................................... 48
3.3 Register Map ............................................................................................................... 493.4 Device Emulation Registers .............................................................................................. 513.5 Interrupts .................................................................................................................... 52
3.5.1 External Interrupts .............................................................................................. 563.6 System Control ............................................................................................................ 57
3.6.1 OSC and PLL Block ............................................................................................ 583.6.1.1 External Reference Oscillator Clock Option .................................................... 593.6.1.2 PLL-Based Clock Module ......................................................................... 603.6.1.3 Loss of Input Clock ................................................................................ 61
3.6.2 Watchdog Block ................................................................................................. 623.7 Low-Power Modes Block ................................................................................................. 63
4 Peripherals ....................................................................................................................... 644.1 DMA Overview ............................................................................................................. 644.2 32-Bit CPU-Timers 0/1/2 ................................................................................................. 664.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6 ) ........................................................................ 68
2 Contents Copyright 20072010, Texas Instruments Incorporated
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439HJUNE 2007REVISED MARCH 2010
4.4 High-Resolution PWM (HRPWM) ....................................................................................... 724.5 Enhanced CAP Modules (eCAP1/2/3/4/5/6) ........................................................................... 734.6 Enhanced QEP Modules (eQEP1/2 ) ................................................................................... 754.7 Analog-to-Digital Converter (ADC) Module ............................................................................ 77
4.7.1 ADC Connections if the ADC Is Not Used .................................................................. 814.7.2 ADC Registers .................................................................................................. 824.7.3 ADC Calibration ................................................................................................. 83
4.8 Multichannel Buffered Serial Port (McBSP) Module .................................................................. 844.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) .................................... 874.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) .......................................... 924.11 Serial Peripheral Interface (SPI) Module (SPI-A ) ..................................................................... 964.12 Inter-Integrated Circuit (I2C) ............................................................................................. 994.13 GPIO MUX ................................................................................................................ 1004.14 External Interface (XINTF) .............................................................................................. 107
5 Device Support ................................................................................................................ 1095.1 Device and Development Support Tool Nomenclature ............................................................. 1095.2 Documentation Support ................................................................................................. 111
6 Electrical Specifications ................................................................................................... 1166.1 Absolute Maximum Ratings ............................................................................................. 1166.2 Recommended Operating Conditions ................................................................................. 1176.3 Electrical Characteristics ................................................................................................ 1176.4 Current Consumption .................................................................................................... 118
6.4.1 Reducing Current Consumption ............................................................................. 1206.4.2 Current Consumption Graphs ............................................................................... 1216.4.3 Thermal Design Considerations ............................................................................. 122
6.5 Emulator Connection Without Signal Buffering for the DSP ....................................................... 1236.6 Timing Parameter Symbology .......................................................................................... 124
6.6.1 General Notes on Timing Parameters ...................................................................... 1246.6.2 Test Load Circuit .............................................................................................. 1246.6.3 Device Clock Table ........................................................................................... 125
6.7 Clock Requirements and Characteristics ............................................................................. 1266.8 Power Sequencing ....................................................................................................... 127
6.8.1 Power Management and Supervisory Circuit Solutions .................................................. 1276.9 General-Purpose Input/Output (GPIO) ................................................................................ 130
6.9.1 GPIO - Output Timing ........................................................................................ 1306.9.2 GPIO - Input Timing .......................................................................................... 1316.9.3 Sampling Window Width for Input Signals ................................................................. 1326.9.4 Low-Power Mode Wakeup Timing .......................................................................... 133
6.10 Enhanced Control Peripherals ......................................................................................... 1386.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ....................................................... 1386.10.2 Trip-Zone Input Timing ....................................................................................... 1386.10.3 Enhanced Capture (eCAP) Timing ......................................................................... 1396.10.4 Enhanced Quadrature Encoder Pulse (eQEP) Timing ................................................... 1396.10.5 ADC Start-of-Conversion Timing ............................................................................ 140
6.11 External Interrupt Timing ................................................................................................ 1406.12 I2C Electrical Specification and Timing ............................................................................... 1416.13 Serial Peripheral Interface (SPI) Timing .............................................................................. 141
Copyright 20072010, Texas Instruments Incorporated Contents 3
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232SPRS439HJUNE 2007REVISED MARCH 2010 www.ti.com
6.13.1 Master Mode Timing .......................................................................................... 1416.13.2 SPI Slave Mode Timing ...................................................................................... 146
6.14 External Interface (XINTF) Timing ..................................................................................... 1496.14.1 USEREADY = 0 ............................................................................................... 1496.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) ............................................. 1506.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) ............................................ 1516.14.4 XINTF Signal Alignment to XCLKOUT ..................................................................... 1536.14.5 External Interface Read Timing ............................................................................. 1546.14.6 External Interface Write Timing ............................................................................. 1566.14.7 External Interface Ready-on-Read Timing With One External Wait State ............................ 1586.14.8 External Interface Ready-on-Write Timing With One External Wait State ............................. 1616.14.9 XHOLD and XHOLDA Timing ............................................................................... 164
6.15 On-Chip Analog-to-Digital Converter .................................................................................. 1676.15.1 ADC Power-Up Control Bit Timing .......................................................................... 1686.15.2 Definitions ...................................................................................................... 1696.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................ 1706.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .......................................... 1716.15.5 Detailed Descriptions ......................................................................................... 172
6.16 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 1736.16.1 McBSP Transmit and Receive Timing ...................................................................... 1736.16.2 McBSP as SPI Master or Slave Timing .................................................................... 176
6.17 Flash Timing .............................................................................................................. 1806.18 Migrating Between F2833x Devices and F2823x Devices ......................................................... 181
7 Revision H Revision History .............................................................................................. 1828 Revision G Revision History .............................................................................................. 1839 Thermal/Mechanical Data .................................................................................................. 186
4 Contents Copyright 20072010, Texas Instruments Incorporated
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439HJUNE 2007REVISED MARCH 2010
List of Figures2-1 F2833x, F2823x 176-Pin PGF/PTP LQFP (Top View) ...................................................................... 162-2 F2833x, F2823x 179-Ball ZHH MicroStar BGA (Upper Left Quadrant) (Bottom View) .............................. 172-3 F2833x, F2823x 179-Ball ZHH MicroStar BGA (Upper Right Quadrant) (Bottom View)............................. 182-4 F2833x, F2823x 179-Ball ZHH MicroStar BGA (Lower Left Quadrant) (Bottom View) .............................. 192-5 F2833x, F2823x 179-Ball ZHH MicroStar BGA (Lower Right Quadrant) (Bottom View)............................. 202-6 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper Left Quadrant) (Bottom View)...................................... 212-7 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper Right Quadrant) (Bottom View) .................................... 222-8 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower Left Quadrant) (Bottom View)...................................... 232-9 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower Right Quadrant) (Bottom View) .................................... 233-1 Functional Block Diagram ...................................................................................................... 343-2 F28335/F28235 Memory Map ................................................................................................. 373-3 F28334/F28234 Memory Map ................................................................................................. 383-4 F28332/F28232 Memory Map ................................................................................................. 393-5 External and PIE Interrupt Sources ............................................................................................ 533-6 External Interrupts................................................................................................................ 533-7 Multiplexing of Interrupts Using the PIE Block ............................................................................... 543-8 Clock and Reset Domains ...................................................................................................... 573-9 OSC and PLL Block Diagram................................................................................................... 583-10 Using a 3.3-V External Oscillator............................................................................................... 593-11 Using a 1.9 -V External Oscillator.............................................................................................. 593-12 Using the Internal Oscillator .................................................................................................... 593-13 Watchdog Module ................................................................................................................ 624-1 DMA Functional Block Diagram ................................................................................................ 654-2 CPU-Timers ....................................................................................................................... 664-3 CPU-Timer Interrupt Signals and Output Signal ............................................................................. 664-4 Multiple PWM Modules in an 2833x/2823x System ......................................................................... 684-5 ePWM Submodules Showing Critical Internal Signal Interconnections ................................................... 714-6 eCAP Functional Block Diagram ............................................................................................... 734-7 eQEP Functional Block Diagram ............................................................................................... 754-8 Block Diagram of the ADC Module ............................................................................................ 784-9 ADC Pin Connections With Internal Reference .............................................................................. 794-10 ADC Pin Connections With External Reference ............................................................................. 804-11 McBSP Module .................................................................................................................. 854-12 eCAN Block Diagram and Interface Circuit ................................................................................... 884-13 eCAN-A Memory Map ........................................................................................................... 894-14 eCAN-B Memory Map ........................................................................................................... 904-15 Serial Communications Interface (SCI) Module Block Diagram............................................................ 954-16 SPI Module Block Diagram (Slave Mode) .................................................................................... 984-17 I2C Peripheral Module Interfaces .............................................................................................. 994-18 GPIO MUX Block Diagram .................................................................................................... 1014-19 Qualification Using Sampling Window ....................................................................................... 1064-20 External Interface Block Diagram............................................................................................. 1074-21 Typical 16-bit Data Bus XINTF Connections................................................................................ 1084-22 Typical 32-bit Data Bus XINTF Connections................................................................................ 1085-1 Example of F2833x, F2823x Device Nomenclature........................................................................ 1106-1 Typical Operational Current Versus Frequency (F28335/F28235/F28334/F28234) ................................... 122
Copyright 20072010, Texas Instruments Incorporated List of Figures 5
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232SPRS439HJUNE 2007REVISED MARCH 2010 www.ti.com
6-2 Typical Operational Power Versus Frequency (F28335/F28235/F28334/F28234) .................................... 1226-3 Emulator Connection Without Signal Buffering for the DSP ............................................................. 1236-4 3.3-V Test Load Circuit......................................................................................................... 1246-5 Clock Timing..................................................................................................................... 1276-6 Power-on Reset ................................................................................................................. 1286-7 Warm Reset ..................................................................................................................... 1296-8 Example of Effect of Writing Into PLLCR Register ......................................................................... 1306-9 General-Purpose Output Timing .............................................................................................. 1316-10 Sampling Mode ................................................................................................................. 1316-11 General-Purpose Input Timing ................................................................................................ 1326-12 IDLE Entry and Exit Timing.................................................................................................... 1336-13 STANDBY Entry and Exit Timing Diagram .................................................................................. 1356-14 HALT Wake-Up Using GPIOn................................................................................................. 1376-15 PWM Hi-Z Characteristics ..................................................................................................... 1386-16 ADCSOCAO or ADCSOCBO Timing ........................................................................................ 1406-17 External Interrupt Timing....................................................................................................... 1406-18 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 1436-19 SPI Master Mode External Timing (Clock Phase = 1) ..................................................................... 1456-20 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 1476-21 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 1486-22 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 1526-23 Example Read Access ......................................................................................................... 1556-24 Example Write Access ......................................................................................................... 1576-25 Example Read With Synchronous XREADY Access ...................................................................... 1596-26 Example Read With Asynchronous XREADY Access ..................................................................... 1606-27 Write With Synchronous XREADY Access .................................................................................. 1626-28 Write With Asynchronous XREADY Access ................................................................................ 1636-29 External Interface Hold Waveform............................................................................................ 1656-30 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) .................................................. 1666-31 ADC Power-Up Control Bit Timing ........................................................................................... 1686-32 ADC Analog Input Impedance Model ........................................................................................ 1696-33 Sequential Sampling Mode (Single-Channel) Timing ...................................................................... 1706-34 Simultaneous Sampling Mode Timing ....................................................................................... 1716-35 McBSP Receive Timing ........................................................................................................ 1756-36 McBSP Transmit Timing ....................................................................................................... 1756-37 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ................................................... 1766-38 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ................................................... 1776-39 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ................................................... 1786-40 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ................................................... 179
6 List of Figures Copyright 20072010, Texas Instruments Incorporated
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439HJUNE 2007REVISED MARCH 2010
List of Tables2-1 F2833x Hardware Features .................................................................................................... 132-2 F2823x Hardware Features .................................................................................................... 142-3 Signal Descriptions............................................................................................................... 243-1 Addresses of Flash Sectors in F28335/F28235 ............................................................................. 393-2 Addresses of Flash Sectors in F28334/F28234 .............................................................................. 393-3 Addresses of Flash Sectors in F28332/F28232 .............................................................................. 393-4 Handling Security Code Locations ............................................................................................. 403-5 Wait-states ........................................................................................................................ 413-6 Boot Mode Selection............................................................................................................. 443-7 Peripheral Frame 0 Registers .................................................................................................. 493-8 Peripheral Frame 1 Registers .................................................................................................. 493-9 Peripheral Frame 2 Registers .................................................................................................. 503-10 Peripheral Frame 3 Registers .................................................................................................. 503-11 Device Emulation Registers..................................................................................................... 513-12 PIE Peripheral Interrupts ....................................................................................................... 543-13 PIE Configuration and Control Registers...................................................................................... 553-14 External Interrupt Registers ..................................................................................................... 563-15 PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................................................... 583-16 PLL Settings ...................................................................................................................... 603-17 CLKIN Divide Options ........................................................................................................... 603-18 Possible PLL Configuration Modes ............................................................................................ 613-19 Low-Power Modes ............................................................................................................... 634-1 CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 674-2 ePWM Control and Status Registers (Default Configuration in PF1)...................................................... 694-3 ePWM Control and Status Registers (Remapped Configuration in PF3 - DMA-Accessible)........................... 704-4 eCAP Control and Status Registers ........................................................................................... 744-5 eQEP Control and Status Registers ........................................................................................... 764-6 ADC Registers ................................................................................................................... 824-7 McBSP Register Summary...................................................................................................... 864-8 3.3-V eCAN Transceivers ...................................................................................................... 884-9 CAN Register Map .............................................................................................................. 914-10 SCI-A Registers .................................................................................................................. 934-11 SCI-B Registers .................................................................................................................. 934-12 SCI-C Registers ................................................................................................................. 944-13 SPI-A Registers................................................................................................................... 974-14 I2C-A Registers ................................................................................................................. 1004-15 GPIO Registers ................................................................................................................. 1024-16 GPIO-A Mux Peripheral Selection Matrix ................................................................................... 1034-17 GPIO-B Mux Peripheral Selection Matrix ................................................................................... 1044-18 GPIO-C Mux Peripheral Selection Matrix ................................................................................... 1054-19 XINTF Configuration and Control Register Mapping ....................................................................... 1085-1 TMS320x2833x, 2823x Peripheral Selection Guide ....................................................................... 1116-1 TMS320F28335/F28235 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT ................. 1186-2 TMS320F28334/F28234 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT ................. 1196-3 Typical Current Consumption by Various Peripherals (at 150 MHz) .................................................... 1206-4 Clocking and Nomenclature (150-MHz Devices) ........................................................................... 125
Copyright 20072010, Texas Instruments Incorporated List of Tables 7
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232SPRS439HJUNE 2007REVISED MARCH 2010 www.ti.com
6-5 Clocking and Nomenclature (100-MHz Devices) ........................................................................... 1256-6 Input Clock Frequency ......................................................................................................... 1266-7 XCLKIN Timing Requirements PLL Enabled ............................................................................. 1266-8 XCLKIN Timing Requirements PLL Disabled ............................................................................ 1266-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 1266-10 Power Management and Supervisory Circuit Solutions ................................................................... 1276-11 Reset (XRS) Timing Requirements .......................................................................................... 1296-12 General-Purpose Output Switching Characteristics ........................................................................ 1306-13 General-Purpose Input Timing Requirements .............................................................................. 1316-14 IDLE Mode Timing Requirements ........................................................................................... 1336-15 IDLE Mode Switching Characteristics ....................................................................................... 1336-16 STANDBY Mode Timing Requirements ..................................................................................... 1346-17 STANDBY Mode Switching Characteristics ................................................................................ 1346-18 HALT Mode Timing Requirements ........................................................................................... 1366-19 HALT Mode Switching Characteristics ...................................................................................... 1366-20 ePWM Timing Requirements ................................................................................................. 1386-21 ePWM Switching Characteristics ............................................................................................ 1386-22 Trip-Zone Input Timing Requirements ...................................................................................... 1386-23 High-Resolution PWM Characteristics at SYSCLKOUT = (60 150 MHz).............................................. 1396-24 Enhanced Capture (eCAP) Timing Requirement .......................................................................... 1396-25 eCAP Switching Characteristics ............................................................................................. 1396-26 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................. 1396-27 eQEP Switching Characteristics ............................................................................................. 1396-28 External ADC Start-of-Conversion Switching Characteristics............................................................. 1406-29 External Interrupt Timing Requirements .................................................................................... 1406-30 External Interrupt Switching Characteristics ................................................................................ 1406-31 I2C Timing ...................................................................................................................... 1416-32 SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 1426-33 SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 1446-34 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 1466-35 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 1486-36 Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 1496-37 XINTF Clock Configurations .................................................................................................. 1526-38 External Interface Read Timing Requirements ............................................................................. 1546-39 External Interface Read Switching Characteristics ......................................................................... 1546-40 External Interface Write Switching Characteristics ......................................................................... 1566-41 External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)................................... 1586-42 External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 1586-43 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 1586-44 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)....................................... 1586-45 External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ................................... 1616-46 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 1616-47 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 1616-48 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 1656-49 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 1666-50 ADC Electrical Characteristics (over recommended operating conditions) ............................................ 1676-51 ADC Power-Up Delays......................................................................................................... 1686-52 Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) .............................. 168
8 List of Tables Copyright 20072010, Texas Instruments Incorporated
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439HJUNE 2007REVISED MARCH 2010
6-53 Sequential Sampling Mode Timing ........................................................................................... 1706-54 Simultaneous Sampling Mode Timing ....................................................................................... 1716-55 McBSP Timing Requirements ................................................................................................ 1736-56 McBSP Switching Characteristics ........................................................................................... 1746-57 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ................................ 1766-58 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)............................ 1766-59 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ................................ 1776-60 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)............................ 1776-61 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ................................ 1786-62 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)............................ 1786-63 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ................................ 1796-64 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ........................... 1796-65 Flash Endurance for A and S Temperature Material ...................................................................... 1806-66 Flash Endurance for Q Temperature Material .............................................................................. 1806-67 Flash Parameters at 150-MHz SYSCLKOUT ............................................................................... 1806-68 Flash/OTP Access Timing ..................................................................................................... 1806-69 Minimum Required Flash/OTP Wait-States at Different Frequencies ................................................... 1809-1 Thermal Model 176-Pin PGF Results ........................................................................................ 1869-2 Thermal Model 176-Pin PTP Results ........................................................................................ 1869-3 Thermal Model 179-Ball ZHH Results ....................................................................................... 1869-4 Thermal Model 176-Ball ZJZ Results ....................................................................................... 187
Copyright 20072010, Texas Instruments Incorporated List of Tables 9
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232SPRS439HJUNE 2007REVISED MARCH 2010 www.ti.com
10 List of Tables Copyright 20072010, Texas Instruments Incorporated
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439HJUNE 2007REVISED MARCH 2010
Digital Signal Controllers (DSCs)Check for Samples: TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, TMS320F28232
1 TMS320F2833x, TMS320F2823x DSCs1.1 Features123
High-Performance Static CMOS Technology Enhanced Control Peripherals Up to 150 MHz (6.67-ns Cycle Time) Up to 18 PWM Outputs 1.9-V/1.8 -V Core, 3.3-V I/O Design Up to 6 HRPWM Outputs With 150 ps MEP
Resolution High-Performance 32-Bit CPU (TMS320C28x) Up to 6 Event Capture Inputs
IEEE-754 Single-Precision Floating-PointUnit (FPU) (F2833x only) Up to 2 Quadrature Encoder Interfaces
16 x 16 and 32 x 32 MAC Operations Up to 8 32-Bit/Nine 16-Bit Timers 16 x 16 Dual MAC Three 32-Bit CPU Timers Harvard Bus Architecture Serial Port Peripherals Fast Interrupt Response and Processing Up to 2 CAN Modules Unified Memory Programming Model Up to 3 SCI (UART) Modules Code-Efficient (in C/C++ and Assembly) Up to 2 McBSP Modules (Configurable as
SPI) Six-Channel DMA Controller (for ADC, McBSP,ePWM, XINTF, and SARAM) One SPI Module
16-Bit or 32-Bit External Interface (XINTF) One Inter-Integrated-Circuit (I2C) Bus Over 2M x 16 Address Reach 12-Bit ADC, 16 Channels
On-Chip Memory 80-ns Conversion Rate F28335/F28235: 256K x 16 Flash, 34K x 16 2 x 8 Channel Input Multiplexer
SARAM Two Sample-and-Hold
F28334/F28234: 128K x 16 Flash, 34K x 16 Single/Simultaneous Conversions
SARAM Internal or External Reference
F28332/F28232: 64K x 16 Flash, 26K x 16 Up to 88 Individually Programmable,SARAM Multiplexed GPIO Pins With Input Filtering
1K x 16 OTP ROM JTAG Boundary Scan Support (1)
Boot ROM (8K x 16) Advanced Emulation Features
With Software Boot Modes (via SCI, SPI, Analysis and Breakpoint FunctionsCAN, I2C, McBSP, XINTF, and Parallel I/O) Real-Time Debug via Hardware
Standard Math Tables Development Support Includes
Clock and System Control ANSI C/C++ Compiler/Assembler/Linker
Dynamic PLL Ratio Changes Supported Code Composer Studio IDE
On-Chip Oscillator DSP/BIOS
Watchdog Timer Module Digital Motor Control and Digital Power
GPIO0 to GPIO63 Pins Can Be Connected to Software LibrariesOne of the Eight External Core Interrupts Low-Power Modes and Power Savings
Peripheral Interrupt Expansion (PIE) Block That IDLE, STANDBY, HALT Modes SupportedSupports All 58 Peripheral Interrupts Disable Individual Peripheral Clocks
128-Bit Security Key/Lock Protects Flash/OTP/RAM Blocks Prevents Firmware Reverse Engineering
(1) IEEE Standard 1149.1-1990 Standard Test Access Port andBoundary Scan Architecture
1
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2MicroStar BGA, Code Composer Studio, DSP/BIOS, TMS320C28x, Delfino, PowerPAD, TMS320C54x, TMS320C55x, C28x are trademarksof Texas Instruments.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright 20072010, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232SPRS439HJUNE 2007REVISED MARCH 2010 www.ti.com
Package Options: Temperature Options: Lead-free, Green Packaging A: 40C to 85C (PGF, ZHH, ZJZ) Low-Profile Quad Flatpack (PGF, PTP) S: 40C to 125C (PTP, ZJZ) MicroStar BGA (ZHH) Q: 40C to 125C (PTP, ZJZ) Plastic BGA (ZJZ) Community Resources
TI E2E Community TI Embedded Processors Wiki
1.2 Getting StartedThis section gives a brief overview of the steps to take when first developing for a C28x device. For moredetail on each of these steps, see the following: Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0). C2000 Getting Started Website (http://www.ti.com/c2000getstarted) TMS320F28x DSC Development and Experimenter's Kits (http://www.ti.com/f28xkits)
12 TMS320F2833x, TMS320F2823x DSCs Copyright 20072010, Texas Instruments IncorporatedSubmit Documentation Feedback
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234TMS320F28232
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439HJUNE 2007REVISED MARCH 2010
2 IntroductionThe TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, andTMS320F28232 devices, members of the TMS320C28x/ Delfino DSC/MCU generation, are highlyintegrated, high-performance solutions for demanding control applications.Throughout this document, the devices are abbreviated as F28335, F28334, F28332, F28235, F28234,and F28232, respectively. Table 2-1 and Table 2-2 provide a summary of features for each device.
Table 2-1. F2833x Hardware Features
FEATURE TYPE (1) F28335 (150 MHz) F28334 (150 MHz) F28332 (100 MHz)Instruction cycle 6.67 ns 6.67 ns 10 nsFloating-point Unit Yes Yes Yes3.3-V on-chip flash (16-bit word) 256K 128K 64KSingle-access RAM (SARAM) (16-bit word) 34K 34K 26KOne-time programmable (OTP) ROM
1K 1K 1K(16-bit word)Code security for on-chip
Yes Yes Yesflash/SARAM/OTP blocksBoot ROM (8K x 16) Yes Yes Yes16/32-bit External Interface (XINTF) 1 Yes Yes Yes6-channel Direct Memory Access (DMA) 0 Yes Yes YesPWM outputs 0 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6
ePWM1A/2A/3A/4A/5A/HRPWM channels 0 ePWM1A/2A/3A/4A/5A/6A ePWM1A/2A/3A/4A6A32-bit Capture inputs or auxiliary PWM 0 eCAP1/2/3/4/5/6 eCAP1/2/3/4 eCAP1/2/3/4outputs32-bit QEP channels (four inputs/channel) 0 eQEP1/2 eQEP1/2 eQEP1/2Watchdog timer Yes Yes Yes
No. of channels 16 16 1612-Bit ADC MSPS 2 12.5 12.5 12.5
Conversion time 80 ns 80 ns 80 ns32-Bit CPU timers 3 3 3Multichannel Buffered Serial Port 1 2 (A/B) 2 (A/B) 1 (A)(McBSP)/SPISerial Peripheral Interface (SPI) 0 1 1 1Serial Communications Interface (SCI) 0 3 (A/B/C) 3 (A/B/C) 2 (A/B)Enhanced Controller Area Network (eCAN) 0 2 (A/B) 2 (A/B) 2 (A/B)Inter-Integrated Circuit (I2C) 0 1 1 1General Purpose I/O pins (shared) 88 88 88External interrupts 8 8 8
176-Pin PGF Yes Yes Yes176-Pin PTP Yes Yes Yes
Packaging179-Ball ZHH Yes Yes Yes176-Ball ZJZ Yes Yes YesA: 40C to 85C (PGF, ZHH, ZJZ) (PGF, ZHH, ZJZ) (PGF, ZHH, ZJZ)
Temperature S: 40C to 125C (PTP, ZJZ) (PTP, ZJZ) (PTP, ZJZ)options Q: 40C to 125C
(PTP, ZJZ) (PTP, ZJZ) (PTP, ZJZ)(Q100 Qualification)
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minordifferences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in theTMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides.
Copyright 20072010, Texas Instruments Incorporated Introduction 13Submit Documentation Feedback
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234TMS320F28232
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232SPRS439HJUNE 2007REVISED MARCH 2010 www.ti.com
Table 2-1. F2833x Hardware Features (continued)FEATURE TYPE (1) F28335 (150 MHz) F28334 (150 MHz) F28332 (100 MHz)
Product status (2) TMS TMS TMS(2) See Section 5.1 , Device and Development Support Tool Nomenclature, for descriptions of device stages.
Table 2-2. F2823x Hardware Features
FEATURE TYPE (1) F28235 (150 MHz) F28234 (150 MHz) F28232 (100 MHz)Instruction cycle 6.67 ns 6.67 ns 10 nsFloating-point Unit No No No3.3-V on-chip flash (16-bit word) 256K 128K 64KSingle-access RAM (SARAM) (16-bit
34K 34K 26Kword)One-time programmable (OTP) ROM
1K 1K 1K(16-bit word)Code security for on-chip
Yes Yes Yesflash/SARAM/OTP blocksBoot ROM (8K x 16) Yes Yes Yes16/32-bit External Interface (XINTF) 1 Yes Yes Yes6-channel Direct Memory Access (DMA) 0 Yes Yes YesPWM outputs 0 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6HRPWM channels 0 ePWM1A/2A/3A/4A/5A/6A ePWM1A/2A/3A/4A/5A/6A ePWM1A/2A/3A/4A32-bit Capture inputs or auxiliary PWM 0 eCAP1/2/3/4/5/6 eCAP1/2/3/4 eCAP1/2/3/4outputs32-bit QEP channels (four inputs/channel) 0 eQEP1/2 eQEP1/2 eQEP1/2Watchdog timer Yes Yes Yes
No. of channels 16 16 1612-Bit ADC MSPS 2 12.5 12.5 12.5
Conversion time 80 ns 80 ns 80 ns32-Bit CPU timers 3 3 3Multichannel Buffered Serial Port 1 2 (A/B) 2 (A/B) 1 (A)(McBSP)/SPISerial Peripheral Interface (SPI) 0 1 1 1Serial Communications Interface (SCI) 0 3 (A/B/C) 3 (A/B/C) 2 (A/B)Enhanced Controller Area Network 0 2 (A/B) 2 (A/B) 2 (A/B)(eCAN)Inter-Integrated Circuit (I2C) 0 1 1 1General Purpose I/O pins (shared) 88 88 88External interrupts 8 8 8
176-Pin PGF Yes Yes Yes176-Pin PTP Yes Yes Yes
Packaging179-Ball ZHH Yes Yes Yes176-Ball ZJZ Yes Yes YesA: 40C to 85C (PGF, ZHH, ZJZ) (PGF, ZHH, ZJZ) (PGF, ZHH, ZJZ)S: 40C to 125C (PTP, ZJZ) (PTP, ZJZ) (PTP, ZJZ)
Temperature options Q: 40C to 125C(Q100 (PTP, ZJZ) (PTP, ZJZ) (PTP, ZJZ)Qualification)
Product status (2) TMS TMS TMS(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in theTMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides.
(2) See Section 5.1 , Device and Development Support Tool Nomenclature, for descriptions of device stages.
14 Introduction Copyright 20072010, Texas Instruments IncorporatedSubmit Documentation Feedback
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234TMS320F28232
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
GPIO48/ECAP5/XD31
TCK
EMU1
EMU0VDD3VFLVSS
TEST2
TEST1
XRS
TMS
TRST
TDO
TDI
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO27/ECAP4/EQEP2S/MFSXB
GPIO26/ECAP3/EQEP2I/MCLKXBVDDIOVSS
GPIO25/ECAP2/EQEP2B/MDRB
GPIO24/ECAP1/EQEP2A/MDXB
GPIO23/EQEP1I/MFSXA/SCIRXDB
GPIO22/EQEP1S/MCLKXA/SCITXDB
GPIO21/EQEP1B/MDRA/CANRXB
GPIO20/EQEP1A/MDXA/CANTXB
GPIO19/ /SCIRXDB/CANTXASPISTEA
GPIO18/SPICLKA/SCITXDB/CANRXAVDDVSSVDD2A18VSS2AGND
ADCRESEXT
ADCREFP
ADCREFM
ADCREFIN
ADCINB7ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
VDDAIO
GP
IO75/X
D4
GP
IO74/X
D5
GP
IO73/X
D6
GP
IO72/X
D7
GP
IO71/X
D8
GP
IO70/X
D9
VD
D
VS
S
GP
IO69/X
D10
GP
IO68/X
D11
GP
IO67/X
D12
VD
DIO
VS
S
GP
IO66/X
D13
VS
S
VD
D
GP
IO65/X
D14
GP
IO64/X
D15
GP
IO63/S
CIT
XD
C/X
D16
GP
IO62/S
CIR
XD
C/X
D17
GP
IO61/M
FS
RB
/XD
18
GP
IO60/M
CLK
RB
/XD
19
GP
IO59/M
FS
RA
/XD
20
VD
D
VS
S
VD
DIO
VS
S
XC
LK
INX
1
VS
S
X2
VD
D
GP
IO58/M
CLK
RA
/XD
21
GP
IO57/
/XD
22
SP
IST
EA
GP
IO56/S
PIC
LK
A/X
D23
GP
IO55/S
PIS
OM
IA/X
D24
GP
IO54/S
PIS
IMO
A/X
D25
GP
IO53/E
QE
P1I/X
D26
GP
IO52/E
QE
P1S
/XD
27
VD
DIO
VS
S
GP
IO51/E
QE
P1B
/XD
28
GP
IO50/E
QE
P1A
/XD
29
GP
IO49/E
CA
P6/X
D30
GP
IO30/C
AN
RX
A/X
A18
GP
IO29/S
CIT
XD
A/X
A19
VS
SV
DD
GP
IO0/E
PW
M1A
GP
IO1/E
PW
M1B
/EC
AP
6/M
FS
RB
GP
IO2/E
PW
M2A
VS
SV
DD
IO
GP
IO3/E
PW
M2B
/EC
AP
5/M
CLK
RB
GP
IO4/E
PW
M3A
GP
IO5/E
PW
M3B
/MF
SR
A/E
CA
P1
GP
IO6/E
PW
M4A
/EP
WM
SY
NC
I/E
PW
MS
YN
CO
VS
S
VD
D
GP
IO7/E
PW
M4B
/MC
LK
RA
/EC
AP
2
GP
IO8/E
PW
M5A
/CA
NT
XB
/AD
CS
OC
AO
GP
IO9/E
PW
M5B
/SC
ITX
DB
/EC
AP
3
GP
IO10/E
PW
M6A
/CA
NR
XB
/AD
CS
OC
BO
GP
IO11/E
PW
M6B
/SC
IRX
DB
/EC
AP
4
GP
IO12
/CA
NT
XB
/MD
XB
/TZ
1
VS
S
VD
D
GP
IO13/
/CA
NR
XB
/MD
RB
TZ
2
GP
IO14/
/XH
OLD
//
TZ
3S
CIT
XD
BM
CLK
XB
GP
IO15/
/XH
OLD
AT
Z4
/SC
IRX
DB
/MF
SX
B
GP
IO16/S
PIS
IMO
A/C
AN
TX
B/T
Z5
GP
IO17/S
PIS
OM
IA/C
AN
RX
B/T
Z6
VD
D
VS
S
VD
D1A
18
VS
S1A
GN
D
VS
SA
2
VD
DA
2
AD
CIN
A7
AD
CIN
A6
AD
CIN
A5
AD
CIN
A4
AD
CIN
A3
AD
CIN
A2
AD
CIN
A1
AD
CIN
A0
AD
CLO
VS
SA
IO
GPIO76/XD3
GPIO77/XD2
GPIO78/XD1
GPIO79/XD0
GPIO38/XWE0XCLKOUT
VDDVSS
GPIO28/SCIRXDA/XZCS6
GPIO34/ECAP1/XREADY
VDDIOVSS
GPIO36/SCIRXDA/XZCS0VDDVSS
GPIO35/SCITXDA/XR/W
XRDGPIO37/ECAP2/XZCS7
GPIO40/XA0/XWE1
GPIO41/XA1
GPIO42/XA2VDDVSS
GPIO43/XA3
GPIO44/XA4
GPIO45/XA5VDDIO
VSSGPIO46/XA6
GPIO47/XA7
GPIO80/XA8
GPIO81/XA9
GPIO82/XA10
VSSVDD
GPIO83/XA11
GPIO84/XA12VDDIO
VSSGPIO85/XA13
GPIO86/XA14
GPIO87/XA15
GPIO39/XA16
GPIO31/CANTXA/XA17
GPIO28/SCIRXDA/XZCS6
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439HJUNE 2007REVISED MARCH 2010
2.1 Pin AssignmentsThe 176-pin PGF/PTP low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-1. The179-ball ZHH ball grid array (BGA) terminal assignments are shown in Figure 2-2 through Figure 2-5. The176-ball ZJZ plastic ball grid array (PBGA) terminal assignments are shown in Figure 2-6 throughFigure 2-9.Table 2-3 describes the function(s) of each pin.
Figure 2-1. F2833x, F2823x 176-Pin PGF/PTP LQFP (Top View)
Copyright 20072010, Texas Instruments Incorporated Introduction 15Submit Documentation Feedback
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234TMS320F28232
ADCINB0 ADCINB2 ADCINB6 ADCREFP
ADCINA1
ADCRESEXTADCINA2 ADCLO ADCINA0 ADCINB4
VSS1AGND
ADCINA4 ADCINA3 ADCINB3 ADCREFIN
P P
N N
M M
L LADCINA5
GPIO18/
SPICLKA/
SCITXDB/
CANRXA
VSSA2 ADCINA7 ADCINB7
GPIO17/
SPISOMIA/
CANRXB/
TZ6
VDD1A18VDD
GPIO14/
/
SCITXDB/
MCLKXB
TZ3XHOLD/
GPIO13/
CANRXB/
MDRB
TZ2/
VDDAIO
K K
J J
H H
1 2 3 4 5
6 7
GPIO20/
EQEP1A/
MDXA/
CANTXB
VSS2AGND
GPIO21/
EQEP1B/
MDRA/
CANRXB
GPIO22/
EQEP1S/
MCLKXA/
SCITXDB
VSS
1 2 3 4 5 6 7
VSSAIO VSS
VDD
VDD
GPIO23/
EQEP1I/
MFSXA/
SCIRXDB
GPIO19/
SCIRXDB/
CANTXA
SPISTEA/
ADCINA6
GPIO16/
SPISIMOA/
CANTXB/
TZ5
GPIO15/
/
SCIRXDB/
MFSXB
TZ4XHOLDA/
VDDA2
VDD2A18
ADCREFMADCINB5ADCINB1
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232SPRS439HJUNE 2007REVISED MARCH 2010 www.ti.com
NOTEThe powerpad on the bottom side of the PTP package is not connected to the ground (GND)of the die. Proper thermal management of the PowerPAD package requires PCBpreparation. A thermal land is required on the surface of the PCB directly underneath thebody of the PowerPAD package. The size of the thermal land should be as large as neededto dissipate the required heat. Note that the PowerPAD package with exposed pad downmust be soldered to the PCB. Refer to the PowerPAD Thermally Enhanced PackageApplication Report (literature number SLMA002) for more details on using the PowerPADpackage.
Figure 2-2. F2833x, F2823x 179-Ball ZHH MicroStar BGA (Upper Left Quadrant) (Bottom View)
16 Introduction Copyright 20072010, Texas Instruments IncorporatedSubmit Documentation Feedback
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234TMS320F28232
GPIO50/
EQEP1A/
XD29
TMS TEST2 EMU1
GPIO51/
EQEP1B/
XD28
GPIO48/
ECAP5/
XD31
TCK
GPIO52/
EQEP1S/
XD27
VSS
GPIO27/
ECAP4/
EQEP2S/
MFSXB
XRS EMU0
GPIO53/
EQEP1I/
XD26
VDD
GPIO55/
SPISOMIA/
XD24
VSS
GPIO56/
SPICLKA/
XD23
GPIO58/
MCLKRA/
XD21
GPIO33/
SCLA/
EPWMSYNCO/
ADCSOCBO
TRST
GPIO32/
SDAA/
EPWMSYNCI/
ADCSOCAO
VDDIO
8 9
10 11 12 13 14
PP
NN
MM
LL
KK
JJ
HH
GPIO57/
/
XD22
SPISTEA
X1 XCLKIN
GPIO59/
MFSRA/
XD20
VSS
GPIO25/
ECAP2/
EQEP2B/
MDRB
VSS
VDD
VSS
8 9 10 11 12 13 14
VSS
VSS
TEST1
VDD3VFL
GPIO24/
ECAP1/
EQEP2A/
MDXB
GPIO26/
ECAP3/
EQEP2I/
MCLKXB
TDO
VDDIO
VSSX2
GPIO54/
SPISIMOA/
XD25
TDI
VDDIO
GPIO49/
ECAP6/
XD30
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439HJUNE 2007REVISED MARCH 2010
Figure 2-3. F2833x, F2823x 179-Ball ZHH MicroStar BGA (Upper Right Quadrant) (Bottom View)
Copyright 20072010, Texas Instruments Incorporated Introduction 17Submit Documentation Feedback
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234TMS320F28232
GPIO11
EPWM6B
SCIRXDB
ECAP4
/
/
/
GPIO12
CANTXB
MDXB
/
/
/
TZ1
GPIO10
EPWM6A
CANRXB
/
/
/
ADCSOCBO
GPIO9/
EPWM5B/
SCITXDB/
ECAP3
GPIO81/
XA9
GPIO8/
EPWM5A/
CANTXB/
ADCSOCAO
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
GPIO84/
XA12
GPIO6/
EPWM4A/
EPWMSYNCI/
EPWMSYNCO
GPIO4/
EPWM3A
GPIO5/
EPWM3B/
MFSRA/
ECAP1
GPIO3/
EPWM2B/
ECAP5/
MCLKRB
VDDIO
VDDIO
VSSGPIO2/
EPWM2A
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO86/
XA14
GPIO83/
XA11
G
F
E
D
GPIO0/
EPWM1A
GPIO29/
SCITXDA/
XA19
VSSGPIO85/
XA13
GPIO82/
XA10
VDD
GPIO30/
CANRXA/
XA18
GPIO39/
XA16VSS VDD
GPIO31/
CANTXA/
XA17
GPIO87/
XA15VDDIO
C
B
A
1 2 3 4 5 6 7
G
F
E
D
C
B
A
VSSGPIO45/
XA5
VSSGPIO80/
XA8
GPIO46/
XA6
GPIO43/
XA3
GPIO44/
XA4
GPIO47/
XA7VSS
1 2 3 4 5
6 7
VSSVDD
VSS
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232SPRS439HJUNE 2007REVISED MARCH 2010 www.ti.com
Figure 2-4. F2833x, F2823x 179-Ball ZHH MicroStar BGA (Lower Left Quadrant) (Bottom View)
18 Introduction Copyright 20072010, Texas Instruments IncorporatedSubmit Documentation Feedback
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234TMS320F28232
GPIO60/
MCLKRB/
XD19
GPIO64/
XD15
GPIO63/
SCITXDC/
XD16
GPIO61/
MFSRB/
XD18
GPIO67/
XD12
GPIO65/
XD14
GPIO62/
SCIRXDC
XD17
GPIO78/
XD1
GPIO79/
XD0
GPIO66/
XD13
GPIO68/
XD11
VSS
GPIO37/
ECAP2/
XZCS7
GPIO34/
ECAP1/
XREADY
GPIO38/
XWE0
GPIO70/
XD9
G
F
E
D
VDD
GPIO40/
XA0/
XWE1
VSS
XCLKOUTGPIO73/
XD6
GPIO42/
XA2XRD
GPIO28/
SCIRXDA/
XZCS6
VDD
GPIO35/
SCITXDA/
XR/W
GPIO69/
XD10
VDDIO
C
B
A
8 9 10 11 12 13 14
G
F
E
D
C
B
A
GPIO74/
XD5
GPIO76/
XD3
GPIO72/
XD7
GPIO75/
XD4
GPIO77/
XD2
VSS
GPIO41/
XA1
VSS
VDD
VSS
8 9
10 11 12 13 14
VSS VDD
VSS
VDDIO
GPIO36/
SCIRXDA/
XZCS0
VDD
GPIO71/
XD8
TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439HJUNE 2007REVISED MARCH 2010
Figure 2-5. F2833x, F2823x 179-Ball ZHH MicroStar BGA (Lower Right Quadrant) (Bottom View)
Copyright 20072010, Texas Instruments Incorporated Introduction 19Submit Documentation Feedback
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234TMS320F28232
VSSA2 ADCINB0 ADCREFM ADCREFP ADCRESEXT ADCREFIN
VSSAIO ADCLO ADCINB1 ADCINB3 ADCINB5 ADCINB7 EMU0
ADCINA2 ADCINA1 ADCINA0 ADCINB2 ADCINB4 ADCINB6 TEST1
ADCINA5 ADCINA4 ADCINA3 VSS1AGND VDDAIO VDD2A18 TEST2
ADCINA7 ADCINA6 VDD1A18 VDDA2
GPIO15/
/ /
SCIRXDB/
MFSXB
TZ4XHOLDA
GPIO16/
SPISIMOA/
CANTXB/
TZ5
GPIO17/
SPISOMIA/
CANRXB/
TZ6
VDD VSS VSS
GPIO14/
/TZ3XHOLD/
SCITXDB/
MCLKXB
VDD VSS VSS
P
N
M
L
K
J
H
1 2 3 4 5 6 7
VSS2AGND
GPIO12/
TZ1/
CANTXB/
MDXB
GPIO13/
TZ2/
CANRXB/
MDRB
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Figure 2-6. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper Left Quadrant) (Bottom View)
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VSS VSS
VSS VSS
P
N
M
L
K
J
H
8 9 10 11 12 13 14
EMU1
GPIO20/
EQEP1A/
MDXA/
CANTXB
GPIO23/
EQEP1I/
MFSXA/
SCIRXDB
GPIO26/
ECAP3/
EQEP2I/
MCLKXB
GPIO33/
SCLA/
EPWMSYNCO/
ADCSOCBO
VSS VSS
GPIO18/
SPICLKA/
SCITXDB/
CANRXA
GPIO21/
EQEP1B/
MDRA/
CANRXB
GPIO24/
ECAP1/
EQEP2A/
MDXB
GPIO27/
ECAP4/
EQEP2S/
MFSXB
TDI TDO VDDIO
GPIO19/
/
SCIRXDB/
CANTXA
SPISTEA
GPIO22/
EQEP1S/
MCLKXA/
SCITXDB
GPIO25/
ECAP2/
EQEP2B/
MDRB
GPIO32/
SDAA/
EPWMSYNCI/
ADSOCAO
TMS XRS TCK
VDD VDD3VFL VDDIO TRST
GPIO50/
EQEP1A/
XD29
GPIO49/
ECAP6/
XD30
GPIO48/
ECAP5/
XD31
VDD
GPIO53
EQEP1I/
XD26
GPIO52/
EQEP1S/
XD27
GPIO51/
EQEP1B/
XD28
VDD
GPIO56/
SPICLKA/
XD23
GPIO55/
SPISOMIA/
XD24
GPIO54/
SPISIMOA/
XD25
GPIO59/
MFSRA/
XD20
GPIO58/
MCLKRA/
XD21
GPIO57/
/
XD22
SPISTEA X2
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Figure 2-7. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper Right Quadrant) (Bottom View)
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GF
E
D
C
B
A
1 2 3 4 5 6 7
GPIO9/
EPWM5B/
SCITXDB/
ECAP3
GPIO10/
EPWM6A/
CANRXB/
ADCSOCBO
GPIO11/
EPWM6B/
SCIRXDB/
ECAP4
VDDIO VSS VSS
VSS VSS
GPIO6/
EPWM4A/
EPWMSYNCI/
EPWMSYNCO
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
GPIO8/
EPWM5A/
CANTXB/
ADCSOCAO
VDD
GPIO3/
EPWM2B/
ECAP5/
MCLKRB
GPIO4/
EPWM3A
GPIO5/
EPWM3B/
MFSRA/
ECAP1
VDDIO
GPIO0/
EPWM1A
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO2/
EPWM2AVDD VDD
GPIO47/
XA7VDDIO
GPIO29/
SCITXDA/
XA19
GPIO30/
CANRXA/
XA18
GPIO39/
XA16
GPIO85/
XA13
GPIO82/
XA10
GPIO46/
XA6
GPIO43/
XA3
VDDIO
GPIO31/
CANTXA/
XA17
GPIO87/
XA15
GPIO84/
XA12
GPIO81/
XA9
GPIO45/
XA5
GPIO42/
XA2
VSS VSSGPIO86/
XA14
GPIO83/
XA11
GPIO80/
XA8
GPIO44/
XA4
GPIO41/
XA1
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Figure 2-8. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower Left Quadrant) (Bottom View)
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GF
E
D
C
B
A
8 9 10 11 12 13 14
X1VSS VSS
VSS VSS
VDDIO
GPIO60/
MCLKRB/
XD19
XCLKIN
VDD
GPIO63/
SCITXDC/
XD16
GPIO62/
SCIRXDC/
XD17
GPIO61/
MFSRB/
XD18
VDDGPIO66/
XD13
GPIO65/
XD14
GPIO64/
XD15
VDD VDD
GPIO28/
SCIRXDA/
XZCS6
VDDIOGPIO69/
XD10
GPIO68/
XD11
GPIO67/
XD12
GPIO40/
XA0/XWE1
GPIO36/
SCIRXDA/
XZCS0
GPIO38/
XWE0
GPIO78/
XD1
GPIO75/
XD4
GPIO71/
XD8
GPIO70/
XD9
GPIO37/
ECAP2/
XZCS7
GPIO35/
SCITXDA/
XR/W
GPIO79/
XD0
GPIO77/
XD2
GPIO74/
XD5
GPIO72
XD7VSS
VSSXRD
GPIO34/
ECAP1/
XREADY
XCLKOUTGPIO76/
XD3
GPIO73/
XD6VDDIO
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Figure 2-9. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower Right Quadrant) (Bottom View)
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2.2 Signal DescriptionsTable 2-3 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheralsignals that are listed under them are alternate functions. Some peripheral functions may not be availablein all devices. See Table 2-1 and Table 2-2 for details. Inputs are not 5-V tolerant. All pins capable ofproducing an XINTF output function have a drive strength of 8 mA (typical). This is true even if the pin isnot configured for XINTF functionality. All other pins have a drive strength of 4-mA drive typical (unlessotherwise indicated). All GPIO pins are I/O/Z and have an internal pullup, which can be selectivelyenabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups onGPIO0GPIO11 pins are not enabled at reset. The pullups on GPIO12GPIO87 are enabled upon reset.
Table 2-3. Signal Descriptions
PIN NO.PGF/NAME DESCRIPTION (1)ZHH ZJZPTP BALL # BALL #PIN #
JTAGJTAG test reset with internal pulldown. TRST, when driven high, gives the scan systemcontrol of the operations of the device. If this signal is not connected or driven low, thedevice operates in its functional mode, and the test reset signals are ignored.NOTE: TRST is an active high test pin and must be maintained low at all times during
TRST 78 M10 L11 normal device operation. An external pulldown resistor is required on this pin. The value ofthis resistor should be based on drive strength of the debugger pods applicable to thedesign. A 2.2-k resistor generally offers adequate protection. Since this isapplication-specific, it is recommended that each target board be validated for properoperation of the debugger and the application. (I, )
TCK 87 N12 M14 JTAG test clock with internal pullup (I, )JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked intoTMS 79 P10 M12 the TAP controller on the rising edge of TCK. (I, )JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected registerTDI 76 M9 N12 (instruction or data) on a rising edge of TCK. (I, )JTAG scan out, test data output (TDO). The contents of the selected register (instruction orTDO 77 K9 N13 data) are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from theemulator system and is defined as input/output through the JTAG scan. This pin is alsoused to put the device into boundary-scan mode. With the EMU0 pin at a logic-high stateand the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch thedevice into boundary-scan mode. (I/O/Z, 8 mA drive )EMU0 85 L11 N7 NOTE: An external pullup resistor is required on this pin. The value of this resistor shouldbe based on the drive strength of the debugger pods applicable to the design. A 2.2-k to4.7-k resistor is generally adequate. Since this is application-specific, it is recommendedthat each target board be validated for proper operation of the debugger and theapplication.Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from theemulator system and is defined as input/output through the JTAG scan. This pin is alsoused to put the device into boundary-scan mode. With the EMU0 pin at a logic-high stateand the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch thedevice into boundary-scan mode. (I/O/Z, 8 mA drive )EMU1 86 P12 P8 NOTE: An external pullup resistor is required on this pin. The value of this resistor shouldbe based on the drive strength of the debugger pods applicable to the design. A 2.2-k to4.7-k resistor is generally adequate. Since this is application-specific, it is recommendedthat each target board be validated for proper operation of the debugger and theapplication.
FLASHVDD3VFL 84 M11 L9 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.TEST1 81 K10 M7 Test Pin. Reserved for TI. Must be left unconnected. (I/O)TEST2 82 P11 L7 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
(1) I = Input, O = Output, Z = High impedance, OD = Open drain, = Pullup, = Pulldown24 Introduction Copyright 20072010, Texas Instruments Incorporated
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TMS320F28232
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Table 2-3. Signal Descriptions (continued)PIN NO.
PGF/NAME DESCRIPTION (1)ZHH ZJZPTP BALL # BALL #PIN #CLOCK
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-halfthe frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 18:16(XTIMCLK) and bit 2 (CLKMODE) in the XINTCNF2 register. At reset, XCLKOUT =XCLKOUT 138 C11 A10 SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XINTCNF2[CLKOFF]to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance stateduring a reset. (O/Z, 8 mA drive).External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this
XCLKIN 105 J14 G13 case, the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.9-Voscillator is used to feed clock to X1 pin), this pin must be tied to GND. (I)Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or aceramic resonator may be connected across X1 and X2. The X1 pin is referenced to the
X1 104 J13 G14 1.9-V core digital power supply. A 1.9-V external oscillator may be connected to the X1 pin.In this case, the XCLKIN pin must be connected to ground. If a 3.3-V external oscillator isused with the XCLKIN pin, X1 must be tied to GND. (I)Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connectedX2 102 J11 H14across X1 and X2. If X2 is not used, it must be left unconnected. (O)
RESETDevice Reset (in) and Watchdog Reset (out).Device reset. XRS causes the device to terminate execution. The PC will point to theaddress contained at the location 0x3FFFC0. When XRS is brought to a high level,execution begins at the location pointed to by the PC. This pin is driven low by the DSCXRS 80 L10 M13when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for thewatchdog reset duration of 512 OSCCLK cycles. (I/OD, )The output buffer of this pin is an open-drain with an internal pullup. It is recommendedthat this pin be driven by an open-drain device.
ADC SIGNALSADCINA7 35 K4 K1 ADC Group A, Channel 7 input (I)ADCINA6 36 J5 K2 ADC Group A, Channel 6 input (I)ADCINA5 37 L1 L1 ADC Group A, Channel 5 input (I)ADCINA4 38 L2 L2 ADC Group A, Channel 4 input (I)ADCINA3 39 L3 L3 ADC Group A, Channel 3 input (I)ADCINA2 40 M1 M1 ADC Group A, Channel 2 input (I)ADCINA1 41 N1 M2 ADC Group A, Channel 1 input (I)ADCINA0 42 M3 M3 ADC Group A, Channel 0 input (I)ADCINB7 53 K5 N6 ADC Group B, Channel 7 input (I)ADCINB6 52 P4 M6 ADC Group B, Channel 6 input (I)ADCINB5 51 N4 N5 ADC Group B, Channel 5 input (I)ADCINB4 50 M4 M5 ADC Group B, Channel 4 input (I)ADCINB3 49 L4 N4 ADC Group B, Channel 3 input (I)ADCINB2 48 P3 M4 ADC Group B, Channel 2 input (I)ADCINB1 47 N3 N3 ADC Group B, Channel 1 input (I)ADCINB0 46 P2 P3 ADC Group B, Channel 0 input (I)ADCLO 43 M2 N2 Low Reference (connect to analog ground) (I)ADCRESEXT 57 M5 P6 ADC External Current Bias Resistor. Connect a 22-k resistor to analog ground.ADCREFIN 54 L5 P7 External reference input (I)
Internal Reference Positive Output. Requires a low ESR (50 m - 1.5 ) ceramic bypassADCREFP 56 P5 P5capacitor of 2.2 mF to analog ground. (O)Internal Reference Medium Output. Requires a low ESR (50 m - 1.5 ) ceramic bypassADCREFM 55 N5 P4capacitor of 2.2 mF to analog ground. (O)
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Table 2-3. Signal Descriptions (continued)PIN NO.
PGF/NAME DESCRIPTION (1)ZHH ZJZPTP BALL # BALL #PIN #CPU AND I/O POWER PINS
VDDA2 34 K2 K4 ADC Analog Power PinVSSA2 33 K3 P1 ADC Analog Ground PinVDDAIO 45 N2 L5 ADC Analog I/O Power PinVSSAIO 44 P1 N1 ADC Analog I/O Ground PinVDD1A18 31 J4 K3 ADC Analog Power PinVSS1AGND 32 K1 L4 ADC Analog Ground PinVDD2A18 59 M6 L6 ADC Analog Power PinVSS2AGND 58 K6 P2 ADC Analog Ground PinVDD 4 B1 D4VDD 15 B5 D5VDD 23 B11 D8VDD 29 C8 D9VDD 61 D13 E11VDD 101 E9 F4VDD 109 F3 F11 CPU and Logic Digital Power PinsVDD 117 F13 H4VDD 126 H1 J4VDD 139 H12 J11VDD 146 J2 K11VDD 154 K14 L8VDD 167 N6VDDIO 9 A4 A13VDDIO 71 B10 B1VDDIO 93 E7 D7VDDIO 107 E12 D11VDDIO 121 F5 E4 Digital I/O Power PinVDDIO 143 L8 G4VDDIO 159 H11 G11VDDIO 170 N14 L10VDDIO N14
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Table 2-3. Signal Descriptions (continued)PIN NO.
PGF/NAME DESCRIPTION (1)ZHH ZJZPTP BALL # BALL #PIN #VSS 3 A5 A1VSS 8 A10 A2VSS 14 A11 A14VSS 22 B4 B14VSS 30 C3 F6VSS 60 C7 F7VSS 70 C9 F8VSS 83 D1 F9VSS 92 D6 G6VSS 103 D14 G7VSS 106 E8 G8VSS 108 E14 G9VSS 118 F4 H6 Digital Ground PinsVSS 120 F12 H7VSS 125 G1 H8VSS 140 H10 H9VSS 144 H13 J6VSS 147 J3 J7VSS 155 J10 J8VSS 160 J12 J9VSS 166 M12 P13VSS 171 N10 P14VSS N11VSS P6VSS P8
GPIO AND PERIPHERAL SIGNALSGPIO0 General purpose input/output 0 (I/O/Z)EPWM1A Enhanced PWM1 Output A and HRPWM channel (O)5 C1 D1- -
- -
GPIO1 General purpose input/output 1 (I/O/Z)EPWM1B Enhanced PWM1 Output B (O)6 D3 D2ECAP6 Enhanced Capture 6 input/output (I/O)MFSRB McBSP-B receive frame synch (I/O)GPIO2 General purpose input/output 2 (I/O/Z)EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)7 D2 D3- -
- -
GPIO3 General purpose input/output 3 (I/O/Z)EPWM2B Enhanced PWM2 Output B (O)10 E4 E1ECAP5 Enhanced Capture 5 input/output (I/O)MCLKRB McBSP-B receive clock (I/O)GPIO4 General purpose input/output 4 (I/O/Z)EPWM3A Enhanced PWM3 output A and HRPWM channel (O)11 E2 E2- -
- -
GPIO5 General purpose input/output 5 (I/O/Z)EPWM3B Enhanced PWM3 output B (O)12 E3 E3MFSRA McBSP-A receive frame synch (I/O)ECAP1 Enhanced Capture input/output 1 (I/O)
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Table 2-3. Signal Descriptions (continued)PIN NO.
PGF/NAME DESCRIPTION (1)ZHH ZJZPTP BALL # BALL #PIN #GPIO6 General purpose input/output 6 (I/O/Z)EPWM4A Enhanced PWM4 output A and HRPWM channel (O)13 E1 F1EPWMSYNCI External ePWM sync pulse input (I)EPWMSYNCO External ePWM sync pulse output (O)GPIO7 General purpose input/output 7 (I/O/Z)EPWM4B Enhanced PWM4 output B (O)16 F2 F2MCLKRA McBSP-A receive clock (I/O)ECAP2 Enhanced capture input/output 2 (I/O)GPIO8 General Purpose Input/Output 8 (I/O/Z)EPWM5A Enhanced PWM5 output A and HRPWM channel (O)17 F1 F3CANTXB Enhanced CAN-B transmit (O)ADCSOCAO ADC start-of-conversion A (O)GPIO9 General purpose input/output 9 (I/O/Z)EPWM5B Enhanced PWM5 output B (O)18 G5 G1SCITXDB SCI-B transmit data(O)ECAP3 Enhanced capture input/output 3 (I/O)GPIO10 General purpose input/output 10 (I/O/Z)EPWM6A Enhanced PWM6 output A and HRPWM channel (O)19 G4 G2CANRXB Enhanced CAN-B receive (I)ADCSOCBO ADC start-of-conversion B (O)GPIO11 General purpose input/output 11 (I/O/Z)EPWM6B Enhanced PWM6 output B (O)20 G2 G3SCIRXDB SCI-B receive data (I)ECAP4 Enhanced CAP Input/Output 4 (I/O)GPIO12 General purpose input/output 12 (I/O/Z)TZ1 Trip Zone input 1 (I)21 G3 H1CANTXB Enhanced CAN-B transmit (O)MDXB McBSP-B transmit serial data (O)GPIO13 General purpose input/output 13 (I/O/Z)TZ2 Trip Zone input 2 (I)24 H3 H2CANRXB Enhanced CAN-B receive (I)MDRB McBSP-B receive serial data (I)GPIO14 General purpose input/output 14 (I/O/Z)
Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the externalinterface (XINTF) to release the external bus and place all buses and strobes into ahigh-impedance state. To prevent this from happening when TZ3 signal goes active,
TZ3/XHOLD disable this function by writing XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus25 H2 H3will go into high impedance anytime TZ3 goes low. On the ePWM side, TZn signals areignored by default, unless they are enabled by the code. The XINTF will release the buswhen any current access is complete and there are no pending accesses on the XINTF. (I)
SCITXDB SCI-B Transmit (O)MCLKXB McBSP-B transmit clock (I/O)GPIO15 General purpose input/output 15 (I/O/Z)
Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based onthe direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4function is chosen. If the pin is configured as an output, then XHOLDA function is chosen.
TZ4/XHOLDA XHOLDA is driven active (low) when the XINTF has granted an XHOLD request. All XINTF26 H4 J1 buses and strobe signals will be in a high-impedance state. XHOLDA is released when theXHOLD signal is released. External devices should only drive the external bus whenXHOLDA is active (low). (I/O)
SCIRXDB SCI-B receive (I)MFSXB McBSP-B transmit frame synch (I/O)GPIO16 General purpose input/output 16 (I/O/Z)SPISIMOA SPI slave in, master out (I/O)27 H5 J2CANTXB Enhanced CAN-B transmit (O)TZ5 Trip Zone input 5 (I)
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Table 2-3. Signal Descriptions (continued)PIN NO.
PGF/NAME DESCRIPTION (1)ZHH ZJZPTP BALL # BALL #PIN #GPIO17 General purpose input/output 17 (I/O/Z)SPISOMIA SPI-A slave out, master in (I/O)28 J1 J3CANRXB Enhanced CAN-B receive (I)TZ6 Trip zone input 6 (I)GPIO18 General purpose input/output 18 (I/O/Z)SPICLKA SPI-A clock input/output (I/O)62 L6 N8SCITXDB SCI-B transmit (O)CANRXA Enhanced CAN-A receive (I)GPIO19 General purpose input/output 19 (I/O/Z)SPISTEA SPI-A slave transmit enable input/output (I/O)63 K7 M8SCIRXDB SCI-B receive (I)CANTXA Enhanced CAN-A transmit (O)GPIO20 General purpose input/output 20 (I/O/Z)EQEP1A Enhanced QEP1 input A (I)64 L7 P9MDXA McBSP-A transmit serial data (O)CANTXB Enhanced CAN-B transmit (O)GPIO21 General purpose input/output 21 (I/O/Z)EQEP1B Enhanced QEP1 input B (I)65 P7 N9MDRA McBSP-A receive serial data (I)CANRXB Enhanced CAN-B receive (I)GPIO22 General purpose input/output 22 (I/O/Z)EQEP1S Enhanced QEP1 strobe (I/O)66 N7 M9MCLKXA McBSP-A transmit clock (I/O)SCITXDB SCI-B transmit (O)GPIO23 General purpose input/output 23 (I/O/Z)EQEP1I Enhanced QEP1 index (I/O)67 M7 P10MFSXA McBSP-A transmit frame synch (I/O)SCIRXDB SCI-B receive (I)GPIO24 General purpose input/output 24 (I/O/Z)ECAP1 Enhanced capture 1 (