EE130 Lecture 41, Slide 1Spring 2007

Lecture #41

QUIZ #6 (Friday, May 4)• Material of HW#12 & HW#13 (Lectures 33 through 38)

– MOS non-idealities, VT adjustment; MOSFET I-V, effective mobility, body effect, and small-signal model

• Closed book, no calculators; 6 pages of notes allowed• Review session today at 5PM in 521 Cory (Hogan Rm)

OUTLINE Modern MOSFETs:

• The short-channel effect• Source/drain structure• Drain-induced barrier lowering• Excess current effects

Reading: Chapter 19.1, 19.2

EE130 Lecture 41, Slide 2Spring 2007

The Short Channel Effect (SCE)

• |VT| decreases with L– Effect is exacerbated by

high values of |VDS|

• This is undesirable (i.e. we want to minimize it!) because circuit designers would like VT to be invariant with transistor dimensions and biasing conditions

“VT roll-off”

EE130 Lecture 41, Slide 3Spring 2007

Qualitative Explanation of SCE

• Before an inversion layer forms beneath the gate, the surface of the Si underneath the gate must be depleted (to a depth WT)

• The source & drain pn junctions assist in depleting the Si underneath the gate – Portions of the depletion charge in the channel

region are balanced by charge in S/D regions, rather than by charge on the gate

less gate charge is required to reach inversion (i.e. |VT | decreases)

EE130 Lecture 41, Slide 4Spring 2007

depletionchargesupportedby gate(simplifiedanalysis)

n+ n+

VG

p depletion region

Large L:

S D

Small L:

DS

Depletion charge supported by S/D

Depletion charge supported by S/D

The smaller the L, the greater percentage of charge balanced by the S/D pn junctions:

rj

EE130 Lecture 41, Slide 5Spring 2007

First-Order Analysis of SCE• The gate supports the depletion

charge in the trapezoidal region. This is smaller than the rectangular depletion region underneath the gate, by the factor

• This is the factor by which the depletion charge Qdep is reduced from the ideal

• One can deduce from simple geometric analysis that

1

212

j

Tj r

WrLL

L

LL

21

Wdm

EE130 Lecture 41, Slide 6Spring 2007

VT Roll-Off: First-Order Model

1

21)(

j

Tj

oxe

TATchannellongTT r

W

L

r

C

WqNVVV

Minimize VT by

• reducing Toxe

• reducing rj

• increasing NA

(trade-offs: degraded m, MOSFET vertical dimensions should be scaled along with horizontal dimensions!

EE130 Lecture 41, Slide 7Spring 2007

Source and Drain Structure• To minimize SCE, we want

shallow (small rj) S/D regions -- but the parasitic resistance of these regions will increase when rj is reduced.

where = resistivity of the S/D regions

• Shallow S/D “extensions” may be used to effectively reduce rj without increasing the S/D sheet resistance too much

jdrainsource WrRR /,

EE130 Lecture 41, Slide 8Spring 2007

Electric Field Along the Channel• The lateral electric field peaks

at the drain.– peak can be as high as 106 V/cm

• High E-field causes problems:– damage to gate-oxide interface

and bulk – substrate current due to impact

ionization:

EE130 Lecture 41, Slide 9Spring 2007

• Parasitic BJT action

EE130 Lecture 41, Slide 10Spring 2007

Lightly Doped Drain Structure

• Lower pn junction doping results in lower peak E-field “Hot-carrier” effects

reduced Series resistance

increased

EE130 Lecture 41, Slide 11Spring 2007

)(1 0

0

TGS

sDsat

DsatDsat

VVRI

II

• If IDsat0 VGS – VT ,

• IDsat is reduced by about 15% in a 0.1m MOSFET.

• VDsat = VDsat0 + IDsat (Rs + Rd)

Rs RdS D

G

gate

oxide

dielectric spacer contact metal

channel

N+ source or drain

Parasitic Source-Drain Resistance

TiSi2 or NiSi

EE130 Lecture 41, Slide 12Spring 2007

Drain Induced Barrier Lowering (DIBL)• As the source & drain get closer, they become

electrostatically coupled, so that the drain bias can affect the potential barrier to carrier flow at the source junction subthreshold current increases.

EE130 Lecture 41, Slide 13Spring 2007

Excess Current Effects

• Punchthrough

EE130 Lecture 41, Slide 14Spring 2007

Summary: MOSFET OFF State vs. ON State

• OFF state (VGS < VT):– IDS is limited by the rate at which carriers diffuse across the

source pn junction– Sub-threshold swing S, DIBL are issues

• ON state (VGS > VT):– IDS is limited by the rate at which carriers drift across the

channel– Punchthrough and parasitic BJT effects are of concern at

high drain bias• IDsat increases rapidly with VDS

– Parasitic series resistances reduce drive current• source resistance RS reduces effective VGS

• source and drain resistances RS and RD reduce effective VDS

EE130 Lecture 41, Slide 15Spring 2007