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June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Software-Hardware co-design for Real Time Systems
Marko BertognaReTiS Lab.
Scuola S.Anna, Pisa
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Overview What is Co-design? Co-design typical instruments
VHDL SystemC
Reconfigurable Devices CSoC Co-design for RT Systems
Introduction
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Co-design types Mechanical vs electrical design Analog/digital Control vs computing Sw/Hw
time vs space programming centralized vs distributed computing sequential vs parallel behaviour
Introduction
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
What is a task in hardware?
Software programming
c=a+b;
result=c/2;
Hardware implement.
a
b
c+
shifter
result
Assembler expansion:ldr r0,aldr r1,badd r0,r0,r1mov r0,LSR r0str r0,result
5 operations
All in one clock cycle!
Introduction
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
VHDL – Verilog Very High Speed Integrated Circuit
Hardware Description Language formal model for the behaviour of a
system simulation synthesis: automatic transformation
refinement from a less detailed description… until existing components
design reuse
VHDL
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
VHDL features Abstraction, modularity, hierarchy
Behavioural
RTL
Logic
Layout
o<=i1+i2*i3 after 100 ns
…U6: ND2 port map(A=>n3, B=>n9, Z=>I7);U7: IVP port map(A=>n13, B=>n19);U8: ND2 port map(A=>u8, B=>u1, Z=>n4);…
VHDL
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
VHDL synthesis steps Specification (“paper and pencil”) System level: behaviour Logic design: all synthesis aspects Gate level: mapping to ASIC library or
FPGA logic blocks. Automatic synthesis Netlist
Layout
Validation at each step!
VHDLdesign
VHDL
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
VHDL synthesis
Behavioural VHDL RTL VHDL Netlist VHDL Layout
Back annotationΣ longest path (gate delay) < Tck
Brehavioural synthesisLogic synthesis (use gate libraries)
Placementand route
functional timing:“after 10s signal A switches to 1”
clock, functions, events gate delays path delays
VHDL
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
VHDL structural elements Entity/Architecture Components Configuration Process Library Subprogram (functions
and procedures) Package/Package
Body Signals, Testbench
entity HALFADDER is port( A, B: in bit; SUM, CARRY: out bit);end HALFADDER;
architecture RTL of HALFADDER is
begin
SUM <= A xor B; CARRY <= A and B;
end RTL;-- VHDL'93: end architecture RTL ;
VHDL
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
VHDL synthesis exampleLibrary IEEE;use IEEE.Std_Logic_1164.all;entity IF_EXAMPLE is port (A, B, C, X : in std_ulogic_vector..; Z : out std_ulogic_vector..);end IF_EXAMPLE;
architecture A of IF_EXAMPLE isbegin
process (A, B, C, X) begin if ( X = "1110" ) then Z <= A; elsif (X = "0101") then Z <= B; else Z <= C; end if; end process;end A;
VHDL
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
VHDL optimization examples
Refinement
Refinement
OUT1<=IN1+IN2+IN3+IN4+IN5+IN6 OUT2<=(IN1+IN2)+(IN3+IN4)+(IN5+IN6)
VHDL
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
SystemC Integration with C++ Provides:
hardware timing (clock and delay) concurrency support (modules) reactive behaviour (events) signal-based communication support new data types (logic values, bit vectors,
etc.)
No need to translate to HDLs
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
SystemC Design Methodology
Current system design methodology: SystemC Design Methodology:
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
SystemC features Implemented as a C++ class
library (libsystemc.a) Inherits all hierarchy features Built-in simulation environment Easy refinement and reworking Lightweight
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
SystemC core language Modules Processes Clocks, custom wait() calls Support for events, sensitivity list,
watching() construct Signals
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Modules Basic building block Map functionality of Hw/Sw blocks Derived from class sc_module Possibility to use hierarchy
constructs and sub-modules Interface each other via
ports/interfaces/channels
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Modules//my_module.hSC_MODULE(my_module){//port declarations//process declarationsSC_CTOR(my_module){//process configuration//initialization code}};
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Ports/Channels/Interfaces
Ports provide communication functions to modulesInterfaces connect ports to channelsTypical channel: signal
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Processes Provide module functionality Implemented as C++ member
functions Run concurrently between each other Execute statements sequentially Three kinds:
SC_METHOD SC_THREAD SC_CTHREAD
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
SC_METHOD//my_module.hSC_MODULE(my_module){sc_in<bool> id;sc_in<sc_uint<3> > in_a;sc_in<sc_uint<3> > in_b;sc_out<sc_uint<3> > out_c;void my_method();SC_CTOR(my_module){SC_METHOD(my_method);sensitive << a << b;}};
//my_module.cppvoid my_module::my_method(){if (id.read())out_c.write(in_a.read());elseout_c.write(in_b.read());};
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
SC_THREAD//my_module.hSC_MODULE(my_module){sc_in<bool> id;sc_in<bool> clock;sc_in<sc_uint<3> > in_a;sc_in<sc_uint<3> > in_b;sc_out<sc_uint<3> > out_c;void my_thread();SC_CTOR(my_module){SC_THREAD(my_thread);sensitive << clock.pos();}};
//my_module.cppvoid my_module:: my_thread(){while(true){if (id.read())out_c.write(in_a.read());elseout_c.write(in_b.read());wait();}};
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Channels The most common type is signal Signal can be traced: waveform
dumping produces .VCD output file Other channels:
sc_fifo sc_mutex sc_semaphore
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
SystemC scheduler Similar to HDL scheduler Two different time steps:
Discrete simulation cycle “Delta cycle”
“Evaluate then update” semantic Order of process resumption
unknown Event objects extend sensitivity
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Co-design for embedded systems “Programming in Space” versus
“Programming in Time” Key design choices:
- Computational units and their granularity
- Interconnect Network- (Re)configuration time and frequency
Formal verification Automatic synthesis
Reconfigurable Devices
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Flexibility vs efficiency
Reconfigurable Devices
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Reconfigurable devices advantages Efficiency AND Flexibility Time to market Easier upgrade Lower cost (on scale production) Reusable IP Customable interface
Reconfigurable Devices
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Reconfigurable devices parameters Block granularity Density Reconfiguration time Compile-Time Reconfiguration
(CTR) vs Run-Time Reconfiguration (RTR)
Partial or Total reprogramming
Reconfigurable Devices
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
FPGA SRAM-based Field Programmable
Gate Array Basic block is the Logic Element (LE) Capacity from 1k to 100k LEs Configurable Interconnect Need for optimized CAD or pre-
binded design libraries
Reconfigurable Devices
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
FPGACSL organization: Basic Logic Element:
Reconfigurable Devices
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoCCSoCConfigurable Systems on
Chip RISC processor FPGA block On-chip memories External memories Peripherals DIP switches and connectors Debug support
CSoC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Research on CSoC• PRISM (Brown)• PRISC (Harvard)• DPGA-coupled uP, Raw
processor (MIT)• V-IRAM, GARP,
Pleiades, etc. (UCB)• OneChip (Toronto)• REMARC (Stanford)• NAPA (NSC)
• E5, A7 etc. (Triscend)• Chameleon• Quicksilver• Excalibur (Altera)• Virtex+PowerPC (Xilinx)• PIM Processor (Sun)
CSoC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
CSoC companies Xilinx Triscend
(50% market in PLDs and FPGA)
Altera many others
Triscend and Altera boards available in our lab
CSoC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
The Triscend A7S Board
TA7S20-60Q CSoC SDRAM 32Mb Flash 2Mb Memory sockets 2 serial connectors 7 segment LED Oscillator for CK Debug facilities
CSoC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
The Triscend A7S chip
CSoC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Triscend Fastchip 2.4 FPGA optimized
module library IO Editor Generate file.h Bind (placement
and route) file.csl
Config file.cfg Download
CSoC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Triscend Fastchip modules
CSoC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Co-design and real-time RTOS Booster (Lindh et al.):
hardware fixed-priority scheduler no need for clock tick administration interprocess communication, mutex and
semaphores Beware to bus bottlenecks!
SoC Lock Cache (Lee) Configurable Hardware scheduler (GIT) Online scheduling of Hardware RT tasks to
Partially Reconfigurable Devices (Thiele et al.)
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Hardware RTOS: the RTULindh et al., RTU (Real Time Unit):
- Accelerator Interface- Scheduler Unit- Message, Semaphore and Delay Handler- Intelligent Interrupt Handler- Real-Time Control- General and Technology Dependent Bus Interface
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Drawbacks of centralized computing Moore’s law is going the wrong
way for power consumption A memory access consumes far
more then a CPU local operation Chip area= logic + MEMORY Under 100nm many problems:
Increasing leakage current Difficult interconnect Litho and process variaibility
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Power delivery and dissipation
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Power efficiency
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Road to distributed computing Concurrent programming Compilers that can exploit parallelism High-level debuggers Algorithm for intermediate levels of
granularity (between C++ and HDLs) New benchmarking methods and
metrics (MOPS/$ or MOPS/kg W)
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Cell processor(IBM, Sony, Toshiba)
(from IMEC – Hugo de Man)
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Grazie per l’attenzione!
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
SystemC layers
No notion of time (processes
and data transfers)
Functional verification
Algorithm validation
Cycle accuracy, signal
accuracy
Detailed benchmarking
Microarchitectural analysis
Notion of time (processes and data transfers)
Coarse benchmarking
Architectural analysis
+ formal
+ pin acc.
+ time
+ cycle acc.
+ HW mapping
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
UnTimed Functional (UTF) model
// constgen.h
SC_MODULE(constgen) {
{sc_fifo_out<float> output;
SC_CTOR(constgen) {
SC_THREAD(generating());}
void generating() {
while (true) {
output.write(0.7);
}}}
// adder.hSC_MODULE(adder) {{sc_fifo_in<float> input1, input2;sc_fifo_out<float> output;SC_CTOR(adder) {SC_THREAD(adding());}void adding() {while (true) {output.write(input1.read() + input2.read());}}}
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Timed Functional (TF) model
// constgen.h
SC_MODULE(constgen) {
{sc_fifo_out<float> output;
SC_CTOR(constgen) {
SC_THREAD(generating());}
void generating() {
while (true) {
output.write(0.7);
}}}
// constgen.h
SC_MODULE(constgen) {
{sc_fifo_out<float> output;
SC_CTOR(constgen) {
SC_THREAD(generating());}
void generating() {
while (true) {
wait(200, SC_NS);
output.write(0.7);
}}}
refining
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Bus Cycle Accurate (BCA) model
// euclid.hSC_MODULE (euclid) {sc_in_clk clock;sc_in<bool> reset;sc_in<unsigned int> a, b;sc_out<unsigned int> c;sc_out<bool> ready;void compute();SC_CTOR(euclid) {SC_CTHREAD(compute, clock.pos());watching(reset.delayed() == true);}};
// euclid.cppvoid euclid::compute(){unsigned int tmp_a = 0, tmp_b; // reset sectionwhile (true) {c.write(tmp_a); // signaling outputready.write(true);wait(); // moving to next cycletmp_a = a.read(); // sampling inputtmp_b = b.read();ready.write(false);wait(); // moving to next cyclewhile (tmp_b != 0) { // computingunsigned int r = tmp_a;tmp_a = tmp_b;r = r % tmp_b;tmp_b = r; }}}
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
Register Transfer Level (RTL) model
- RTL level: signal accurate, cycle accurate, resourceaccurate- Can not use abstractions (functional units, communicationinfrastructures, …)
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
RTL adder
// counter.hSC_MODULE(counter) {sc_in<bool> clk;sc_in<bool> load;sc_in<bool> clear;sc_in<sc_uint<8> > din;sc_out<sc_uint<8> > dout;unsigned int countval;void counting();SC_CTOR(counter) {SC_METHOD(counting);sensitive << clk.pos();}};
// counter.cpp#include "counter.h“void counter::counting(){if (clear)countval = 0;else if (load.read())countval = (unsigned int)din.read();elsecountval++;dout.write((sc_uint<8>)countval);}
SystemC
June 24, 2004 Marko Bertogna - Sw/Hw Co-design
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Introduction VHDL SystemC Reconfigurable Devices CSoC
RTL shifter
// shifter.hSC_MODULE(shifter) {sc_in<sc_uint<8> > din;sc_in<bool> clk;sc_in<bool> load;sc_in<bool> LR; // shift left if truesc_out<sc_uint<8> > dout;sc_uint<8> shiftval; //local tempvoid shifting();SC_CTOR(shifter) {SC_METHOD(shifting);sensitive << clk.pos();}};
// shifter.cpp#include "shifter.h“void shifter::shifting() {if (load.read())shiftval = din.read();else if (!LR.read()) { // shift rightshiftval.range(6,0) = shiftval.range(7,1);shiftval[7] = '0'; }else if (LR.read()) { // shift leftshiftval.range(7,1)=shiftval.range(6,0);shiftval[0] = '0'; }dout.write(shiftval);}
SystemC