refSim - a simulation based signal reflection calculator

by Kaushik Patra

Agenda

Why to rebuild reflection calculator

The electrical model

The computational model

User Interface

Tool Architecture

Examples

Implementation challenges

What next ?

Why to rebuild ?Some of us will go into EDA (Electronic Design Automation) industry (like Synopsys, Cadance, even big chip design companies have internal EDA department).

This industry needs people with very good hardware and software knowledge.

This is a very good exercise to learn and experience both hardware and software lessons.

Needs understanding of electrical theory behind signal reflection and how to calculate.

Need computer science knowledge to convert the problem in algorithmic computational domain.

The Electrical Model

Generally the lattice diagram is used.

Since each segment has non uniform delay, lattice diagram calculation becomes complex.

Potential candidate for algorithmic solution.

The Computational Model

The Computational Model

dV

dT

User Interface User will define the PCB trace model in a topology (text) file.

User can also define

cycle time

rise time

fall time

input pulse pattern

simulation resolution

change sensitivity

User Interface

Command line usage is as following

refSim -in <input topology file> [ -chSens <change sensitivity, default 0.001> ]

[ -rtime <rise time, default 0.1 ns> ]

[ -ftime <fall time, default 0.1 ns> ]

[ -ctime <cycle time, default 10 ns> ]

[ -simRes <simulation resolution, default 0.01ns]

[ -bitPat <input bit pattern, default 1]

User Interface

Tool Architecture

Tool Architecture

Example - non uniform delay

Example - non uniform delay

Example - non uniform delay

Implementation challenges

Signal source with configurable rise / fall time.

Implementation challenges

Input voltage pulse train with configurable BIT pattern

0x5A 01011010 and 0x1

right shift(>>)

Implementation challenges

Storage and retrieval of node voltage

Implementation challenges

Event Scheduler Implementation.

‘priority_queue’ of STL has been used

(time,edge) is stored comparing the time.

Need to create own comparator for time.

Signal graph generation

Using GNU plot utility.

Repeat (v,t) points for PWL generation.

(0,0) (2.5,5) (5,10) (2.5,15) (0,20) converted into

(0,0) (0,5) (2.5,5) (2.5,10) (5,10) (5,15) . . .

What Next ?

Extend the algorithm to support complex topologies ( V, tree etc).

Computation model can easily be extended to multiple rows to simulate such complex topology

The primary challenge is to correctly compute the reflection coefficient.

Hopefully some one in next class will pick this up and enhance.

We can even distribute this to others using ‘GNU’ licensing as a ‘class room reflection simulator’