Post on 15-Jan-2022
1
Prin CMPE 413
Se
clk
CL
ciples of VLSI Design Sequential Circuits
quential Circuits
Combinational CircuitsOutputs depend on the current inputs
Sequential Circuits Outputs depend on current and previous inputs Requires separating previous, current and future Called states or tokens Example: Finite State Machines (FSMs), Pipelines
CL
clk
in out
clk clk
CL
PipelineFinite State Machine
2
Prin CMPE 413
Se
elements will be needed
slow tokens
tly one stage per cycle
ciples of VLSI Design Sequential Circuits
quential Circuits
If tokens moved through pipeline at constant speed, no sequencingEx: Fibre-optic cable, called wave pipelining in circuits
However, dispersion is high in most circuitsWe need to delay fast tokens, so that they don't catch up with
Use flip-flops to delay fast tokens so that they move through exac
Inevitably adds some delay to slow tokens
Makes circuit slower than just the logic delayCalled sequencing overhead
Sometimes called clocking overheadBut it applies to asynchronous circuits tooInevitable side effect of maintaining sequence
3
Prin CMPE 413
Se
ciples of VLSI Design Sequential Circuits
quential Elements
LatchLevel sensitiveTransparent latchD latch
Flip-FlopEdge triggeredMaster-slave flip-flopD flip-flop, D register
D
Flop
Latc
h
Q
clk clk
D Q
clk
D
Q (latch)
Q (flop)
4
Prin CMPE 413
Se
ciples of VLSI Design Sequential Circuits
quential Elements: Latch
Pass Transistor Latch
Pros: Tiny Low clock loads
Cons: Vt drop
nonrestoring backdriving output noise sensitivity dynamic diffusion input
D Q
φ
5
Prin CMPE 413
Se
Q
Q
Q
φ
φ
ciples of VLSI Design Sequential Circuits
quential Elements: Latch
Transmission Gate Latch No Vt drop
Requires inverted clock
Inverting BufferPros:
Restoring No backdriving Fixes either:
output noise sensitivityOr diffusion input
Cons: Inverted output
D
φ
φ
D
φ
φ
X
D
6
Prin CMPE 413
Se
φ
φ
Q
φ
φ
QX
φ
φ
ciples of VLSI Design Sequential Circuits
quential Elements: Latch
Tristate feedback
Static Backdriving risk
Static latches are now essential
Buffered Input
Fixes diffusion inputNoninverting
φ
φ
D X
D
7
Prin CMPE 413
Se
φ
φ
Q
X
φ
φ
Q
ciples of VLSI Design Sequential Circuits
quential Elements: Latch
Buffered Output Non backdriving
Widely used in standard cells Very robust (important feature) Rather large Rather slow (1.5 - 2 FO4 delays) High clock loading
Datapath Latch
Smaller, faster Unbuffered input
D
φ
φ
φ
φ
D X
8
Prin CMPE 413
Se
Q
Q
ciples of VLSI Design Sequential Circuits
quential Elements: Flip-Flop
Flip-FlopBuilt as a pair of back-to-back latches
D Q
φ
φ
φ
φ
X
D
φ
φ
φ
φ
X
φ
φ
φ
φ
9
Prin CMPE 413
Se
Latc
h
Q
n
Q
n
g Design
ciples of VLSI Design Sequential Circuits
quential Elements
EnableIgnore clock when enable is inactive
Mux: increase latch D-Q delayClock-gating: increase enable setup time, skew
D Q
Latc
h
D Q
en
en
φ
φ
Latc
hDQ
φ
0
1
en
D
φ e
DQ
φ
0
1
enD
φ e
Flop
Flop
Flop
Symbol Multiplexer Design Clock Gatin
10
Prin CMPE 413
Se
Q
Qφ
φ
φ
φφ
φ
Q
reset
ciples of VLSI Design Sequential Circuits
quential Elements
ResetForce output low when reset is assertedSynchronous vs. asynchronous
D
φ
φ
φ
φφ
φ
reset
D
φ
φφ
φ
φ
φ
Qφ
φ
Dreset
φ
φ
Qφ
φ
Dreset
reset
reset
Synchronous R
esetA
synchronous Reset
Sym
bol FlopD Q
Latc
h
D Q
reset reset
φ φ
11
Prin CMPE 413
Se
Q
set
ciples of VLSI Design Sequential Circuits
quential Elements
Set / ResetSet forces output high when asserted
Flip-Flop with asynchronous set and reset
D
φ
φ
φ
φφ
φ
φ
φ
reset
set reset
12
Prin CMPE 413
Tim
tpd
tcd
thold
cq
tpcq
tccq
tsetup tholdtpcq
tpdqtcdq
th
ts
tp
tp
tc
tp
tc
tp
th
ts
tp
tp
tc
tp
tc
tp
ciples of VLSI Design Sequential Circuits
ing Diagrams
Flop
A
Y
CombinationalLogicA Y
D Q
clk clk
D
QLa
tch
D Q
clk clk
D
Q
tsetup
tc
Latch/Flop Hold Timeold
Latch/Flop Setup Timeetup
Latch D-Q Cont. Delaycq
Latch D-Q Prop Delaydq
Latch/Flop Clk-Q Cont. Delaycq
Latch/Flop Clk-Q Prop Delaycq
Logic Cont. Delayd
Logic Prop. Delayd
Latch/Flop Hold Timeold
Latch/Flop Setup Timeetup
Latch D-Q Cont. Delaycq
Latch D-Q Prop Delaydq
Latch/Flop Clk-Q Cont. Delaycq
Latch/Flop Clk-Q Prop Delaycq
Logic Cont. Delayd
Logic Prop. Delayd
Contamination
propogation delaysand
13
Prin CMPE 413
Se
Flop
clk
Latc
h
φp
φ1
binationalLogic
Latc
h
tnonoverlap
lf-Cycle 1
ciples of VLSI Design Sequential Circuits
quencing Methods
Flip-Flops
2-Phase latches
Pulsed latches
Flip-Flops
Flop
Latc
h
clk
φ1
φ2
φp
clk
Latc
h
φp
φ1 φ2
2-Phase Transparent Latches
Pulsed Latches
Combinational Logic
CombinationalLogic
Com
Combinational Logic
Latc
h
Tc
Tc/2
tnonoverlap
tpw
Half-Cycle 1 Ha
14
Prin CMPE 413
Ma
F2
clk
ciples of VLSI Design Sequential Circuits
x-Delay: Flip-Flops
F1
clk
clk
Combinational Logic
Tc
Q1 D2
Q1
D2
tpd
tsetuptpcq
TC tpcq tpd tsetup+ +=
tpd TC tsetup tpcq+( )−≤
sequencing delay
15
Prin CMPE 413
Ma
c
L3
φ1
CombinationalLogic 2
Q3D3
tpd2
dq2
tp
T
ciples of VLSI Design Sequential Circuits
x-Delay: 2-Phase Latches
T
Q1
L1
φ1
φ2
L2
φ1 φ2
CombinationalLogic 1
Q2D1 D2
Q1
D2
Q2
D3
D1
tpd1
tpdq1
tp
d tpd1 tpd2+ Tc 2tpdq( )−≤=
c tpdq1 tpd1 tpdq2 tpd2+ + +≥
sequencing delay
16
Prin CMPE 413
Ma
(a)
(b)
tpd tsetup tpw−+ + )
tpcq tsetup tpw−+, )
sequencing delay
ciples of VLSI Design Sequential Circuits
x-Delay: Pulsed Latches
Tc
Q1 Q2D1 D2
Q1
D2
D1
φp
φp φp
Combinational LogicL1 L2
tpw
tpw > tsetup
Q1
D2
tpw < tsetup
Tc
tpd
tpdq
tpcq
tpd tsetup
TC max tpdq tpd tpcq,+(≥
tpd TC max tpdq(−≤
17
Prin CMPE 413
Mi
ciples of VLSI Design Sequential Circuits
n-Delay: Flip-Flops
CL
clk
Q1
D2
F1
clk
Q1
F2
clk
D2
tcd
thold
tccq
tcd thold tccq−≥
18
Prin CMPE 413
Mi
tcced by nonoverlap
applies twice each cyclely once for flops
two latches !!!
ciples of VLSI Design Sequential Circuits
n-Delay: 2 Phase Latches
CL
Q1
D2
D2
Q1
φ1L1
φ2
L2
φ1
φ2
tnonoverlap
tcd
thold
tccq
d1 tcd2, thold tccq tnonoverlap− −≥
Hold time redu
Paradox: Hold vs. on
But flops have
19
Prin CMPE 413
Mi
ased by pulse width
ciples of VLSI Design Sequential Circuits
n-Delay: Pulsed Latches
CL
Q1
D2
Q1
D2
φp tpw
φp
L1
φp
L2
tcd
thold
tccq
tcd thold tccq tpw+−≥Hold time incre
20
Prin CMPE 413
Tim
ciples of VLSI Design Sequential Circuits
e Borrowing
In a flip-flop based system
Data launches on one rising/falling edge Must setup before next rising/falling edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges
In a latch-based system
Data can pass through latch when transperent Long cycle of logic can borrow time into the next cycle As long as each loop completes in one cycle
This mechanism is called time borrowing
21
Prin CMPE 413
Tim
Latc
hnal
time acrossge boundary
ycle
φ1
ciples of VLSI Design Sequential Circuits
e Borrowing
Latc
h
Latc
h
Combinational Logic CombinatioLogic
Borrowing time acrosshalf-cycle boundary
Borrowingpipeline sta
(a)
(b) Latc
h
Latc
hCombinational Logic Combinational
Logic
Loops may borrow time internally but must complete within the c
φ1
φ2
φ1
φ1
φ2
φ2
22
Prin CMPE 413
Tim
L2
φ2
Q22
tnonoverlap
tsetup
overlap)
ciples of VLSI Design Sequential Circuits
e Borrowing
Q1L1
φ1
φ2
φ1
Combinational Logic 1D1 D
D2
Tc
Tc/2 Nominal Half-Cycle 1 Delay
tborrow
How much borrowing?
2 phased latches:
pulsed latches:
tborrow
TC2
------- tsetup tnon+(−≤
tborrow tpw tsetup−≤
23
Prin CMPE 413
Cl
F2
clk
al Logic
c
D2
tskew
tsetuptpdq
W
C
C
t
t
ciples of VLSI Design Sequential Circuits
ock Skew
F1
clk
clk
Combination
T
Q1
Q1
D2
CL
Q1
D2
F1
clk
Q1
F2
clk
D2
clk
tskew
tpcq
tcd
thold
tccq
e have assumed zero clock skew
lock really have uncertainty in arrival time
decrease max-delay
increases min-delay
decreases time borrowing
lock Skew: Flip-flops
pd TC tpcq tsetup tskew− −( )−≤
cd thold tccq− tskew+≥
24
Prin CMPE 413
Cl
L3
φ1
CombinationalLogic 2
2 Q3D3
2
p
ciples of VLSI Design Sequential Circuits
ock Skew: Latches
Q1
L1
φ1
φ2
L2
φ1 φ2
CombinationalLogic 1
QD1 D2
phased latches
tcd1 tcd2, thold tccq tnonoverlap tskew+− −≥
tpd Tc 2tpdq( )−≤
tborrow
TC2
------- tsetup tnonoverlap tskew+ +( )−≤
ulsed latches
tpd TC max tpdq tpcq tsetup tpw−+, tskew+( )−≤
tcd thold tccq tpw tskew+ +−≥
tborrow tpw tsetup tskew+( )−≤