Scoreboarding Simulation

Advanced Computer ArchitectureLinda Wills

Animation by: Chris Lee

What is Scoreboarding?

Scoreboarding is a technique used to prevent data and structural hazards. It does this by keeping relevant information stored in a data structure comprising of an instruction queue, a table of function unit status, and a table for register result status.

Properties of Scoreboarding

Large data structure to hold relevant information In-order issue, but out-of-order completion Can issue an instruction when:

All earlier instructions have been issued The needed functional unit is free No other active instruction has the same destination

register (WAW)

Properties of Scoreboarding (Cont)

Reads operands when both become available Executes the instruction when the instruction has

been issued and both operands have been read Writes result to destination register (Rd) after all

pending instructions that have Rd as a source operand have read their operands (WAR).

A Closer Look at Scoreboarding Tables

Three types of tables: Instruction Queue Status

Keeps track of instructions and their progress. Function Unit Status

Keeps track of what hardware is currently in use and what it will need to read from and write to.

Register Result Status Tracks which functional unit is computing a register's value.

Instruction Queue Status

Instruction Queue Status Instruction (Operation, Resultant, Operand1,

Operand2) Issued - has the instruction been issued? Op. Read - are both operands available and have they

been read? Ex. Cmpl. - Has the execution of this instruction

completed yet? Result - Has the result of this instruction been written

back to the register?

Function Unit Status

Function Unit Status List of functional units Busy - Is this functional unit currently executing? Op - Operation is this functional unit performing Dest - Name of destination register Sop1, Sop2 - Source operand 1 and 2 respectively Unit1, Unit 2 - Functional unit currently computing

operand 1 and 2 respectively

Register Result Status

Register Result Status Keeps a list of all registers Keeps a record of which functional unit is computing

the value of this register.

An Example

We have the following program:

LF F6,34(R2)LF F2,45(R3)MULTF F0,F2,F4SUBF F8,F6,F2DIVF F10,F0,F6ADDF F6,F8,F2

Assume the initial state is that the first instruction has completed. The Second LF has just completed execution and is about to write its results.

An Example (Cont)

Suppose we have the following hardware:1 ALU for integer operations (including loads and stores), called 1[i], with a latency of 1 cycle.2 FP multiplication units, 2[*1] and 3[*2], with latencies of 10 cycles each.1 FP addition and subtraction unit, 4[+], with a latency of 2 cycles1 FP division unit, 5[/], with a latency of 40 cycles

1[i] 2[*1] 3[*2] 4[+] 5[/]

1 Cycle 10 Cycles 10 Cycles 2 Cycles 40 Cycles

1. Instruction Status QueueInstruction Issued Op Read Ex Cmpl ResultLF F6,34(R2) X X X XLF F2,45(R3) X X XMULTF F0,F2,F4SUBF F8,F6,F2DIVF F10,F0,F6ADDF F6,F8,F2

2. Function Unit StatusFU Busy Op Dest Sop1 Sop2 Unit1 Unit2 Rdy1 Rdy21[i] Y Load F2 R3 *2[*1] N3[*2] N4[+] N5[/] N

Which instructions can issue? Let’s issue as many as is allowed and fill in the status tables.

Registers: F0 F2 F4 F6 F8FU# 1[i]

3. Register Result Status

2. Function Unit StatusFU Busy Op Dest Sop1 Sop2 Unit1 Unit2 Rdy1 Rdy21[i] Y Load F2 R3 *2[*1] Y Mult F0 F2 F4 1[i] No Yes3[*2] N4[+] N5[/] N

Registers: F0 F2 F4 F6 F8FU# 2[*1] 1[i]

3. Register Result Status

In this step, the MULTF was issued.The changes are noted in Red.

1. Instruction Status QueueInstruction Issued Op Read Ex Cmpl ResultLF F6,34(R2) X X X XLF F2,45(R3) X X XMULTF F0,F2,F4 XSUBF F8,F6,F2DIVF F10,F0,F6ADDF F6,F8,F2

2. Function Unit StatusFU Busy Op Dest Sop1 Sop2 Unit1 Unit2 Rdy1 Rdy21[i] Y Load F2 R3 *2[*1] Y Mult F0 F2 F4 1[i] No Yes3[*2] N4[+] Y Sub F8 F6 F2 1[i] Yes No5[/] N

Registers: F0 F2 F4 F6 F8FU# 2[*1] 1[i] 4[+]

3. Register Result Status

In this step, the SUBF was issued.The changes are noted in Red.

1. Instruction Status QueueInstruction Issued Op Read Ex Cmpl ResultLF F6,34(R2) X X X XLF F2,45(R3) X X XMULTF F0,F2,F4 XSUBF F8,F6,F2 XDIVF F10,F0,F6ADDF F6,F8,F2

2. Function Unit StatusFU Busy Op Dest Sop1 Sop2 Unit1 Unit2 Rdy1 Rdy21[i] Y Load F2 R3 *2[*1] Y Mult F0 F2 F4 1[i] No Yes3[*2] N4[+] Y Sub F8 F6 F2 1[i] Yes No5[/] Y Div F10 F0 F6 2[*1] No Yes

Registers: F0 F2 F4 F6 F8 F10FU# 2[*1] 1[i] 4[+] 5[/]

3. Register Result Status

In this step, the DIVF was issued.The changes are noted in Red.

1. Instruction Status QueueInstruction Issued Op Read Ex Cmpl ResultLF F6,34(R2) X X X XLF F2,45(R3) X X XMULTF F0,F2,F4 XSUBF F8,F6,F2 XDIVF F10,F0,F6 XADDF F6,F8,F2

2. Function Unit StatusFU Busy Op Dest Sop1 Sop2 Unit1 Unit2 Rdy1 Rdy21[i] Y Load F2 R3 *2[*1] Y Mult F0 F2 F4 1[i] No Yes3[*2] N4[+] Y Sub F8 F6 F2 1[i] Yes No5[/] Y Div F10 F0 F6 2[*1] No Yes

Registers: F0 F2 F4 F6 F8 F10FU# 2[*1] 1[i] 4[+] 5[/]

3. Register Result Status

In this step, the ADDF was attempted but not issued. Why was this not issued?

1. Instruction Status QueueInstruction Issued Op Read Ex Cmpl ResultLF F6,34(R2) X X X XLF F2,45(R3) X X XMULTF F0,F2,F4 XSUBF F8,F6,F2 XDIVF F10,F0,F6 XADDF F6,F8,F2

AnswerBecause there is no free floating point adding unit,

this instruction cannot be issued

at this time.

2. Function Unit StatusFU Busy Op Dest Sop1 Sop2 Unit1 Unit2 Rdy1 Rdy21[i] N2[*1] Y Mult F0 F2 F4 Yes Yes3[*2] N4[+] Y Sub F8 F6 F2 Yes Yes5[/] Y Div F10 F0 F6 2[*1] No Yes

Registers: F0 F2 F4 F6 F8 F10FU# 2[*1] 4[+] 5[/]

3. Register Result Status

The Second LF Writes BackThe changes are noted in Red.

1. Instruction Status QueueInstruction Issued Op Read Ex Cmpl ResultLF F6,34(R2) X X X XLF F2,45(R3) X X X XMULTF F0,F2,F4 XSUBF F8,F6,F2 XDIVF F10,F0,F6 XADDF F6,F8,F2

2. Function Unit StatusFU Busy Op Dest Sop1 Sop2 Unit1 Unit2 Rdy1 Rdy21[i] N2[*1] Y Mult F0 F2 F4 * *3[*2] N4[+] Y Sub F8 F6 F2 * *5[/] Y Div F10 F0 F6 2[*1] No Yes

Registers: F0 F2 F4 F6 F8 F10FU# 2[*1] 4[+] 5[/]

3. Register Result Status

The MULTF and SUBF can now read needed operands. The changes are noted in Red.

1. Instruction Status QueueInstruction Issued Op Read Ex Cmpl ResultLF F6,34(R2) X X X XLF F2,45(R3) X X X XMULTF F0,F2,F4 X XSUBF F8,F6,F2 X XDIVF F10,F0,F6 XADDF F6,F8,F2

2. Function Unit StatusFU Busy Op Dest Sop1 Sop2 Unit1 Unit2 Rdy1 Rdy21[i] N2[*1] Y Mult F0 F2 F43[*2] N4[+] Y Sub F8 F6 F25[/] Y Div F10 F0 F6 2[*1] No Yes

The SUBF instruction will complete before the MULTF. The changes are noted in Red.

1. Instruction Status QueueInstruction Issued Op Read Ex Cmpl ResultLF F6,34(R2) X X X XLF F2,45(R3) X X X XMULTF F0,F2,F4 X XSUBF F8,F6,F2 X X XDIVF F10,F0,F6 XADDF F6,F8,F2

Registers: F0 F2 F4 F6 F8 F10FU# 2[*1] 4[+] 5[/]

3. Register Result Status

* *

* *

2. Function Unit StatusFU Busy Op Dest Sop1 Sop2 Unit1 Unit2 Rdy1 Rdy21[i] N2[*1] Y Mult F0 F2 F4 No Yes3[*2] N4[+] Y Add F6 F8 F2

5[/] Y Div F10 F0 F6 2[*1] No Yes

Registers: F0 F2 F4 F6 F8 F10FU# 2[*1] 4[+] 5[/]

3. Register Result Status

The SUBF Writes Results and Frees up FU4, Allowing I4 to be Issued.

The changes are noted in Red.

1. Instruction Status QueueInstruction Issued Op Read Ex Cmpl ResultLF F6,34(R2) X X X XLF F2,45(R3) X X X XMULTF F0,F2,F4 X XSUBF F8,F6,F2 X X X XDIVF F10,F0,F6 XADDF F6,F8,F2 X X

QuestionWhich instruction should finish next?

* *