Post on 08-Apr-2018
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DesignCon 2013
Reliability Modeling of
Electronics for Co-Designed
System Applications
Greg Caswell, DfR Solutions, LLC
gcaswell@dfrsolutions.com 301-640-5825 (o)
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Abstract Complex electronic systems are implemented in a multitude of designs covering all high
reliability market segments, e.g. telecommunications, medical, aerospace, solar, etc. In
many cases, these systems are expected to be exposed to environmental thermal cycling
and moisture over a period of up to 25 years. Fabricators of these systems need to be
comfortable knowing that their designs will meet these aggressive environments. A new
reliability modeling tool has been developed that is being used to predict the failure rate
of the electronics in these systems. This tool provides the designer with the ability to find
and correct design flaws before release of the product, thus avoiding costly failures in the
field. The failure rate is predicted for thermal cycle fatigue of solder joints and plated
through hole vias as well as shorting from conductive anodic filament (CAF) formation.
The tool also produces a finite element analysis of the circuit board(s) showing regions
susceptible to excessive board strain during vibration or shock events. The most value
comes from the ability of the engineers to perform various “what if” scenarios to
determine the impact of any number of design choices.
• What if I change the mount point locations?
• What if I change the via diameters, the spacing, or the copper thickness on the circuit
board?
• What if I change the laminate thickness or material selected?
• What component is at highest risk of failure and what if I change its packaging format?
• What is the reliability impact of changing from SnPb to SAC305 solder?
Finally, once the design has been optimized to satisfy the competing requirements, the
software can be used to predict the rate of failure over the lifetime of the product and this
information used to more accurately plan for the warranty costs. This presentation will
use some specific examples to demonstrate the capabilities and value that this new tool
provides to the electronics industry.
Author’s Biography
Greg is widely recognized as a pioneer in surface mount technology (SMT) and has 40
years of experience in the electronics industry. Currently he is a Sr. Member of the
Technical Staff for DfR Solutions. Previously he was the VP-Engineering for Reactive
NanoTechnologies and VP Business Development for Newport Enterprises.
His experience encompasses all aspects of SMT manufacturing, circuit board fabrication
and materials, advanced packaging, IC fabrication processes and materials, solder reflow,
RoHS, and bonding utilizing specialized nanotechnology.
Greg, a Past President of IMAPS NA, was the National Chairman for the IMAPS
Advanced Technology Workshop program from 1989-2000 and was the Editor in Chief
for Advancing Microelectronics magazine for the past 3 years.
He received his Bachelor of Science in Electrical Engineering from Rutgers University
and also has a Bachelor’s in Management from St. Edwards University in Austin
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Introduction
Any electronic system or assembly is a complex interaction of materials that depends on
the interaction of their various mechanical, thermal, and electrical properties.
It has been demonstrated that the overall cost and quality of a product is most influenced
by decisions made early in the design stage. Finding and correcting design flaws later in
the product development cycle is extremely costly with the worst case situation
discovering design problems after failures occur in the field. Implementing a newly
developed reliability prediction analysis tool will forever change this equation. Before a
single product is built, this valuable new tool enables the engineer to import the design
files and quantitatively predict the life of the product according to the assumptions made
for the user environment.
With margins shrinking in the electronics industry, OEMs depend more on profits from
extended warrantees. Inaccurate life prediction can cut heavily into this income stream.
Under prediction of the failure rate will lead to cost overruns while over estimating
failure will mean lost business to competing extended warranty plans and the setting
aside of funds that could instead be used for further product development. This paper
demonstrates the capabilities and value that this new tool provides to the various
functional units within a electronics design environment where the reliability of the chip,
package, circuit board and system are paramount.
Environmental stresses are also an element of this assessment. They can vary from hand
held units (e.g. cell phones) projected to survive for 2-3 years to solar electronics having
a 25 year life requirement. These more stringent environments can involve:
a. being used at varying temperatures or temperature extremes
c. having a temperature range of -55°C to 125°C
d. being used in an application having a medium to high shock, pressure,
vibration, or moisture environment
e. being stored for later usage (over 10 years)
f. having an application life span of 10 to 25 years
When faced with these daunting product implementation requirements, it is vital to
ascertain whether the product can survive its intended environment as early as possible.
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Common Failure Modes
Wire Bond Failures
Wire bonding has been the most common interconnect for IC packages for over 50 years.
The most common materials are gold, aluminum, and more recently copper. The most
common bond pad material is aluminum. A cross section of a typical wire bond is shown
in Figure 1.
Figure 1 – Cross Section of a Typical Wire Bond.
Wire bonds tend to fail if exposed to elevated temperatures (intermetallic formation),
exposure to elevated temperature and humidity (corrosion) and exposure to temperature
cycling (low cycle fatigue).
Printed Wiring Board Failures
Printed Wiring Boards have several failure modes that are detrimental to reliable
operation. Failures in PCBs can be driven by:
• Size (larger boards tend to experience higher temperatures)
• Thickness (thicker boards experience more thermal stress)
• Material (lower Tg tends to be more susceptible)
• Design (higher density, higher aspect ratios)
• Number of reflow exposures
The failure modes that can typically occur are Conductive Anodic Filament (CAF) shown
in Figure 2, and plated though hole (PTH) Failures which can be driven by voids, etch
pits or fatigue.
Conductive anodic filament (CAF), also referred to as metallic electromigration, is an
electrochemical process which involves the transport (usually ionic) of a metal across a
nonmetallic medium under the influence of an applied electric field. CAF can cause
current leakage, intermittent electrical shorts and dielectric breakdown between
conductors in printed wiring boards.
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Figure 2– Conductive Anodic Filament Failure
PTH voids can cause large stress concentrations, resulting in crack initiation. The
location of the voids can provide crucial information in identifying the defective process;
around the glass bundles; in the area of the resin; at the inner layer interconnects (aka,
wedge voids) or at the center or edges of the PTH. Etch pits are due to either insufficient
tin resist deposition or improper outer-layer etching process and rework. They can cause
large stress concentrations locally, increasing likelihood of crack initiation and large etch
pits can result in an electrical open.
Overstress cracking can occur in the PTH due to a Coefficient of Thermal Expansion
(CTE) mismatch which places the PTH in compression. Pressure applied during In-
Circuit-Testing (ICT) using a "bed-of-nails" can also compress the PTHs.
Circumferential cracking of the copper plating that forms the PTH wall can also occur
which is driven by the differential expansion between the copper plating (~17 ppm) and
the out-of-plane CTE of the printed board (~70 ppm). Figure 3 illustrates these three
failure mechanisms.
Figure 3– Plated Through Hole Failure Mechanisms: voids (left), etch pits (center) and
barrel cracking from fatigue (right)
Wouldn’t it be an ideal scenario if you could determine during the design phase of your
product whether it will survive the intended environments for its projected lifetime
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without incurring any of the noted failure mechanisms? You can accomplish this with
DfRs Automated Design Analysis Tool, Sherlock.
Solder Fatigue Failures
Thermo-Mechanical Fatigue of solder joints is one of the primary wear-out mechanisms
in electronic products. This is especially true in products used outside of commercial/
consumer environments where a longer lifetime is required and more severe operating
conditions exist. Sherlock assesses the fatigue of the solder joints as a function of the
stresses applied during its lifetime and provides insight into whether joints are susceptible
to failure. Figure 4 is an example of a fatigued solder joint on a Ball Grid Array (BGA)
package.
Figure 4 – Example of Solder Joint Fatigue on BGA Package
Sherlock ™ Automated Design Analysis There are several high levels steps involved in running the Sherlock software. They are:
• Define Reliability Goals
• Define Environments
• Add Circuit Cards
• Import Files
• Generate Inputs
• Perform Analysis
• Interpret Results
Reliability Goals
Desired lifetime and product performance metrics must be identified and documented.
The desired lifetime might be defined as the warranty period or by the expectations of the
customer. Some companies set reliability goals based on survivability which is often
bounded by confidence levels such as 95% reliability with 90% confidence over 15 years.
The advantages of using survivability are that it helps set bounds on test time and sample
size and does not assume a failure rate behavior (decreasing, increasing, steady-state).
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Defining Environments
Meaningful reliability predictions must take into account the environment in which the
product is used. There are several commonly used approaches to identifying the
environment. Approach 1 involves the use of industry/military specifications such as
MIL-STD-810, MIL-HDBK-310, SAE J1211, IPC-SM-785, Telcordia GR3108, and IEC
60721-3. The advantages of this approach include the low cost of the standards, their
comprehensive nature, and agreement throughout the industry. If information is missing
from a given industry, simply consider standards from other industries. The
disadvantages include the age of the standards, some are more than 20 years old, and the
lack of validation against current usage. The standards both overestimate and
underestimate reliability by an unknown margin.
Another approach to identifying the field environment is based on actual measurements
of similar products in similar environments. This gives the ability to determine both
average and realistic worst-case scenarios. All failure-inducing loads can be identified
and all environments, manufacturing, transportation, storage, and field, can be included.
In addition to thermal cycle environments, the Sherlock software accepts vibration and
shock input as well. Figure 5 shows representation of this input.
Vibration loads can be very complex and may consist of sinusoidal (g as function of
frequency), random (g2/Hz as a function of frequency) and sine over/on random.
Vibration loads can be multi-axis and damped or amplified depending upon the
chassis/housing.
Figure 5 – Typical stresses that can be addressed in Sherlock
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Import Files
The software is designed to accept ODB++ files which contain all the data for the PCB,
the components, and their locations. The data can also be imported with Gerber files and
an individual bill of materials. Figure 6 shows an example of a PCB stack-up and relevant
data for reliability modeling. The software automatically generates the PCB stack-up,
and its embedded database of over 400 laminate materials having 48 different properties
provides input to the models based on the materials selected.
Parts List
Individual component data is part of the ODB++ file; however, modifications to the data
can be made manually to ensure the physical characteristics of all the components are
accurate. Figure 7(a) shows two examples of the component editor, illustrating the
images of a C-Bend package and a QFN to facilitate selecting the correct package during
an analysis, while Figure 7(b) shows the components laid out on the board.
Figure 6– PCB Stackup with Materials Database
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Figure 7 – Illustration of Component Editor (a) on top and Board layout (b) on bottom
The software can also establish 3D models by creating a mesh structure and the model
from the data input to the analysis. Figure 8 illustrates the mesh construction and Figure
9 a typical 3D image obtained.
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Figure 8 – Mesh Configuration
Figure 9 -3D Image obtained as a Result of Analysis
This information is then processed to obtain the outputs of reliability information from
Sherlock.
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Analyses
Sherlock can currently perform eight different analyses. They are:
CAF – Conductive Anodic Filament Formation
Plated Through Hole Fatigue
Solder Joint Fatigue
Finite Element Simulations
ICT Impact
DFMEA
Vibration Fatigue - Natural Frequencies
Mechanical Shock
The output information from Sherlock can be illustrated in several ways; as an
unreliability curve, a parts list showing the discrepant parts, the physical location, the
overall assessment and the relative rank ordering of the components. Figure 10 provides
examples of the component location and unreliability curves outputs.
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Figure 10 – Failed component Locations (top) and Unreliability Curves (bottom)
Sherlock can also identify areas where natural frequencies impact the product design, as
shown in Figure 11. It can provide a pictorial illustration of the stress locations for each
of the natural frequencies identified. The software can identify up to 10 natural
frequencies.
Figure 11 – Natural Frequencies Identified by Sherlock (1
st-upper left), (2
nd-upper fight),
(3rd
-lower left) and 4th
– Lower Right)
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In addition, Sherlock can provide data regarding the strains applied to the circuit board as
a function of the vibration stress levels. Figure 12 illustrates this data in the XX direction
for the 1st image and YY in the second.
Figure 12 – XX (top) and YY (bottom) Images Illustrating Strain Levels
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WHAT IF ANALYSIS EXAMPLE Figure 13 is a comparison of the solder joint fatigue characteristics for a circuit card
assembly in an avionics application. The left image shows the results for the assembly
with Sn/Pb solder while the right image illustrates the results for a SAC-305 solder
composition. In the Tin/Lead analysis the solder fatigue (green curve) exceeds the 10
year life expectancy identified for the product. However, when a separate analysis was
performed with SAC-305 the green curve shows the solder joint fatigue occurring prior to
the 10 year mark. This comparison analysis was accomplished in less than 5 minutes and
Demonstrated to avionics customer that transition to Pb-free would have a detrimental
impact to product performance.
Figure 13 – Comparison of Sn/Pb and SAC-305 Solder Joint Fatigue in Avionics
Application
In another example, an Industrial controls customer was experiencing failures during
vibration testing. Through Sherlock, DfR was able to rapidly identify optimum location
of additional standoff that altered the natural frequency enough to eliminate the design
issue. Figure 14 illustrates this difference. This “what if” was also done in less than 5
minutes.
Figure 14 – Comparison of Mount Point locations (left image is failing), (right image
after addition of mount point-Passing)
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PRODUCT TEST PLANS Product test plans, also known as design verification, product qualification, and
accelerated life testing (though, these are not the same thing), are critical to the successful
launch of a new product or new technology into the marketplace. These test plans require
sufficient stresses to bring out real design deficiencies or defects, but not excessive levels
that induce non-representative product failure. Tests must be rapid enough to meet tight
schedules, but not so accelerated as to produce excessive stresses. Every test must
provide value and must demonstrate correlation to the eventual use environment (which
includes screening, storage, transportation/shipping, installation, and operation).
The critical first step is a good understanding of the use environment for the product.
How well is the product protected during shipping (truck, ship, plane, parachute, storage,
etc.)? How does temperature/humidity, thermal cycling, ambient temperature/operating
temperature, salt, sulfur, dust, fluids, etc. as well as mechanical cycles (lid cycling,
connector cycling, torsion, etc.) impact the product, particularly in an avionic application.
Followed by the question - Do you have data or are you guessing?
Product test plans are critical to the success of a new product or technology and must be
stressful enough to identify defects and show correlation to a realistic environment. PoF
Knowledge can be used to develop test plans and profiles that can be correlated to the
field. This paper will provide insight into a process to develop viable test plans and a tool
that facilitates the entire process so that minimal testing is performed, thus reducing costs
and schedule impacts.
Figure 15 is an example of how Sherlock was able to provide an appropriate test time and
test condition based on field environment and likely failure mechanism as an input to the
customer for a product qualification plan.
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Figure 15 - Failures Curves on Top and Predicted Test Plan for Validating Data on Bottom
Summary and Conclusions This paper has presented some of the issues associated with electronics reliability and a
tool that can be used during the design phase of a project to mitigate those reliability
issues.
Knowing this information at the design stage permits the designer to make modifications
to the layout such as hold down points, component placement, stiffeners etc. to assure
compliance with the reliability requirements, prior to initiating a prototype manufacturing
run, thus reducing both cost and risk, while simultaneously improving time to market.