Ramon Ramon ChipsChips

Rad-Tolerant design of all-digital DLL

Tuvia Liran [tuvia@ramon-chips.com ]Ran Ginosar [ran@ramon-chips.com ]

Dov Alon [dov@ramon-chips.com ]Ramon-Chips Ltd., Israel

Ramon Chips is named in memory of Col. Ilan Ramon, Israeli astronaut who died on board the Columbia space shuttle, 1/2/2003

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Outline• Issues with analog DLL/PLL• All-digital DLL (ADDLL) architecture• Radiation hardening of ADDLL• Applications of ADDLL• Integration of ADDLL in SOC• Future developments

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Issues with analog PLL

PFD+

CPVCO

/N

clk_refclk_out

Ionizing particle

Issues:- Sensitive to TID of analog- Might un-lock due to SET- Accumulate phase error due to SET- Might miss cycle due to SET- Sensitive to process, voltage, temperature

control voltage

time

time

time

frequency

control voltage

frequency

phase

Discharge by ionizing particle

Missing clock cycle

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All-digital DLL concept• Standard cell based logic

Operates at wide range of process, voltage & temperature

• Timing is controlled by logic• Fast locking / immediate re-locking• Low jitter – typically <1% of CLKREF period

PHD CTRL

DCDL

up

dn

ctrl[m-1:0]

MUL

clkfb

REFCLK

CLK1XCLK2XCLK4X

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DCDL operation

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EN0

IN

OUT

EN1 EN2

Gross tuning of delay

Fine tuning of delay

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DCDL response to control code

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DCDL4 Delay vs code

0.00E+00

2.00E-09

4.00E-09

6.00E-09

8.00E-09

1.00E-08

1.20E-08

1.40E-08

0 50 100 150 200 250 300 350 400 450

Code

Del

ay

slow typ fast up_slow up_fast dn_slow dn_fast

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Radiation hardening of ADDLL

• Key radiation hazards:• TID• SEL• Phase error due to SE• Clock spike due to SET• Reset/re-configure due to SEU/SET

• RH mitigation techniques• The use of RadSafeTM std. cells – immunity to TID &

SEL• Use of SEP flip-flops mitigates SEU – immunity to

change in control• Glitch filtering at each DCDL stage – mitigates SET

spikes• Requirements for double sampling of reset –

mitigates SET in reset/load7

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Advantages of ADDLL• Voltage range – as logic core• Temperature range – as logic core• Lock time – limited # of cycles• Re-locking time – immediate• Standby power – zero• Dynamic power – very low• Bursts of clocks - enabled• Control of slave delay lines - enabled• Area – very small• Floor planning – anywhere in the chip / I/O

strip• Immunity to Soft-Errors - Optional

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ADDLL in RadSafeTM library

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DLCTRDelay controller

PHDPhase

detector

CLKOUT

FBCLK

PHDREF

CTRL_IN ]11:0[

LDEN

REFCLK DCDLDigitally Controlled Delay

Line

DCDLEN

PH ]8:1[

CLK1X

CLK4X

LDB

FCLKEN

BCNT ]11:0[CTRLEN

CLK2X

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All-digital DLL cores• Three DLL cores for 3 frequency

ranges• Locking guaranteed• 0.05 mm2/core• 8 mW/core @0.18u• Highly protected from radiation

effects• Can be placed anywhere in the core• Powered by core supply lines

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ADDLL application – de-skewing

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ADDLLCLKOUT

FBCLK

PHDREF

DCDLREF

CLKTree

REFCLK

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ADDLL application – frequency multiplication

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PHOUT[0]

PHOUT[1]

PHOUT[2]

PHOUT[3]

PHOUT[4]

PHOUT[5]

PHOUT[6]

PHOUT[7]

CLK2X

CLK4X

REFCLK

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ADDLL application – master-slave operation

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R EFCLK

LO C K

ADDLLP HO U T [n-1 :0 ]

C LK O UT

D CD LE NC T R LE NR ST B

CTRL_INCTRL_O UTC T R LS LLO C K

FB C LK

P HD R EF

D CD LR E F

P HO U T [n-1 :0 ] P HO U T [2n-1:n ]

ADDLLP HO U T [n-1 :0 ]

C LK O UT

D CD LE NC T R LE NR ST B

CTRL_INCTRL_O UTC T R LS L

FB C LK

P HD R EF

D CD LR E F

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Other optional applications• Frequency multiplication by

8X/16X…• Frequency multiplication by non 2n

• Duty cycle re-construction• Digitally monitoring of aging/PVT• Operation with bursts of clocks• Frequency hoping

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Record of integrating ADDLLs

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Example of ADDLL (commercial IP)

80µ

140µ

DCDL

PHD

Slave DCDL

CTRL

SlaveCTRL

SYNCDigI/F

•TSMC/0.13u process•200-500MHz input clock•Area: 0.01mm2

•Power: 2mW @1.2V•Located inside I/O ring•DDR2 application

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Summary• ADDLL provides significant advantages over

analog PLL/DLLs• RH ADDLL overcomes the sensitivities of analog

PLLs/DLLs• ADDLL can be used for clock de-skewing and

multiplication, and other applications• RadSafeTM ADDLL is mature and proven