Progress ReportDesign, implementation, experiments, and demo plan

2014/12/03

1

Project GoalStudy the current scheduling

algorithms for homogenous and asymmetric multi-core architecture.

Design and implement the hypervisor scheduler on asymmetric multi-core platform.Assign virtual cores to physical cores for

execution.Minimize the power consumption with

performance guarantee.

2

3

Dom0

VCPU

XenHypervisor

Asymmetry-aware Scheduler

System Architecture

Juno board

Cortex-A53Cortex-

A57

Cortex-A53Cortex-

A57Cortex-

A53Cortex-

A53

DomU

VCPU VCPU

DomU

VCPU VCPU

Main Work ItemsFunctions that fetch physical and

virtual core frequencies and send them to the scheduler.

Implement the asymmetric-aware scheduler on Xen.

5

Dom0

VCPU

XenHypervisor

Asymmetry-aware Scheduler

Implementation - Setting

DomU

VCPU VCPU

DomU

VCPU VCPU

Cortex-A53

Cortex-A57

Cortex-A53

Cortex-A57 Cortex-

A53

Cortex-A53

One A53 core (called “master core”) is

dedicated to Dom0.

6

Dom0

VCPU

XenHypervisor

Asymmetry-aware Scheduler

Implementation - Trigger Scheduling

DomU

VCPU VCPU

DomU

VCPU VCPU

Cortex-A53

Cortex-A57

Cortex-A53

Cortex-A57 Cortex-

A53

Cortex-A53

A timer is set on the master core during the initialization of the scheduler.It triggers the scheduler to

generate plan every interval.

Timer

7

Dom0

VCPU

XenHypervisor

Asymmetry-aware Scheduler

Implementation - Fetch frequency

DomU

VCPU VCPU

DomU

VCPU VCPU

Cortex-A53

Cortex-A57

Cortex-A53

Cortex-A57 Cortex-

A53

Cortex-A53

The scheduler fetches the

frequency of each pcpu and

vcpu before generating a scheduling

plan.

8

Dom0

VCPU

XenHypervisor

Asymmetry-aware Scheduler

Implementation – Scheduler(Cont.)

DomU

VCPU VCPU

DomU

VCPU VCPU

Cortex-A53

Cortex-A57

Cortex-A53

Cortex-A57 Cortex-

A53

Cortex-A53

The scheduler generates a

plan according to the

frequency input, and

assigns vcpus to the run

queue of each pcpu.

Scheduler ImplementationBuild the scheduler based on the

Xen scheduling framework.sched_asym.c

Some Technical DetailsEvery physical core has a run queue.

◦Contains a list of virtual cores, sorted by the start time.

Every virtual core keeps a list of assignment. ◦An assignment contains the information of

target core, start and end time on target core.

The scheduler updates the assignment of each vcpu according to the scheduling plan every time interval.

Example

PCPU 1

PCPU 2

Vcpu 0

Vcpu 2

Vcpu 1 Vcp

u 3

Target core:1Start_time: 20End_time :30

Target core: 2Start_time: 50End_time :60

Target core: 2Start_time: 0End_time :30

Target core: 1Start_time: 0End_time :20

…

…

Time = 0

Example

PCPU 1

PCPU 2

Vcpu 0

Vcpu 2

Vcpu 1 Vcp

u 3

Target core:1Start_time: 20End_time :30

Target core: 2Start_time: 50End_time :60

Target core: 2Start_time: 0End_time :30

Target core: 1Start_time: 0End_time :20

…

…

Time = 20

Vcpu 1 check its next plan_element

Example

PCPU 1

PCPU 2

Vcpu 0

Vcpu 2

Vcpu 1 Vcp

u 3

Target core:1Start_time: 20End_time :30

Target core: 2Start_time: 50End_time :60

Target core: 2Start_time: 0End_time :30

Target core: 2Start_time: 30End_time :50

…

…

Time = 20

Migrate to target core, and sort the run queue according to start time.

Example

PCPU 1

PCPU 2

Vcpu 2

Vcpu 0

Vcpu 1 Vcp

u 3

Target core:2Start_time: 30End_time :50

Target core: 2Start_time: 50End_time :60

Target core: 2Start_time: 0End_time :30

Target core: 1Start_time: 20End_time :30

…

…

Time = 20

Check if the next vcpu in the queue can start

Experiment Setting Juno board

◦1 Dom0: 1 virtual core Xen

◦2 DomU: 1~4 virtual core(s) VM(s) running benchmarks/applications.

Probe◦Hardware: Juno Probe◦Software: Linaro Power Probe

Execution ScenarioSame as the simulation scenarios

in GCCE 2014 paper.◦Case 1: two virtual machines with

light workload.◦Case 2: one virtual machine with

heavy workload, the other with modestly workload.

Benchmark◦CoreBench