Porting & Scaling Strategies for Nanoscale CMOS RHBD

5/18/2015SEE/MAPLD

Robert Shuler

robert@mc1soft.com+1-281-413-7713 cell

http://mc1soft.com/papersSee full paper at above URL for explanation of charts

Robert Shuler has 42 years of experience in aerospace & avionics fault tolerant systems design with NASA, and MSEE (Rice) and BSEE (Miss. State U.) degrees. He has half a dozen patents, and publications in fields ranging from economics (corporate risk compensation,

the equity premium) to physics (inertia & quantum gravity). He lives in Texas with his wife Natasha, and has written books on The Equity Premium Puzzle, Money, Wealth & War, and crash rate theory (Economic Optimization of Innovation & Risk).

Human spaceflight 20-year needs• high speed, low power and highly complex

integrated circuits to support manned missions assisted by intelligent subsystems• find landing sites in real time . . . . . . . . . . . . at night!• large scale multi-core integrated circuits• Incremental design over long periods• Specialized commercial applications

may share similar need to protect design investment

Problems . . .

• Vendors consider ONLY mass-consumer applications• Older RHBD techniques, and weaker technique, are

in-vogue for hi-reliability commercial applications• University programs emphasize the weaker

techniques to get grants and jobs for graduates• As susceptibility increases, space applications need

more robust techniques• Need to research and adopt new techniques derails

notion of incremental progress toward distant goals• Cost of porting to new processes growing very large

5 techniquesfor addressingthese issues:

1. 10-cell library

• NAND/NOR functionsare regular & easy

• Most effort spent onMUX/XOR/various FF

• Use MUX for FF, XOR• INVZ = Guard Gate/TAG• FF variations with external

gates costs very little• Regular and RHBD mux/lat• Delay SET filter not viable

much longer

2. Multi-parameter scalingN

WEL

L

P+

P+

N+

N+

diffu

sion

(acti

ve)

M1

M2

N guard ring

P guard ring

Vdd • Replaceable sub-cells for exactsize CONTACT and VIA1/2

• Max of minimum space-extensionrounding up to nearest lambda

• Pick “lambda” for drawing metal &diffusion rather than gates

• With few cells, adjust gate lengthsmanually

• DRC subset for 12 base cell layers

• Copy with layer map to vendorsetup for full DRC, routing, verification

3. Critical Node Separation

• Quest for smallest DICE layout obscures its “dual interlocked” history

• Re-layout single cell for node separation undone by one generation

• DICE, SERT, TAG4 share same topology• DICE has most missing transistors, weak• Dooley cell = TAG4 off patent as of 2015• Half-cell layout for arbitrary separation

Critical Node Separation – cont’d• Dooley-TAG4 2-1 MUX cell• Half of RHBD latch• Compact layout with

conventional mux setup

Dooley-TAG4

Standard MUX

4. Compact Voting Latch• Based on TAG/Guard Gate• Single gate votes 3 things:

– it’s current output node state– input A– input B

• Setting output node does not cause node fights– sim’d all cases– regular gate won’t even work in this configuration

• Use conventional 2nd FF stage for TOTAL of 3 interconnects vs. 8!

• Same size as conventional DFF

Traditional voting latch – 22T

Compact Voting Latch (CVL) – 8T

CVL DFF

5. Automatic interlock/voting

• Top/bottom of blocks for signals(was already author’s block convention)

• Left/right for coupling ports• Connection by placement• Blocks are identical• #1 of each triad is primary inside block• Ports rotate 1→3, 2→1, 3→2• Blocks could be dynamically configurable

Results – library layoutNote: PAD buffers will be about as much work as the base library

Results – baseline for comparisonConventional TMR with mixed routing:33% inefficiencyno better than dual rail(just different sensitive angles)Even at 180 nm!

Results – single string vs. CVL TMR• About 10% above theoretical minimum (3x) with Tanner router, 65 nm generic• Horizontal routing channels available for full row abutment (green rectangles)• 7 nm critical node spacing would be ~3 mm, up to 10 mm with low aspect ratio

Conclusions & further information• Combination of techniques should work into 7 nm region• Designs probably supportable/evolvable for 20 years (through Mars)• Likely migrate to commercial use in far future just as existing RHBD has• For full paper or author contact

http://ShulerResearch.wordpress.com

Also of interest to high-reliability community:Economic Optimization of Innovation & Risk