1

Module Introduction

PURPOSE:The intent of this module is to provide an overview of the MPC5200.

OBJECTIVES:- Identify the MPC5200 Block Diagram- Identify the MPC5200 Target Markets- Describe HiP7 Technology- Describe Core Features- Describe System Level Features

CONTENT:- 28 pages- 5 questions

LEARNING TIME:- 55 minutes

The intent of this module is to provide you with an overview of the MPC5200 microcontroller. You will become familiar with the MPC5200 and its target markets. You will also learn about the composition of the MPC5200 by studying its block diagram. Finally, you will explore the core and system level features of the of the MPC5200.

2

MPC5200 Overview

Designed with automotive/telematics applications in mind

Runs at higher clock, bus, and CPU speeds

Handles a tremendous range of applications

Welcome to the MPC5200. This processor provides very high performance in automotive and other embedded environments. This device has been designed with automotive and telematics applications in mind.

What is new about the MPC5200? Generally, automotive class processors have not run at the clock speeds seen in the MPC5200. The external bus speeds of this device are up to 132 MHz and the internal execution speed for the CPU is up to 400 MHz. This provides the horsepower to do voice recognition, graphics processing and wireless communications.

The MPC5200 is not just for automotive applications. In fact, this device will handle a tremendous range of applications. This is mainly due to the wide range of communications peripherals and timers, as well as the processing power provided by the 603 G2_LE core that uses the PowerPCTM instruction set.

3

BESTComm

BESTDMA

XLB

BestComm

BestDMA

PowerPC 603e Core

16KICache

32 EntryMMU

16KDCach

e32 Entry

MMU

FPU

603 G2_LE Core

16KICache

32 EntryMMU

16KDCache

32 EntryMMU

FPU

IPBI

PCI Controller

ROM/SRAM

ATA/IDE Host Controller

JTAG

PCI Controller

ROM/SRAM

ATA/IDE Host Controller

JTAG

PSC1 PSC2 PSC3PSC1 PSC2 PSC3 SPI 10/100BaseT

I2C(Two)

CAN 2.0A/B

(Two)SPI 10/100

BaseTI2C

(Two)CAN 2.0

A/B(Two)

Systems Integration Unit

System Functions

Real Time clock

Chip Selects (6)

MemoryController

(DRAM) Interrupt Control

USB(Two)

Systems Integration Unit

System Functions

Real Time clock

Chip Selects (8)

MemoryController

DDR or SDR

SDRAM Interrupt Control

USB(Two)

PSC4 PSC5 PSC6PSC4 PSC5 PSC6

IP Bus

16kB

DPR

AM

J1850

Comm bus

MPC5200 Block Diagram

Here you can see an MPC5200 block diagram. This microcontroller is composed of the 603 G2_LE processor core, many internal modules, several internal busses, and two external busses.

At the heart of the microcontroller is the 603 G2_LE core. The processor core can access all of the internal modules.

BestComm, an intelligent Direct Memory Access (DMA) controller, is capable of moving data between various sources and destinations. Many times, the BestComm controller can move data between one of the peripheralelements and memory on either the LocalPlus or SDRAM bus withoutinterfering with the CPU’s fetching of instructions.

There is a wide range of communications modules that provide different communication formats. This course will provide you with an understanding of all the internal bus structures, the internal peripheral modules, the CPU core, the BestComm controller and the external bus structures.

4

SmartComm

SmartDMA

XLB

BestComm

SmartDMA

PowerPC 603e Core

16KICache

32 EntryMMU

16KDCach

e32 Entry

MMU

FPU

603 G2_LE core

16KICache

32 EntryMMU

16KDCache

32 EntryMMU

FPU

IPBI

PCI Controller

ROM/SRAM

ATA/IDE Host Controller

JTAG

PCI Controller

ROM/SRAM

ATA/IDE Host Controller

JTAG

PSC1 PSC2 PSC3PSC1 PSC2 PSC3 SPI 10/100BaseT

I2C(Two)

CAN 2.0A/B

(Two)SPI 10/100

BaseTI2C

(Two)CAN 2.0

A/B(Two)

Systems Integration Unit

System Functions

Real Time clock

Chip Selects (6)

MemoryController

(DRAM) Interrupt Control

USB(Two)

Systems Integration Unit

System Functions

Real Time clock

Chip Selects (8)

MemoryController

DDR or SDR

SDRAM Interrupt Control

USB(Two)

PSC4 PSC5 PSC6PSC4 PSC5 PSC6

IP Bus

16kB

DPR

AM

J1850

Comm bus

MPC5200 Block DiagramSDRAM BUS

LOCALPLUSBUS

The MPC5200 has a very high level of integration. There are two external data/address bus structures, the SDRAM bus and the LocalPlus bus. The LocalPlus bus can perform normal memory accesses, Advanced Technology Attachment (ATA) cycles, and Peripheral Component Interconnect (PCI) cycles.

There is a wide range of peripherals that provide for many different types of serial communications. For instance, there are six Programmable Serial Controllers, a Serial Peripheral Interface, 10 and 100 Mbit Ethernet, J1850, two I2C modules, two MSCAN modules and two USB channels.

In the System Integration Unit, there is a Real Time Clock, the Interrupt Control Logic, the Chip Select Logic, and an 8 channel Timer module. Click “MPC5200 Features” to learn about the main features of the MPC5200 microcontroller.

5

MPC5200 FeaturesFeatures

• 603e series PowerPC Core16K Instruction and 16K Data CachesDual 32 Entry MMUs

• High Speed SDRAM interface256Mbyte addressing range, 32-bit wide (per Chip Select Line)2 Chip selects

• Flexible multi-function external busPCI master v2.2, ATA v4 compatibility

• SmartComm I/O subsystemSupport for PSC, Ethernet, PCI, ATA, IrDA, I2C, AC97, SPI on PSC, LPC16kB internal SDRAM

• 6 Peripheral Serial ControllersUART, AC97, I2S ( PSC1-3+6)

• Superior system integration for DISCAN, Serial, USB, J1850

Power Management• Nap, Doze + Sleep modes• Deep Sleep

Package• 272 pin PBGA, 1.27mm pitch

Reference info for previous page

6

MPC5200 Target Markets

Gateways and Network Edge Devices (Ethernet and USB)Industrial Control (Ethernet and CAN)Video Detection & Biometrics Processing Electronic and Medical InstrumentationGPS ProcessingTelematics and Automotive (CAN, J1850)

The MPC5200 can be used in a wide range of target markets. Because it is manufactured in HiP7 (or HiPerMOS7) technology, the device yields very high speed circuitry with very small die size. In other words, this device presents a very attractive price to performance ratio.

The 603 G2_LE core implements the PowerPC™ instruction set. Along with the internal Floating Point Unit and high speed internal clock speed, the MPC5200 can handle high speed communications tasks, video, Global Positioning, and other jobs that require significant processing power.

7

Question

Indicate whether the sentence below is True or False.

The MPC5200 can be used in a wide range of target markets. Because it is manufactured in HiP7 technology, this device is very high speed with very small die size.

• True

• False

You have just learned a bit about the MPC5200. Now let’s review some of the material we have covered so far with a question.

Answer:The MPC5200 is used in a wide range of target markets. It is very high speed with a small die size. This means that this device presents a very attractive price to performance ratio.

8

Compiler :CodeWarrior www.Freescale.com

Debugger : Abatron probe http://www.abatron.ch/Lauterbach probe http://www.lauterbach.comIsystem http://www.isystem.com

Operation systems :QSSL QNX http://www.qnx.comOSE systems http://www.ose.com/prodserv/esp/OSEK www.Freescale.com

Evaluation boards :Total5200 Development PlatformLite5200 Evaluation Board a general market EVM system (March 2002)Windriver, Lineo.

Development tools today

Now let’s look at development tools. You can find information on the latest tools such as compilers, debuggers and operating systems at the web sites listed above. Future developments partnerships include Wind River and Lineo.

9

Lite5200 Evaluation Board (EVB)Best in Class Total5200Development Platform

Committed RTOS/SW Support•CodeWarrior Compiler/Debugger•Freescale Linux Solution•QSSL QNX•Green Hills Integrity•Wind River VxWorks•MontaVista Linux•IBM Websphere/J9

Application SW Support•Bluetooth SW Stack•Voice Rec/Text to Speech •AEC/Noise Suppression•PowerPC Applications

Emulation HW SupportAbatron, Lauterbach, PowerTap

EVB/Development Platforms

Here you can see images of the Total5200 Development Platform and the Lite5200 Evaluation Board (EVB). Support for the 5200 series chips are outlined in the graphic. You can see this includes software application and emulation support.

10

400 MHz Lite5200 Board• 160mm x 133mm • 64 MB SDRAM, 8 MB Flash

(Can support 16 MB Flash in future)• PC104+(PCI), ATA• CAN (2), USB, I2C (2)• 1UART• 10/100 Ethernet• All additional MPC5200 I/O available on

header connector• No MOST, LCD Controller, Head Unit,

Audio Subsystem• No Integrated 12V Power Support

Lite5200 Software• CodeWarrior 30-day Eval Seat• dBug - low level debugger & boot loader• Evaluation copies of Green Hills, MontaVista,

QNX and Wind River• Available July, 2003

Lite5200 EVB

Reference info for previous page.

11

400 MHz Total5200 Development Platform• Base unit - 1 DIN Form Factor• 120VAC or 11-14VDC• 64MB SDRAM, 64MB Flash• PC104+(PCI), ATA• 2 CAN, MOST, 2 USB, I2C• 9 UARTs• LCD controller w/ VGA & S-Video (Epson S1D13806)• 10/100 Ethernet• Audio Inputs/Outputs supporting Mic, Bluetooth, Radio,

Phone & Speaker.Total5200 HeadUnit• Detachable, Graphics Touchscreen• Reconfigurable buttons

Evaluation Software/Tools• CodeWarrior• QNX Momentics and IBM WebSphere/ J9 JVM• Green Hills, MontaVista, Wind River evaluation BSPs

being planned• dBug - low level debugger & boot loader• Available July, 2003

Mic

1

Line

1 (D

SP)

Mic

2

RS-232

Line

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3 (V

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Rad

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CRT

S-Video

BigFoot

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Total5200

Reference info for previous page.

12

HiP7 Technology

Is Freescale’s densest, highest performance, most modular, and lowest power System-on-Chip platform process to date

Contains minimum features of 0.065 micron

Enables system-on-chip solutions for applications spanning low power wireless to high performance networking and computing products.

Provides a means to manufacture complex chips that are economically feasible

Now let’s look at HiP7 technology in more detail. The HiP7 is the 0.13 micron Complementary Metal Oxide Semiconductor (CMOS) platform technology.

HiP7, the latest development in continuous scaling of CMOS process technology, is commonly referred to as 0.13 micron. However, it contains minimum features of 0.065 micron.

HiP7 processing technology enables system-on-chip solutions for applications spanning low-power wireless to high-performance networking and computing products.

HiP7 wafer processing technology produces very high-speed chips with sub-micron devices. This advanced technology provides a means to manufacture very complex chips but at a die size that makes these chips economically feasible.

13

MPC5200 Chip Floor Plan

This is a floor plan of the MPC5200. It shows the relative sizes of the various modules. The 603 G2_LE Core is the largest module followed by theBestComm controller.

The BestComm controller is the next most power-hungry area. However, the serial ports and other modules draw less power than their overall area might suggest.

The clock source to each individual module can be enabled or disabled. It is possible to save some power by turning off the clock source to a particular peripheral element.

14

Physical Layout

A picture of the MPC5200 is presented here. This photograph is a visual representation of the floor plan presented previously. The darker areas represent a high transistor count. Obviously, the memory areas are most dense because they are regular structures. The peripheral elements are less dense, because of large sections of random logic.

15

Question

Ethernet10/100

MSCAN

Label the MPC5200 chip floor plan by dragging the letters on the left to their correct location on the right and click Done.

PSC1CDMJ1850

GPIO

IPBI

GPIO

WKP

XLBARB

RTC

PSC2

PSC3

LPC ATA

PSC4

PSC5

PSC6

SLT

MBI PCIARB MBI

MBISTIR

SDRAMSPI

GP TIMERS

INT CNTL

IPBI Mux

I2C

Done Reset Show Solution

A

B

C

D

603 G2_LE Core

BestComm

PCI

A

D

C

B

USB

Here is a question to check your understanding of the material presented so far.

Answer:The first module of the MPC5200 chip floor plan is the 603 G2_LE Core. The second module is Ethernet. The third module is PCI and the fourth module is BestComm.

16

Audio

64MBFlash

LCDCtl

UART

MOST

12VTransc

RS232Transc

CANTransc

USBTransc

10BTTransc 128MB

SDRAM

IrDATransc AT

A

PC104+

CPL

D3V

/5V

LocalPlus

PCI

eBus

AC’97

MPC5200MPC5200

System Block Diagram

This system block diagram represents a typical system. The MPC5200 can interface to CAN, ETHERNET, USB, CODECs, UARTs, and other serial interfaces.

One of the external busses, the LocalPlus bus, is used to drive FLASH, static RAM, and external peripherals. Although program execution is possible on the LocalPlus bus, the majority of program execution is over the SDRAM Bus.

Connecting DRAMs to the LocalPlus Bus would require significant external interface circuitry and is not a recommended design practice. The external SDRAM bus interface is specifically designed to interface to Single Data Rate and Double Data Rate Synchronous Dynamic Random Access Memories (SDR SDRAM and DDR SDRAM).

17

MPC5200 System

SRAM

SRAM

The LocalPlus Bus in this system is connected to Static RAM, Video and Audio Peripherals, and other non-volatile memory.

The LocalPlus bus can run ATA cycles, which are primarily used for disk drives. It can also run PCI cycles. Since program execution always begins on the LocalPlus bus, it is imperative that some type of non-volatile memory be on the LocalPlus Bus.

The SDRAM bus is connected to SDR or DDR SDRAM.

The internal peripheral ports are shown connected to various external devices. The Programmable Serial Controller (PSC) Ports can be connected to a variety of different devices. For instance, the PSC Ports can connect to AC97 devices, CODECs and UARTs. Other ports, such as Ethernet, USB and MSCAN require a physical interface to connect to their respective transmission media.

18

MPC5200 Package

At the present time, the MPC5200 is available in a 272 pin ball grid array package. This package is economical to make and has good thermalcharacteristics.

19

MPC5200 Pin Out Diagram

The pin outs for the MPC5200 are shown here. Among other things, there are three power busses, the CPU core that runs at 1.5 volts, theInput/Output (I/O) that runs at 3.3 volts, and the SDRAM bus that can run at either 2.5 volts or 3.3 volts.

The power pins for each respective bus are internally connected. However, it is most important that all power and ground pins be externally connected to their respective sources.

As a word of caution to circuit designers, it is very important to make sure that all pins are accessible in initial designs. Some board level designers have routed unused balls to inaccessible pads on the PC board. This invariably leads to bad things. It is much easier to route all the balls to accessible pads than to rework a board later.

At least for initial designs, bringing the debug pins to a COP/JTAG header is very important. Some engineers believe that bringing the debug pins to an external header will make it easier for someone to dump the system code. However, this will only present a minor delay to a clandestine attempt by someone wishing to dump the system code. The advantages of being able to debug a circuit, even one that has been in production, far out weigh any issues associated with clandestine attempts to read the system code.

20

Question

• Complete the following sentence.

• “Connecting _________ to the LocalPlus Bus would require significant external interface circuitry and is not a recommended design practice.”

– FLASH

– DRAMs

– ROM

– Static RAM

Here’s an opportunity to see if you can remember what you learned about the system block diagram.

Answer:Connecting DRAMs to the LocalPlus Bus would require significant external interface circuitry and is not a recommended design practice. The external SDRAM bus interface is specifically designed to interface to SDR and DDR SDRAMs.

21

603 G2_LE Core Features

Super Scaler Architecture0 – 400 MHz static operation (-40 to 85 C)0 – 230 MHz static operation (-40 to 105 C)760 MIPS @ 400 MHz430 MIPS @ 230 Mhz

At the heart of the microcontroller is the 603 G2_LE CPU core that has super scaler architecture. This core implements the PowerPC instruction set.Each instruction is 32-bits wide.

The initial targets for CPU performance are 0 – 400 MHz operation for –40 to + 85ºC operation and 0 – 230 MHz operation for –40 to + 105ºC operation.

The MIPS ratings for 400 MHz operation is 760 MIPS. The MIPS ratings for a 230 MHz operation is 430 MIPS. The MIPS rating for this processor is greater than the CPU clock rate because of double instruction dispatch.

Recall that the external SDRAM bus is 32-bits wide. Therefore, only one instruction can be fetched per memory access. However, the 603 G2_LE core has a 64-bit wide bus. This is the same width as the internal instructioncache. Therefore, when the processor is fetching from cache, twoinstructions can be issued per clock cycle. Note that it is not always possible to issue two instructions because of data dependencies, busy execution units and changes of flow.

A data dependency is created when the instruction waiting to be issued has to wait on the results of an instruction that is further ahead in the instruction pipeline. In the case of the Floating Point Unit (FPU) , only one double precision instruction can be issued for each two clock cycles. In the case of a flow control instruction, such as a branch or jump, instruction pipeline flushes will occur. In this case the Instruction Pipeline must refill before an instruction can be issued to an execution unit.

Memory speed also has an effect on MIPS ratings. As the speed of the SDRAM bus is increased, the external memory might require that a Wait State be inserted. This would have the effect of slowing the bus down. As long as the external memory can handle increased bus speed without

22

603 G2_LE Core Features

Double Precision FPU16 Kbyte Instruction Cache16 Kbyte Data CacheInstruction and Data MMUStandard & Critical Interrupt Capability

The 603 G2_LE core contains an instruction cache, a data cache, an instruction memory management unit and a data memory management unit. The core also contains a Double Precision FPU. These elements are critical in enhancing the performance of the CPU.A Cache Memory is a small, specialized memory that is organized in rows. Each row of the 603 G2_LE core instruction cache contains four instructions. This memory is generally integrated into the CPU core. The CPU is able to fetch instructions from the cache using the shortest possible memory cycle. The cache is designed to issue instructions at a sufficient rate so that no CPU pipeline stalls will occur. Each time that the CPU attempts to fetch an instruction that is not in cache, the cache controller will fetch enough instructions from the external memory to fill an entire cache line.When a cache memory is designed, the system designer must take into account how many instructions will probably be executed in consecutive order. In general, the number of instructions held in each row is a power of 2. Therefore, rows could be 2, 4, 8, 16, 32, etc., instructions wide. The probability of 2 instructions being executed in consecutive order is very high. The probability of 4 instructions being executed in consecutive order is still high but not as high as for just 2 instructions. Likewise, the probability of executing 8 consecutive instructions is less than for 4 and so on. So, when the CPU attempts to fetch an instruction that is not in cache, the cache controller fetches enough instructions to fill an entire cache line. The goal is to balance the number of instructions fetched with the probability that all of the instructions will be executed.The 603 G2_LE core supports different types of interrupts. The major types of interrupts are CORE Interrupts, System Management Interrupts and Standard Interrupts. Critical Interrupt sources are BestComm, IRQ0, Slice Timer 0 and CCS Wake UP. System Management Interrupt sources are Slice Timer 1 and Programmable Interrupts. Standard Interrupt Sources are Programmable Interrupts.As a note of caution, if any external interrupt is enabled (IRQ0 – IRQ3), IRQ0, which is the non-maskable interrupt, will be enabled and it cannot be masked. Therefore, it is necessary for the system designer to make sure that IRQ0 will be appropriately driven. That is, IRQ0 should never be allowed to float.

23

603 G2_LE Core Features

CompletionUnit Dispatch

Unit

BranchUnit

IntegerUnit

GenRegFile

Load/StoreUnit

I MMUD MMUData Cache Inst. Cache

Bus Interface Unit

System Bus

32bAddress

32/64bData

GenRe-

name

FloatingPointUnit

FPURegFile

• Two instructions per clock cycle

• Instruction Cache & Data Cache

– LRU replacement

The MPC5200 603 G2_LE core is the brain of the system and instructions are executed here. However, raw clock speed is not a particularly good indicator of how many instructions per unit time can be processed. From a mathematical standpoint, the core can execute a sustained rate of two instructions per clock cycle. However, there is much more to it than that. The instructions have to come from somewhere and they have to be delivered to the CPU core. In truth, even though this is a RISC architecture, instructions are fed to the CPU core through a pipeline that has several stages. If the processor was fed just one instruction and told to execute that instruction before fetching another one, several cycles would elapse between fetching the first instruction and seeing its completion. RISC machines can really fetch an instruction on each clock cycle. Thus, if only INTEGER instructions were being fetched, it is possible during each cycle that we would see two instructions fetched and two instruction retired. However, this is not always the case because of data dependencies. In addition to the CPU’s speed, the Data and Instruction Caches play a very major role in overall processor throughput. When the processor can execute instructions that are already in cache, the processor can execute at the maximum possible speed. It is the job of the Bus Interface Unit to make sure that instructions get into cache as the processor needs them. Of course, this is not always possible. When the processor attempts to fetch an instruction that is not in cache, the Bus Interface Unit must go fetch the instruction from external memory, fill an entire cache line, and then let the CPU get on its way. By having relatively large cache memories, the frequency of cache “misses” will be less and the processor can continue to process instructions at its maximum rate. When the Instruction Cache is full and the CPU requests an instruction that is not in the Instruction Cache, a Least Recently Used (LRU) algorithm chooses the Cache Line to be replaced.As a note on definitions, to issue an instruction means that the instruction has been fetched from the cache and put into the instruction pipeline of the processor. It is possible to issue two instructions per clock cycle.To retire an instruction means that the instruction has been completely executed and that no instructions are waiting on the result of that instruction. For instance, a read of external memory is considered as completed as soon as the memory transaction is handed to the Bus Interface Unit. However, the actual memory transaction may not complete for several cycles. Other instructions can be issued as long as they do not need the results of the preceding memory transaction. However, the instruction that created the memory transaction cannot be “retired” until the memory transaction it started is complete. The reason for keeping a history of instructions is in the case of a memory transaction error. When this occurs, the operating system can try to make a graceful recovery and perhaps retry the instruction. The major point to be learned here is that memory management units, cache memory structures, and a well designed bus interface unit materially affect the throughput of the CPU.

24

Core Features

Features Superscalar• up to 3 Instructions issued & retired per clock• up to 4 Instructions in execution per clock• single cycle execution for most inst.

Four independent execution units• BPU , IU, LSU and system register unit

16k Instruction cache & 16k Data cache• four way set associative • physically addressed• LRU replacement

Data MMU and Instruction MMUDouble precision FPUOn chip debug support (JTAG/COP)

Reference info for previous page.

25

Core Features

System Bus

Integrated Peripherals

CompletionUnit

DispatchUnit

BranchUnit

IntegerUnit

Load/StoreUnit

I MMUD MMUData Cache Inst. Cache

Bus Interface Unit

FloatingPointUnit

FPURegFile

Integrated Peripherals

Integrated Peripherals

Internal 603e bus

Gen Purpose Reg. File

The MPC5200 603 G2_LE core, designed in HiP7 processing technology, runs on 1.5 volts. This provides a core that dissipates significantly less power than cores running at higher voltages. The I/O functions run at 3.3 volts. The SDRAM bus can run at 2.5 volts or 3.3 volts. The voltage depends on the exact type of memory being used. Generally, 2.5 volts is used to accommodate DDR SDRAM.

26

More Features

603 G2_LE processorMapped to a reusable coreGreater than 400 MHz clock speedLower power with reduced core voltage (1.5V)Select enhancements to the core for embedded market applications• critical interrupt

System integration independent test environment

Reference info for previous page.

27

603 G2_LE Core FeaturesProgrammable static branch prediction

Independent with feed-forward, reduces data dependencies in hardware

Zero cycle branch capability (branch folding)

Capable of fetching two instructions/clock from the cache

Six-entry instruction queue w/lookahead capability

A 64 entry, two way set-associative data and instruction lookaside buffers (DTLB/ITLB)

Cache write-back or write through operation programmable on a per page or per block basis

The 603 G2_LE core has incorporated many features that improve its processing performance. For instance, branch prediction is programmable. This is a feature that allows the processor to act as though a conditional branch is always going to take the branch or never take the branch. By assuming that the branch will always take one path or the other, the CPU core can work more efficiently. If the assumption is wrong, there is a penalty to be paid in that the CPU has to back up and run the branch instruction a second time. However, if the prediction is right most of the time, then the penalty for being wrong occasionally is not a high price to pay.

Feed-forward is another feature that increases processor throughput. When two consecutive instructions are in the instruction pipeline and the second instruction needs the result of the first instruction, feed-forward allows the result of the first instruction to be used on the next clock cycle by the second instruction. Normally, the first instruction would have to write its result to a General Purpose Register before the next consecutive instruction could use the result. This speeds up instruction flow by one cycle. However, one cycle is enough to execute an integer instruction.

Examine the green box to see more features of the MPC5200 603 G2_LECore.

28

QuestionMatch the MPC5200 603 G2_LE core feature to the correct voltage.Drag each item on the left to its corresponding box on the right and then click Done.

A

B

C

D

SDRAM bus

603 G2_LE core

DDR SDRAM

I/O functions 2.5 volts or 3.3 volts

1.5 volts

2.5 Volts

3.3 voltsA

D

B

C

Done Reset Show Solution

Here’s a question on MPC5200 603 G2_LE core features.

Answer:The MPC5200 603 G2_LE core, designed in HiP7 processing technology, runs on 1.5 volts. The I/O functions run at 3.3 volts. The SDRAM bus can run at 2.5 volts or 3.3 volts. The voltage depends upon the exact type of memory being used. Generally, 2.5 volts is used to accommodating DDR SDRAM.

29

Programming Model

MBAR reg.SPR 311

Two new exept. Reg.

CSSR0CSSR1

Now let’s look at the programming model of the 603 G2_LE core. The 603 G2_LE core adds several new features to the base core. There is an MBAR register that is used to point to the registers that control the peripheral elements, such as the UARTs or CAN modules.

Here, you can see there are two new exception registers, CSRR0 and CSRR1.

There are 32 General Purpose Registers that are 32 bits wide. There are also 32 Floating-Point Registers. These registers are 64 bits wide to accommodate double precision Floating Point Results.

The General Purpose Registers do not have fixed memory-mapped addresses. Each Special Purpose Register has a register number. Specialized instructions are used to read and write these registers. The register number is used as an embedded field in instructions that are capable of addressing these registers.

30

System Level Features

4 External Interrupts InputsInternal Interrupt SupportWatchdogBus MonitorReal Time ClockClock Control to Individual ModulesPower Management (Nap, Doze, Sleep, Deep Sleep)

There are 4 external interrupts. One of these interrupts (IRQ0) is non-maskable. Please note that this pin cannot be left floating.

Another system level feature is the Internal Interrupt Support. Internal interrupts can be assigned to various interrupt levels and priority levels.

The Watchdog must be continually reset once it is enabled. If the software fails to reset the Watchdog in a specified amount of time, a WATCH DOG reset will occur. The purpose of the Watchdog Timer is primarily to reset the system in case the software stops working as expected. This means, if the software gets lost for some reason the WATCH DOG will cause a system reset to occur.

The Bus Monitor will create an exception if an internal access takes longer than allowed. This protects the system in case a memory access is made to a non-existent memory location.

The Real Time Clock is used to implement a clock function. This provides a “time of day” function as well as a calendar function.

Power Management allows the CPU to put the device into a low-power state. No code is executed in any of the low-power states. Depending upon the mode, different sections of the chip remain powered. In Deep Sleep, all system functions can be powered-down except for interrupt recognition. This is the lowest power state that the chip can achieve.

31

System Level Features

Common On-Chip Processor (COP) debug port

JTAG Access Port

The COP port is the primary port for InCircuit Debuggers and other development tools.

The JTAG port is used primarily for testing the device.

These ports have no real practical application in a user environment and are used primarily for test and debug purposes. These ports do not have much use in a user application. However, it would be unwise to ever underestimate the creativity of the customer base in finding utility for almost anything.

32

QuestionMatch each system level feature to its description. Drag each item on the left to its corresponding box on the right and then clickDone.

A

B

C

D

Bus Monitor

Power Management

Real Time Clock

Watch Dog must be continually reset once it is enabled

is used to implement a clock function.

will create an exception if an internal access takes longer than allowed.

allows the CPU to put the device into a low-power state.

D

C

A

B

Done Reset Show Solution

Here’s a question on the MPC5200 system features.

Answer:The Watchdog must be continually reset once it is enabled. The Bus Monitor will create an exception if an internal access takes longer than allowed. This protects the system in case a memory access is made to a non-existent memory location. The Real Time Clock is used to implement a clock function. This provides a “time of day” function as well as a calendar function. Finally, Power Management allows the CPU to put the device into a low-power state.

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Module Summary

Block DiagramTarget MarketsHiP7 TechnologyCore FeaturesSystem Level Features

Now that you have completed this module, you should have a general understanding of the MPC5200. You should be able to describe the MPC5200 block diagram and list some of the MPC5200 target markets. You should be able to describe HiP7 technology. Finally, you should have a general idea about the MPC5200 core and system level features.