1

Overview of Chapter 4Types of Sequential CircuitsStorage Elements• Latches• Flip-Flops

Sequential Circuit Analysis• State Tables• State Diagrams

Sequential Circuit Design• Specification• Assignment of State Codes• Implementation• HDL Representation

2

Sequential Circuits

A Sequential circuit contains:• Combinational Logic:

Implements a multiple-output switching functionInputs are signals from the outside.Outputs are signals to the outside.Other inputs, State or Present State, are signals from storage elements. The remaining outputs, Next State are inputs to storage elements.

• Storage elements: Latches or Flip-Flops

Combina-tionalLogicStorage

Elements

Inputs Outputs

StateNextState

3

Sequential Circuits

Combinatorial Logic• Next state function:• Next State = f(Inputs, State)

Combinatorial Logic• Outputs = g(Inputs, State)

Alternate output function (Moore):• Outputs = h(State)

Type of output function heavily influences the design

4

Types of Sequential CircuitsDepends on time at which inputs are observed by storage elements and state of storage elements changeSynchronous• Behavior defined from knowledge of its signals at

discrete instances of time• Storage elements affected by inputs and can change

state only in relation to a timing signal (clock pulsesfrom a clock)

Asynchronous• Behavior defined from knowledge of inputs an any

instant of time and the order in continuous time in which inputs change

• If clock just regarded as another input, all circuits are asynchronous!

• Nevertheless, the synchronous abstraction makes complex designs tractable!

5

Discrete Event SimulationIn order to understand the time behavior of a Sequential Circuit we use discrete event simulationRules:• Gates modeled by an ideal (instantaneous) function and

a fixed gate delay• Any change in input values is evaluated to see if it

causes a change in output value• Changes in output values are scheduled for after the

fixed gate delay• At the time for a scheduled output change, the output

value is changed along with any inputs connected to it

6

Simulated NAND GateExample: A 2-Input NAND gate with a 5 ns. delay:

Assume A and B have been 1 for a long timeAt time t=0, A changes to a 0 at t=8 ns, back to 1.

FA

BDELAY 5 ns.

F(Instantaneous)

t(ns) A B F(I) F Comment–∞ 1 1 0 0 A=B=1 for a long time

0 1⇒ 0 1 1⇐0 0 F(I) changes to 1

5 0 1 1 1⇐0 F changes to 1 after a 5 ns delay

8 1⇐0 1 1⇒0 1 F(Instantaneous) changes to 0

13 1 1 0 1⇒0 F changes to 0 after a 5 ns delay

7

Gate Models

Suppose we represent gates with delay n ns as follows:

n n n

8

Storing State

Consider a simple 2-input multiplexer:With function:• Y = A for S = 1• Y = B for S = 0

What would happen if we connect output signal Y to input signal A?

A

SB

Y

0

0.10.1

A

SB

Y0.1

9

Storing State (Continued)The circuit becomes:With function:• Y = B for S = 1, and• Y(t) dependent on

Y(t – 2) for S = 0

The simple combinational circuit has now become a sequential circuit because its output is a function of a time sequence of input signals!

0.10

0.1

0.1SB

Y

SB

Y

10

Storing State (Continued)Simulation example as input signals change with time. Changes occur every 100 ns, so that the 0.2 ns delays are negligible.

Y represents the state of the circuit, not just an output.

B S Y Comment0 1 0 Y = B when S = 11 1 11 0 1 Now Y “remembers” B for S = 00 0 1 No change in Y1 0 10 0 10 1 0 Y = B when S = 10 0 0 Y “remembers” B1 0 0 Even when B changes0 0 0

11

Storing State (Continued)

Suppose we place an inverter in the “feedback path.”The following behavior results:The circuit is said to be unstable.For S = 0 it isan oscillator!

0.10

0.10.1

SB

Y

B S Y Comment0 1 0 Y = B when S = 11 1 11 0 1 Now Y "remembers" B 1 0 0 Y at 0.2 ns later1 0 1 Y at 0.2 ns later1 0 0 Y at 0.2 ns later

0

12

Basic (NOR) S – R Latch

Cross-coupling two NOR gates gives the S – R Latch:Which has the time sequence behavior:

S (s e t)

R (re s e t)Q

Q'

R S Q Q' Comment0 0 ? ? We don't know0 1 1 0 "Set" Q to 10 0 1 0 Now Q "remembers" 11 0 0 1 "Reset" Q to 00 0 0 1 Now Q "remembers" 01 1 0 0 Both go low0 0 ? ? INSTABILITY

13

Basic (NAND) S –R Latch“Cross-Coupling”two NAND gates gives theS -R Latch:

Which has the time sequence behavior: R S Q Q' Comment

1 1 ? ? We don't know 1 0 1 0 "Set" Q to 1 1 1 1 0 Now Q "remembers" 1 0 1 0 1 "Reset" Q to 0 1 1 0 1 Now Q "remembers" 0 0 0 1 1 Both go high 1 1 ? ? INSTABILITY

Q

Q'

S (s e t)

R (re s e t)

14

Clocked S - R Latch

Adding two NAND gates to the basic S - R NAND Latch, we arrive at the Clocked S – R Latch:

S

R

Q

Q'

C

This has a time sequence behavior similar to the Basic S -R Latch except that:

• S and R are now active high signals (i.e. -- a "1" signal on S sets Q to 1) and

• The S and R inputs are only observed when the line C is high.

• C has the meaning "Clock" or "Clock Pulse".

15

Clocked S - R Latch (Continued)

Q(t) S R Q(t+1) Comment 0 0 0 0 No change 0 0 1 0 Clear Q 0 1 0 1 Set Q 0 1 1 ??? Indeterminate1 0 0 1 No change 1 0 1 0 Clear Q 1 1 0 1 Set Q 1 1 1 ??? Indeterminate

S

R

Q

Q'

C

The Clocked S-R Latch can be described by a table:

The table describes what happens after the clock [at time (t+1)] based on: current inputs (S,R) and current state Q(t).

16

Characteristic Equation for S - R LatchWe can describe the behavior of output Q at time (t+1) (immediately after one clock pulse) using a K-Map:

Q

S

R

0 1 23

4 5 67

X

X1 1

1

We can see that: Q(t+1) = S + R'⋅Q given that (both are not high at once): S⋅R = 0 The Clocked S – R Latch has the symbol:

C

R

S

Q

Q'

17

D LatchAdding an inverter to the S-R Latch, gives the D Latch:

DQ

Q'

C

Note that there are no "Indeterminate" states!

Q D Q(t+1) Comment 0 0 0 No change0 1 1 Set Q 1 0 0 Clear Q 1 1 1 Set Q

The graphic symbol for a D Latch is:

C

D Q

Q'

18

Latch and Flip-Flop TriggeringSo far, the latches we have talked about are "clocked" with an input pulse. Here are some possible wave forms:

• Positive Clock Pulse • Negative Clock Pulse• W = Pulse Width • Clock Period = Time

between referenced edges.

• Reference level is generally 50%.

• Rise and Fall times may be important as well.

0

1

0

1

Po s itive e dg e Ne g ative Edg e

Po s itive Clo c k Puls e

Ne g ative Clo c k Puls e

Clo c k Pe rio d

Clo c k Pe rio d w

w

19

System Level Clocking Consider a system comprised of ranks of latches or flip-flops connected by logic:

C

D Q

Q'

C

D Q

Q'

C

D Q

Q'

C

D Q

Q'

C

D Q

Q'

C

D Q

Q'

C

D Q

Q'

C

D Q

Q'

C

D Q

Q'

C

D Q

Q'

CLOCK CLOCK

If the Clock Period is TOO SHORT, some data changes will not propagate through the network. If the Clock Pulse Width is TOO LONG, some data will propagate through the second rank of latches!

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Master-Slave Flip-FlopOne way to solve the Clocking Problem is with a master-slave organization:

C

R

S

Q

Q'

C

R

S

Q

Q'

CR

S

Q

Q'

The complement of the clock is used to change the outputs.Now outputs change on C' only. Problem: One's catching in Master. Problem: Instability in Master. Another solution: Use D-FF's or Edge Triggering

21

Edge Triggered Flip-Flops

Edge triggered Flip-Flops are sensitive to a small window for data changes around the time of a clock edge. • Setup Time: The time

required for input data to be stable before the clock edge.

• Hold Time: The time data must remain stable after the clock edge.

C

D Q

Q' C

T Q

Q'C

J Q

Q'K

C

D Q

Q' C

T Q

Q'C

J Q

Q'K

Po s itive Edg e Trig g e re d FFs

Ne g ative Edg e Trig g e re d FFs

22

Flip-Flop Characteristic Tables

The Characteristic Tables: • Show current inputs. • Show current state implicitly. • Predict flip-flop state

AFTER CLOCKING.

Clocking conditions are: • Positive level triggered. • Negative level triggered. • Positive edge triggered. • Negative edge triggered.

NOTE: Proper clocking or flip-flop operation may be subject to conditions such as: • Set-up and hold times are met. • Simultaneous SR changes disallowed.

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Characteristic TablesJ K Q(t+1) Comment 0 0 Q(t) No change 0 1 0 Clear Q 1 0 1 Set Q 1 1 Q'(t) Complement Q

S R Q(t+1) Comment 0 0 Q(t) No change 0 1 0 Clear Q 1 0 1 Set Q 1 1 ??? Indeterminate

D Q(t+1) Comment 0 0 Clear Q 1 1 Set Q

T Q(t+1) Comment 0 Q(t) No change 1 Q'(t) Complement Q

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J-K Master Slave Flip Flop

Q

Q

S

RC

Q

Q

S

RC

Qm

QsJ

K

CP

Mas te r S laveTwo SR Latches driven by inverted clocks form a master-slave configuration.

Input logic forms the JK logic transition: • Set (master) = J•Qs' • Reset (master) = K•Qs

Master Set is possible if the slave Qs is currently "0" any time the clock CP is high!

Master Reset is possible if the slave Qs is currently "1" any time the clock CP is high!

This is referred to as One's Catching.

25

Master Slave SymbolsMaster-Slave Flip Flops are denoted by a line near the outputs. This highlights the fact that the slave changes AFTER the master clocking condition is deasserted.

C

J Q

Q'K

Po s itive Puls e Trig g e re d Mas te r/S lave FFs

C

S Q

Q'R

C

J Q

Q'K

Ne g ative Puls e Trig g e re d Mas te r/S lave FFs

C

S Q

Q'R

SR JKSR JK

26

Flip-Flop Conventions

A Bubble near a clock input denotes an active low assertion.

A Triangle near the clock input denotes edge sensitive.

A L-Shaped Line near the output denotes Master/Slave.

CK

A

A

CK

Q

Q

CQ

Q

CQ

Q

C

BB

CQ

Q

C

C

Q

Q'

27

Propagation DelayLogic gate, Latch and Flip-Flop timing parameters: TPLH: Propagation time low-to-high -- the time required for an output to transition from a low logic level to a high logic level from an input event (usually clock). TPHL: Propagation time high-to-low -- the time required for an output to transition from a high logic level to a low logic level from an input event (usually clock). Clock Skew: Difference in clock arrival times at different flip-flops.Tsu Set-up time: Time data must be stable at FFs before the clock. Minimum clock period is set by: MAX(TPHL,TPLH) + LogicDelay + Tsu Hold Time and Clock Skew constrain the minimum logic plus flip-flop delay.

28

Calculating Clock FrequencyGiven the network below, assume signal A is changing from "1" to "0":

CD Q

Q'

CLOCK CLOCK

A B C D

CD Q

Q'

A

B

C

D

tpHL (Flip-Flo p)

tpHL (Log ic )

tpHL (Lo g ic )

tpHL (Lo g ic )

ts u (Flip-Flo p)

CLOCK

Clo c k Pe rio dClock Period =

tPHL(Flip-Flop) +3*tPHL(Logic) + tsu (Flip-Flop)

Frequency = 1/(Clock Period)

29

Calculating Clock Frequency…Contd

CD Q

Q'

CLOCK CLOCK

A B C D

CD Q

Q'

A

B

C

D

tpLH (Flip-Flo p)

tpLH (Lo g ic )

tpLH (Lo g ic )

tpL H(Lo g ic )

ts u (Flip-Flo p)

CLOCK

Clo c k Pe rio d

Given the network below, assume signal A is changing from "0" to "1":

Frequency = 1/(Clock Period)

Clock Period = tPLH(Flip-Flop) +3*tPLH(Logic) + tsu (Flip-Flop

We ususally pick MAX(tPHL, TPLH).

30

Sequential Circuit Analysis

General Model• Current State at

time (t) is stored in an array of flip-flops.

• Next State at time (t+1) is a Boolean function of current state and inputs.

• Outputs at time (t) are a Boolean function of current state (t) and (sometimes) current inputs (t).

OutputsCombinationalLogicStorage

Elements

Inputs

StateNextState

CLK

31

Example (from Fig. 4-18)

Input: x(t)Output: y(t) State: A(t), B(t)What is the Output Function?What is the Next State Function?

C

D Q

Q'

C

D Q

Q'

y

x A

A

B

CP

32

Example (Fig. 4-18) (Continued)Boolean Equations for the functions:• A(t+1) = A(t)x(t)

+ B(t)x(t)• B(t+1) =A(t)x(t)• y(t) =x(t)(B(t) + A(t))

C

D Q

Q'

C

D Q

Q'

y

x A

A'

B

CP

Next State

Output

33

Example (Fig. 4-18) (Continued)

Where in time are inputs, outputs and states defined?

0.0 53ns 106ns 159ns 212ns 265ns 318ns 371ns 424ns

l RESET..........

l CLOCK..........

l X..............

l NA.............

l NB.............

l A..............

l B..............

l Y..............

l

Functional Simulation - Fig. 4-18 Mano & Kime

t t+1 t+2 t+3

00

0

0

1

1

1

0

34

State Table Characteristics

State table – a multiple variable function table with the following four sections:• Present State – the values of the state

variables for each allowed state.• Input – the input combinations allowed.• Next-state – the value of the state at time (t+1)

based on the present state and the input.• Output – the value of the output as a function

of the present state and (sometimes) the input.From the viewpoint of a truth table:• the inputs are Input, Present State• and the outputs are Output, Next State

35

Example: State Table (Fig. 4-18)The STATE TABLE can be filled in using the next state and output equations: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) =A (t)x(t) y(t) =x (t)(B(t) + A(t))

Present State Input Next State OutputA(t) B(t) x(t) A(t+1) B(t+1) y(t)

0 0 0 0 0 00 0 1 0 1 00 1 0 0 0 10 1 1 1 1 01 0 0 0 0 11 0 1 1 0 01 1 0 0 0 11 1 1 1 0 0

36

Alternate State Table2-dimensional table that matches well to a K-map. Present state rows and input columns in Gray code order. • A(t+1) = A(t)x(t) + B(t)x(t)• B(t+1) =A (t)x(t)• y(t) =x (t)(B(t) + A(t))

Present State

Next Statex(t)=0 x(t)=1

Outputx(t)=0 x(t)=1

A(t) B(t) A(t+1)B(t+1) A(t+1)B(t+1) y(t) y(t)0 0 0 0 0 1 0 00 1 0 0 1 1 1 01 0 0 0 1 0 1 01 1 0 0 1 0 1 0

37

State Diagram CharacteristicsThe Boolean state variables are a vector of n bits.Not all 2n states are necessarily used!Similarly not all input and output combinations are used.The state variables may need to be initialize to a valid, appropriate initial state.Examples:• A system with 10 states requires a minimum of 4 bits (3

bits gives only 8 symbols). • BCD coded inputs can have 16 combinations, only 10 of

which have meaning.

38

State DiagramsThe sequential circuit function can be represented in graphical form as a state diagram with the following components:• A circle with the state name in it for each state• A directed arc from the Present State to the

Next State for each state transition• A label on each directed arc with the Input

value which causes the state transition, and• A label:

On each circle with the output value produced, orOn each directed arc with the output value produced.

39

State Diagrams

Label form:• On circle with output included:

state/outputMoore type output depends only on state

• On directed arc with the outputincluded:

input/outputMealy type output depends on state and input

40

State Diagram Example

Which type?Gets confusing as circuit grows in size.For small circuits, usually easier to understand than the state table.Try drawing state diagram for mod 4 counter and toggle (T) flip-flop

A B0 0

0 1 1 1

1 0

x=0/y=1 x=1/y=0

x=1/y=0x=1/y=0

x=0/y=1

x=0/y=1

x=1/y=0

x=0/y=0

41

Flip-Flop Input Functions

The D-Flip-Flop easy to analyze since it has only one input. Other FFs such as the JK and SR have two inputs.Convention used in text:• First Letters designate the FF input function.• Second Letters (or subscript) designate the

state variable.Example with Two JKFFs:• JA = B KA =Bx JB = x KB = Ax +A x

Example 4-18 with Two DFFs: • DA = A x + B x DB =A x y = (A + B)x

42

Analysis with Other Flip-Flops

With a D Flip-Flop:• Next state obtained directly from the

flip-flop input equation for Di

With a JK, T or SR Flip-Flop:• Obtain the values for each flip-flop input

in terms of present state and input values

• Use the corresponding flip-flop characteristic table from Table 4-1 to determine the next state value of the flip-flop

43

Characteristic Tables

S R Q(t+1) Comment0 0 Q(t) No change0 1 0 Clear Q1 0 1 Set Q1 1 ? IndeterminateComplement Q

J K Q(t+1) Comment0 0 Q(t) No change0 1 0 Clear Q1 0 1 Set Q1 1 Q(t)

Complement Q

T Q(t+1) Comment0 Q(t) No change1 Q(t)

D Q(t+1) Comment0 0 Clear Q1 1 Set Q

44

JK Flip-Flop Circuit AnalysisStep 1: Write the Boolean expression for each flip-flop input.For flip-flop A:JA = KA= For flip-flop B:JB = KB =

CJ Q

Q'K

x A

BCP C

J Q

Q'K

JA

KA

JB

KB

45

JK Flip-Flop Analysis (Cont.)

Step 2: Using the diagram or equations, fill in the flip-flop inputs.

JA = Bx KA = B JB =x KB = A x

Present State

Input Next State

Flip-Flop Inputs

A B x A B JA KA JB KB0 0 0 0 0 1 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

CJ Q

Q'K

x A

B

CP CJ Q

Q'K

JA

KA

JB

KB

46

JK Flip-Flop Analysis (Cont.)

Step 3: By using JK Characteristic Table, the J and K inputs and the present state from the table, fill in the next state in the table for each flip flop.• QA(t) = 0; JA =0; KA = 0;

Implies QA(t+1) = 0 (No Change)

• QB(t) = 0; JB =1; KB = 0;Implies QB(t+1) = 1(Set Q)

J K Q(t+1) Comment0 0 Q(t) No change0 1 0 Clear Q1 0 1 Set Q1 1 Q(t) Comp. Q

PresentState

Input NextState

Flip-FlopInputs

A B x A B JA KA JB KB0 0 0 0 1 0 0 1 00 0 1 0 0 0 10 1 0 1 1 1 00 1 1 0 1 0 11 0 0 0 0 1 11 0 1 0 0 0 01 1 0 1 1 1 11 1 1 0 1 0 0

47

JK Flip-Flop Analysis (Cont.)

The result of completion of Step 3:

For convenience, discard the flip-flop input columnsWhat is the output function?

Present State

Input Next State

Flip-Flop Inputs

A B x A B JA KA JB KB0 0 0 0 1 0 0 1 00 0 1 0 0 0 0 0 10 1 0 1 1 1 1 1 00 1 1 0 0 0 1 0 11 0 0 1 1 0 0 1 11 0 1 1 0 0 0 0 01 1 0 0 0 1 1 1 11 1 1 0 1 0 1 0 0

48

JK Flip-Flop Analysis (Cont.)

Step 4: From the diagrams or equations, place the output values in the table:

PresentState

Input NextState

A B x A B0 0 0 0 10 0 1 0 00 1 0 1 10 1 1 0 01 0 0 1 11 0 1 1 01 1 0 0 01 1 1 0 1

A B

Output

0 00 00 10 11 01 01 11 1

49

Additional Concepts

Characteristic EquationsMoore and Mealy Models• Diagram Examples• Table Examples

50

Characteristic EquationsCan be used instead of characteristic tables for transforming flip-flop inputs to next state information

Q(t+1) = JQ(t) +KQ(t) Q(t+1) = S +R Q(t)

Q(t+1) = T ⊕ Q(t) Q(t+1) = D

Complement Q

J K Q(t+1) Comment0 0 Q(t) No change0 1 0 Clear Q1 0 1 Set Q1 1 Q(t)

S R Q(t+1) Comment0 0 Q(t) No change0 1 0 Clear Q1 0 1 Set Q1 1 ? Indeterminate

Complement Q

T Q(t+1) Comment0 Q(t) No change1 Q(t)

D Q(t+1) Comment0 0 Clear Q1 1 Set Q

51

Moore and Mealy Models

Sequential Circuits or Sequential Machines are also called Finite State Machines (FSMs). Two formal models exist:

Mealy ModelNamed after G. MealyOutputs are a function of inputsAND statesUsually specified on the state transition arcs.

Moore ModelNamed after E.F. Moore.Outputs are a function ONLY of statesUsually specified on the states.

52

Moore and Mealy Example Diagrams

Mealy Model State Diagram maps inputs and state to outputs

Moore Model State Diagram maps states to outputs

0 1

x=1/y=1

x=1/y=0

x=0/y=0

x=0/y=0

2/1

x=1x=1

x=0

x=0

x=0

0/0

1/0x=1

53

Moore and Mealy Example Tables

Mealy Model State Table maps inputs and state to outputs

Moore Model State Table maps state to outputs

Present State

Next Statex=0 x=1

Outputx=0 x=1

0 0 1 0 01 0 1 0 1

Present State

Next Statex=0 x=1

Output

0 0 1 01 0 2 02 0 2 1