Idongesit Ebong (1-1)Jenna Fu (1-2)

Bowei Gai (1-3)Syed Hussain (1-4)Jonathan Lee (1-5)

Design Manager: Myron Kwai

Overall Project Objective:Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID)

technology while creating a quicker, more convenient shopping experience.

Presentation #10:

Smart Cart 525

Stage X: 28 Mar. 2005Chip Level Layout 2

Status Design Proposal

Project chosen Verilog obtained/modified

Architecture Proposal Behavioral Verilog simulated

Size estimates/floorplanning Gate-level implementation simulated in Verilog Floorplan and more accurate transistor count

Schematic Design Component Layout Functional Block Layout

DRC of functional blocks LVS of functional blocks

Chip Level Layout Full chip LVS!!!!

Simulations (50%) Schematic with loaded inputs/outputs Extracted, ExtractedRC view

Design Decisions

Changed register type after having problems with Analog Simulation

Adding more buffers to design

Previously (320.220 x 293.355)

Currently (323.955 x 296.1)

Design Specifications

Area: 95,923 μm2

# of Transistors: 21,944

Density: (transistors/μm2)

.23

Aspect ratio: 1.09

LVS VerificationNet-list summary for /afs/ece.cmu.edu/usr/bgai/cds/LVS/layout/netlist count

6965 nets87 terminals7752 pmos14192 nmos

Net-list summary for /afs/ece.cmu.edu/usr/bgai/cds/LVS/schematic/netlist count

7066 nets87 terminals101 cds_thru7752 pmos14192 nmos

Terminal correspondence points 1 Clk 2 Clk2 3 done 4 gnd! 5 input16bit<0> 6 input16bit<10> 7 input16bit<11> 8 input16bit<12> 9 input16bit<13> 10 input16bit<14> 11 input16bit<15> 12 input16bit<1> 13 input16bit<2> 14 input16bit<3> 15 input16bit<4> 16 input16bit<5> 17 input16bit<6> 18 input16bit<7> 19 input16bit<8> 20 input16bit<9>

21 lastPrice<0> 22 lastPrice<1> 23 lastPrice<2> 24 lastPrice<3> 25 lastPrice<4> 26 lastPrice<5> 27 lastPrice<6> 28 lastPrice<7> 29 lastPrice<8> 30 lastPrice<9> 31 operationCode<0> 32 operationCode<1> 33 operationCode<2>

34 out<0> 35 out<10> 36 out<11> 37 out<12> 38 out<13> 39 out<14> 40 out<15> 41 out<16> 42 out<17> 43 out<18> 44 out<19> 45 out<1> 46 out<20> 47 out<2> 48 out<3> 49 out<4> 50 out<5> 51 out<6> 52 out<7>

53 out<8> 54 out<9> 55 text_out<0> 56 text_out<10> 57 text_out<11> 58 text_out<12> 59 text_out<13> 60 text_out<14> 61 text_out<15> 62 text_out<16> 63 text_out<17> 64 text_out<18> 65 text_out<19> 66 text_out<1> 67 text_out<20> 68 text_out<21> 69 text_out<22> 70 text_out<23> 71 text_out<24> 72 text_out<25> 73 text_out<26> 74 text_out<27> 75 text_out<28> 76 text_out<29> 77 text_out<2> 78 text_out<30> 79 text_out<31> 80 text_out<3> 81 text_out<4> 82 text_out<5> 83 text_out<6> 84 text_out<7> 85 text_out<8> 86 text_out<9> 87 vdd!

The net-lists match.

layout schematicinstances

un-matched 0 0rewired 0 0size errors 0 0pruned 0 0active 21944 22045total 21944 22045

netsun-matched 0 0merged 0 0pruned 0 0active 6965 7066total 6965 7066

terminalsun-matched 0 0matched butdifferent type 0 0total 87 87

Simulations: Top (Total Output--Schematic)

Simulations: Top (Last Price Output--Schematic)

Simulations: Encryption (Final Output--Schematic)

Simulations: Encryption (ROM)

ExtractedRise Time: 941.308 psFall Time: 698.145 ps

Simulations: Arithmetic Blocks

Multiplier Schematic

Rise Time: 144.599 psFall Time: 94.4327 psPropagation Time: 425 ps

ExtractedRCRise Time: 163.18 psFall Time: 93.65 psPropagation Time: 3.53 ns

Adder Schematic

Rise Time: 144.708 psFall Time: 96.0891 psPropagation Time: 512.017 ps

ExtractedRC coming soon

Simulations: SRAM

SchematicRise Time: 192.883 psFall Time: 103.013 psProp. Time: 1.112 ns ExtractedRCRise Time: 275.000 psFall Time: 147.000 psProp. Time: 947.000 ps

Problems & Questions

White space reduction Buffers expected to fill some of this space

Adder is weird Having to go through so many transmission gates may

be a problem