Introduction to Network-on-Chip&

Low Power Routing algorithms

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Presented by

Professor AJAL A J

Traditional SoC Issues• Variety of dedicated interfaces• Design and verification complexity• Unpredictable performance• Many underutilized wires

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DMA CPU DSP

Bridge

IO IO IOC

A

B Peripheral Bus

CPU Bus

Control signals

NoC: A paradigm Shift in VLSI

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s

s

s

s

s s

s

s

Module

Module

s

Module

From: Dedicated signal wires To: Shared network

Point- To-point Link

Network switch

Computing Module

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Processingelement

NetworkInterface

Router

Inputbuffers

directionallinks

NOC- Working

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NOC- Working

Typical NoC Design Flow

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Determine routing and adjust link capacities

Low Power Routing algorithms

Network Topology

Direct In-direct

Direct Topology:

Topology:

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PE PEPE PE

PE PEPE PE

PE PEPE PE

R R R R

R R R R

PE PEPE PE

R R R R

R R R R

The main problem with the mesh topology is its long diameter that has negative effect on communication latency.

1. Mesh

Topology:

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PE

PE

PE

PE PE

PE

PE

PE

SW

2.Octagon

Indirect Topology:

Topology:

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SW

SWSW

SWSW SWSW

PEPE PEPE PEPE PEPE

1.Tree

NoC Routing

Routing algorithm determine path(s) from source to destination. Routing must prevent deadlock, livelock , and starvation.

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Deadlock, Livelock, and Starvation

Deadlock: A packet does not reach its destination, because it is blocked at some intermediate resource.

Livelock: A packet does not reach its destination, because it enters a cyclic path.

Starvation: A packet does not reach its destination, because some resource does not grant access (wile it grants access to other packets).

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Low Power Routing algorithms

1. XY Routing2. Wormhole Routing

Routing examplesRouting examples

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PE DPE PE

PE PEPE PE

PE PEPE PE

R R R R

R R R R

PE PES PE

R R R R

R R R R

Dimension Ordered Routing (XY Routing)

X

Y

S

D

C om m and

Address

Payload

Wormhole Packet:

Flit

Flit

Flit

Wormhole RoutingFor reduced buffering

Flit (routing info)

Flit

Flit

Wormhole Router

R outer

Module

Moduleor

another router

CR

OS

S-B

AR

SchedulerControlRouting CREDIT

B u ffe rsSIG NAL

RT

RD/W R

BLO CK

SIGNAL

RT

RD/W R

BLO CK

CREDIT

SchedulerControlRouting CREDIT

SIG NAL

RT

RD/W R

BLO CK

SIGNAL

RT

RD/W R

BLO CK

CREDIT

O utput portsInput ports

Status and Open Problems• Power

– complex NI and switching/routing logic blocks are power hungry– several times greater than for current bus-based approaches

• Latency– additional delay to packetize/de-packetize data at NIs– flow/congestion control and fault tolerance protocol overheads– delays at the numerous switching stages encountered by packets– even circuit switching has overhead (e.g. SOCBUS)– lags behind what can be achieved with bus-based/dedicated wiring

• Lack of tools and benchmarks• Simulation speed

– GHz clock frequencies, large network complexity, greater number of PEs slow down simulation

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Trends• Move towards hybrid interconnection fabrics

– NoC-bus based– Custom, heterogeneous topologies

• New interconnect paradigms– Optical– Wireless– Carbon nanotube

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THANK YOU!