POLITECNICO DI MILANO

Marco D. Santambrogio

marco.santabrogio@polimi.it

Metodologie di Progettazine Hardware e

Software

Reconfigurable ComputingReconfigurable Computing- Overview- Overview - -

2

OutlineOutlineReconfigurable Computing

An overviewFPGAConfiguration bitstreamPartitioning and scheduling

MicroLABMPHS Projects

EarendilLimboWAREVIRGILYaRA with LeonDRPCScheduling for reconfigurable architectureLinux and reconfiguration

DRESDPhilosophyTeam and meetingWebIn the world

Questions?

3

What’s next…What’s next…Reconfigurable Computing

An overviewFPGAConfiguration bitstreamPartitioning and scheduling

MicroLABMPHS Projects

EarendilLimboWAREVIRGILYaRA with LeonDRPCScheduling for reconfigurable architectureLinux and reconfiguration

DRESDPhilosophyTeam and meetingWebIn the world

Questions?

4

ReconfigurationReconfiguration

The process of physically altering the location or functionality of network or system elements. Automatic configuration describes the way sophisticated networks can readjust themselves in the event of a link or device failing, enabling the network to continue operation.

Gerald Estrin, 1960

5

Reconfiguration in everyday Reconfiguration in everyday lifelife

Soccer

Hockey

Football

(Partial – Static)

(Complete – Static)

(Partial – Dynamic)

6

Where we are workingWhere we are working

Partial Total

7

Where we are workingWhere we are working

Partial Embedded

fix

8

Where we are workingWhere we are working

Single Device Distributed System

9

FPGA: overviewFPGA: overview

CLB

IOB

Switch Box

10

FPGA: CLBFPGA: CLB

VCC

Switch BoxSLICE

TBUF

Y

X6766

75

74

SLICE_X66Y74

11

FPGA: CLB-coordinatesFPGA: CLB-coordinates

12

FPGA: Column-wise StructureFPGA: Column-wise Structure

5 kinds of column: Clock, RAM, I-RAM, I/O, CLB

Composed of a variable number of frames

Double addressing: Major Address, Minor

Address

Major Address CLB Column

13

FPGA: Configuration BitstreamsFPGA: Configuration Bitstreams

Represents Represents initial initial module module locationlocation

Cyclic Cyclic Redundancy Redundancy Check is also Check is also involvedinvolved

14

FPGA: Frames-coordinatesFPGA: Frames-coordinates

15

Architecture ModelArchitecture Model

Due to technology limitations (or specification limitations?) the smallest reconfigurable portion is a column 1 CLB wide --> |U|=68 reconfigurable units:

1 CLB

…FPGA

16

Architecture ModelArchitecture Model

Each reconfigurable unit contains

Also, it can contain execution units requiring

CLBs

17

Architecture ModelArchitecture Model

Reconfiguration takes an affine time with respect to the size (in CLBs) of the reconfigured area:

Or, in terms of clock cycles:

18

SpecificationSpecification

We are given a directed acyclic graph (DAG)

where O is the set of operations and P are the precedences.

We also add a start node oS and a sink node oE so that all the other nodes are dominated by oS as post-dominated by oE.

19

Temporal partitioningTemporal partitioning

Temporal partitioningNo partial reconfiguration: all the chip is running, then it is stopped, totally reconfigured, and then runs again.

20

Temporal partitioningTemporal partitioning

Can be highly suboptimal:

21

Time-Space partitioningTime-Space partitioning

22

LoopsLoops

Tasks being repeated several times are commonly exploited to hide reconfiguration overhead.

23

QuestionsQuestions