Motorola 680x0aka

Motorola 68k Family

Overview

• CISC Architecture

• 16 General Purpose Registers– 8 Data Registers (D0 – D7)– 8 Address Registers (A0 – A7)– A7 is the Stack Register– Address and Data Registers can’t be

interchanged

• 24 bit Program Counter

Flags

• Flags stored in a 16 bit “System Register”

• User Byte – Bits 0 – 7 aka Flagregister

• System Byte – Bits 8 – 15

• Special Bits• Bit 0 - Carry Flag - C• Bit 1 – Overflow - V• Bit 2 – Zero Flag - Z• Bit 3 – Negative Flag - N• Bit 4 – Extended Flag - X

User Byte

• Carry, Overflow and Zero flags - self explanatory

• Negative Flag - set if highest bit is set in 2s compliment

• Extended Flag - This flag is a copy of the carry-flag, but it won't be changed in all operations where C is changed. This allows you to first make a check (that will set C and X), then some other instructions that will change the C flag but not the X flag, and THEN you can make the branch according to the flags, which means you can use the X flag.

System Byte

• Bits 8 – 10; Interrupt Mask– Interrupt Mask used to set priority of interrupt– 0 0 0(lowest) – 1 1 1(highest)

• Bit 13 – Supervisor Bit– When set, gives more access to instructions and to

the system byte. Used as a security measure and for handling interrupts

• Bit 15 – Trace Bit– Sets interrupts after each instruction – used in

debuggers

Data Storage

• Big Endian• All memory must be aligned• Supports Binary and BCD

– Similar to Packed Decimal– Later versions support floating point with a special

add on coprocessor• Special suffix to let CPU know how much data

used in instruction– Eg: Move.B – Move a byte– Move.W – Move word– Move.L – Move longword

Addressing Modes

• 14(!!) different addressing modes– Data Register Direct – Address Register Direct – Address Register Indirect – Address Register Indirect with Post-Increment – Address Register Indirect with Pre-Decrement – Address Register Indirect with Displacement – Address Register Indirect with Index – Absolute Short – Absolute Long – Program Counter with Displacement – Program Counter with Index – Immediate – Status Register – Condition Code Register

Floating Point Unit

• Eight 16 bit floating point data registers• 16 bit floating point control register

– Enable Byte(8-15), acts as exception/interrupt control

– Mode Byte(0-7), controls selectable rounding modes

• 32 bit floating point status register• 32 bit floating point instruction address

register

The Stack

• Stack stored in system memory• No push and pop instructions• Instead, use:

– Move D0, -(A7) for a push– Move a7+, D0 for a pop

• Note: When popping D0’s top 16 bits must be cleared

• Is there a simpler way to push multiple registers?

More on the Stack

• Yes, special instruction Movem pushes multiple registers– movem d0-d4/a0-a2,-(a7) for a push– movem (a7)+,d0-d4/a0-a2 for a pop

• Most commonly used during procedure calls• Another way to put things on the stack is with

the PEA instruction. It pushes an effective address on the stack, used when pushing pointers. This will decrease A7 with 4 (the size of a pointer).

Instruction Set

• Interesting Instructions– Tst – Compares an operand to 0– Tas – Test and Set, used for “critical” sections– Ext - Makes a sign extension, byte to word or

word to longword– Exg – Exchange contents of two registers– Lea – Calculates effective address and stores

in address register– Pea – Calculates an address and puts it on

the stack

More Instructions

• Contains all the normal logical, shift and rotation instructions

• Bit Manipulation:– BTST - Tests a bit– BSET - Tests a bit, then set it (1)– BCLR - Tests a bit, then reset it (0)– BCHG - Tests a bit, then invert it (0 -> 1, 1 ->

0)

BCD instructions

• Special instructions to manipulate BCD data– ABCD - BCD addition– SBCD - BCD subtraction– NBCD - BCD negate

• “Illegal” causes an interrupt

• Link creates a stack frame, and unlink deletes it

Program Control

• Instructions that alter program execution– Bcc - A group of 15 instruction that branches

depending on the flags.– DBcc - 15 instructions that perform loops.– Scc - 16 instructions that will set/reset a byte

depending on the flags.– BSR, JSR - Branch and Jump Subroutine calls.– RTS - Return from a subroutine.– RTR - Pops the PC and the flags from the stacks.

System Control

• These instructions require the Supervisor bit to be set– MOVE USP - Gives a program in supervisor mode

access to the stack pointer in user mode– RESET - Restores the peripheral units.– RTE - Returns from an interrupt.– STOP - Stops the execution until a given interrupt

occurs– CHK, TRAPV - Finds fatal program errors.– TRAP - 16 instructions that give a program in user

mode the possibility to call another program in supervisor mode.

Later Upgrades

• The 68008 was an 8 bit version of the 68000– Reduced data bus to 8 bits and addresses to

20 bits

• The 68010 was introduced in 1982– Added virtual memory, able to restart

interrupted instructions– Added a special loop mode

• Allowed small decrement and branch loops to be executed in the instruction fetch buffer

68020

• The 68020 was introduced in 1984– Expanded external data and address bus to

32 bits– Simple 3 stage pipeline– 256 byte cache (loop buffer)– Supported either segmented or paged

memory, but not both– Added several new registers (specialized)– Program counter can address 4GB of memory

68030 and 68040

• The 68030 was introduced in 1987– Integrated the paged memory management unit onto

the CPU– Includes 128 word data cache– Includes 128 word instruction cache

• The 68040 was introduced in 1991– Added Harvard busses with 4k for each instruction

and data– Extended pipeline, 6 stages– On chip Floating Point Unit

68060

• The last of the 68k family was introduced in 1994– Contained two 10 stage pipeline– 3 execution units, 2 integer 1 floating point– Cache size doubled to 8k for I-cache and D-cache– Register to Register operations can execute 2 cycles

early using the address stage of pipeline– Able to shut down pipelines not in use to save power,

total power 3.3V, lower than 68040– Branch Cache lowers latency of branch operations

The Future?

• Embedded market – palm pilots, scientific calculators, and other simple machinery– Recent Palm Pilot CPUs have been using

PowerPCs

• Used in old Macintosh computers– Also being replaced by PowerPC architecture

• Not much of a market left for these processors

References

• http://www.ticalc.org/pub/text/68k/• http://www3.sk.sympatico.ca/jbayko/cpu3.html• http://www.fhi-berlin.mpg.de/amiga/ar/ar114/p1-

10.HTML• http://www.lowendmac.com/tech/chips.shtml