Model to Code, Made Simple and Easy · 5 AirSonea device, which connects Philips Healthcare MRI...

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Transcript of Model to Code, Made Simple and Easy · 5 AirSonea device, which connects Philips Healthcare MRI...

1© 2015 The MathWorks, Inc.

Sebastien Dupertuis

Application Engineer

Applications Engineering Group

MathWorks Switzerland

June 11, 2015

Model to Code, Made Simple and Easy

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Challenges to bring an idea into real hardware

People

Software Developers

Specifications

Schematics

Diagrams

Algorithms

…Hardware Engineers

Mechanical Engineers

Tools?

Investments?

ROI?

Manager

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switch(idea)

{

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case ‘Applications’:

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Philips Healthcare MRI scannerAirSonea device, which connects

to a patient’s smartphone

Sonova’s hearing aid and

cochlear implant solutions

Toyota engine

Alstom Grid’s HVDC demonstrator system

with power converter modules

http://nl.mathworks.com/company/user_stories/

The HB-SIA aircraft on a test

flight over San Francisco Bay Photo © Solar Impulse | Revillard | Rezo.ch

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case ‘Programming’:

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ASCIIMATLAB

C

C++

ASSEMBLYVHDL

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case ‘Hardware’:

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MCU /

DSP

ARM®

Analog Devices®

Atmel®

Freescale™

Infineon®

Intel®

Microchip®

NXP™

Renesas®

STMicroelectronics®

Texas Instruments™

Xilinx®

ALTERA®

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case ‘Operating Systems’:

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OS Embedded Linux®

VxWorks®

OSEK-OSMicrosoft® Windows Embedded

Android™

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case ‘Standards’:

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STANDARDS

AUTOSARMISRA AC AGC

ISO 26262

IEC 61508

EN 50128

DO-178B/C

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default :

printf(“Wrong session?”);

}

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MBD_Overview();

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TE

ST

&

VE

RIF

ICA

TIO

N

INTEGRATION

IMPLEMENTATION

ANALYSIS – SPECIFICATION- DESIGN

MODEL

RESEARCH

ACTIVITIES

REQUIREMENTS

DOCUMENTS

MCU DSP FPGA ASIC

Structured

TextVHDL, VerilogC, C++

Architecture

Algorithms

Schematics

TEST

CASES

Environment

Constraints

Physical Domains

TEST

CASES

PLC PAC

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IMPLEMENTATION

MCU DSP FPGA ASIC

Structured

TextVHDL, VerilogC, C++

PLC

TE

ST

&

VE

RIF

ICA

TIO

N

INTEGRATION

ANALYSIS – SPECIFICATION- DESIGN

MODEL

RESEARCH

ACTIVITIES

REQUIREMENTS

DOCUMENTS

MCU DSP FPGA ASIC

Structured

TextVHDL, VerilogC, C++

Architecture

Algorithms

Schematics

TEST

CASES

Environment

Constraints

Physical Domains

TEST

CASES

PLC PAC

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Model2Code();

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Simulink

Modelling Languages

MATLAB

Stateflow

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MATLAB

Unified

representation

C++ Code

HDL Code

C Code

PLC Code

Mathematical

enginesTest cases

Find design

errors

Fixed-point

autoscaling

Code Generation Common Internal Architecture

Simulink

Stateflow

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case ‘Code Generation – Top 5’:

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In-the-Loop Verification Methodologies

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Non-Real-Time Synchronization

with Host at Each Time Step

Execution History

• Logged signal results comparison

• Code coverage

• Execution timing

Communication

Gateway

Software- and Processor- in-the-LoopSIL and PIL

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Code

Generation

Hard Real-Time Execution

Logging and

Tuning via Host

Hardware-in-the-LoopHIL, Rapid Prototyping

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FPGA-in-the-LoopFIL, Test Bench Simulation

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Incremental Build Process

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Incremental Build Process

Significantly saves time

Only build blocks that have changed

Helps with partitioning and

componentization

Scalability!

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Simulink Data Dictionary

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Componentization

Scalability and performance

Change tracking and

differencing

Integration with Simulink

Projects

Code generation

Manage data outside of base workspace

Code Generation for Simulink Data Dictionary

Simulink

Model 1

Model 2

Model 3

SLX

FileSLX

FileSLX

File

SLDD

FileSLDD

FileSLDD

FileGlobal Data

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Profiling of Generated Code

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Measure Execution Time

Supports

– SIL and PIL

– Tasks and functions

– HTML reports

Identify hot spots, worst-case execution

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Intellectual Property Protection

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Password Protected Models

Support options

– Simulation: Allow Accelerator mode

– Code generation:

Include obfuscated code to support

code generation

– Read-only view: Web view of model

– Password protection: Access

protected by password

Protect design IP for models and

generated code

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case ‘Targets’:

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Hardware Support Packages

HW Support Packages are:

– Downloadable from

MathWorks websites

– Available for free with required

base product

– Supported by technical support

HW Support Package

manages:

– Licenses

– 3rd-party software installation

– Hardware setup

36http://nl.mathworks.com/services/consulting/proven-solutions/developing-embedded-targets.html

Services

Automate compile, build, and download

Integrate device drivers and RTOS with Simulink

Optimize code replacements to your target

Verify and validate code execution results

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case ‘Getting FREEd’:

}

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Programming an heterogeneous systemZynq Platform

ARM

FPGAAXI AXI